// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_imu_rds_mess_stage_mux_only.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// choice is available it will apply instead, Sun elects to use only
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// software where a choice of GPL license versions is made
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// ========== Copyright Header End ============================================
module dmu_imu_rds_mess_stage_mux_only
err_cor_mapping_select_pulse,
err_cor_mapping_select_pulse_out,
err_nonfatal_mapping_select_pulse,
err_nonfatal_mapping_select_pulse_out,
err_fatal_mapping_select_pulse,
err_fatal_mapping_select_pulse_out,
pm_pme_mapping_select_pulse,
pm_pme_mapping_select_pulse_out,
pme_to_ack_mapping_select_pulse,
pme_to_ack_mapping_select_pulse_out,
daemon_csrbus_wr_data_in,
daemon_csrbus_wr_data_out,
//====================================================
//====================================================
input clk; // Clock signal
input [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0; // Read Data
input err_cor_mapping_select_pulse; // select
output err_cor_mapping_select_pulse_out; // select
input err_nonfatal_mapping_select_pulse; // select
output err_nonfatal_mapping_select_pulse_out; // select
input err_fatal_mapping_select_pulse; // select
output err_fatal_mapping_select_pulse_out; // select
input pm_pme_mapping_select_pulse; // select
output pm_pme_mapping_select_pulse_out; // select
input pme_to_ack_mapping_select_pulse; // select
output pme_to_ack_mapping_select_pulse_out; // select
input daemon_csrbus_wr_in; // csrbus_wr
output daemon_csrbus_wr_out; // csrbus_wr
input [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data
output [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // SW write
output [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data
output rst_l_out; // HW reset
//====================================================
//====================================================
wire clk; // Clock signal
wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0; // Read Data
wire err_cor_mapping_select_pulse; // select
wire err_cor_mapping_select_pulse_out; // select
wire err_nonfatal_mapping_select_pulse; // select
wire err_nonfatal_mapping_select_pulse_out; // select
wire err_fatal_mapping_select_pulse; // select
wire err_fatal_mapping_select_pulse_out; // select
wire pm_pme_mapping_select_pulse; // select
wire pm_pme_mapping_select_pulse_out; // select
wire pme_to_ack_mapping_select_pulse; // select
wire pme_to_ack_mapping_select_pulse_out; // select
wire daemon_csrbus_wr_in; // csrbus_wr
wire daemon_csrbus_wr_out; // csrbus_wr
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_in; // SW write data
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_out; // SW write data
wire [`FIRE_CSRBUS_DATA_WIDTH - 1:0] read_data_0_out; // Read Data
wire rst_l_out; // HW reset
//====================================================
//====================================================
assign err_cor_mapping_select_pulse_out = err_cor_mapping_select_pulse;
assign err_nonfatal_mapping_select_pulse_out = err_nonfatal_mapping_select_pulse;
assign err_fatal_mapping_select_pulse_out = err_fatal_mapping_select_pulse;
assign pm_pme_mapping_select_pulse_out = pm_pme_mapping_select_pulse;
assign pme_to_ack_mapping_select_pulse_out = pme_to_ack_mapping_select_pulse;
assign rst_l_out = rst_l;
assign daemon_csrbus_wr_out = daemon_csrbus_wr_in;
assign daemon_csrbus_wr_data_out = daemon_csrbus_wr_data_in;
//=====================================================
//=====================================================
dmu_imu_rds_mess_csrpipe_1 dmu_imu_rds_mess_csrpipe_1_inst_1
endmodule // dmu_imu_rds_mess_stage_mux_only