// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_mmu_qcb_qmc.v
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csr2qcb_ds_a, // csr debug select a
csr2qcb_ds_b, // csr debug select b
irb2qcb_enq, // irb srm enqueue
orb2qcb_full, // orb isr queue full
tcb2qcb_vld, // tcb valid bits
qpc2qmc_vld, // qpc valid bits
qrc2qmc_vld, // qrc valid bits
qvc2qmc_vld, // qvc valid bits
qcb2csr_dbg_a, // csr debug bus a
qcb2csr_dbg_b, // csr debug bus b
qcb2csr_paq, // csr physical address queue not empty
qcb2csr_vaq, // csr virtual address queue not empty
qcb2irb_full, // irb queue full
qcb2orb_enq, // orb srm enqueue
qcb2tcb_vld, // tcb valid
qmc2qpc_enq, // qpc enqueue
qmc2qpc_deq, // qpc dequeue
qmc2qrc_enq, // qrc enqueue
qmc2qrc_deq, // qrc dequeue
qmc2qvc_enq, // qvc enqueue
qmc2qvc_deq // qvc dequeue
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
input [`FIRE_DLC_MMU_CSR_DS_BITS] csr2qcb_ds_a;
input [`FIRE_DLC_MMU_CSR_DS_BITS] csr2qcb_ds_b;
input [`FIRE_DLC_MMU_PLS_DPTH:1] tcb2qcb_vld;
input [`FIRE_DLC_MMU_PAQ_DPTH-1:0] qpc2qmc_vld;
input [`FIRE_DLC_MMU_RDQ_DPTH-1:0] qrc2qmc_vld;
input [`FIRE_DLC_MMU_VAQ_DPTH-1:0] qvc2qmc_vld;
output [`FIRE_DBG_DATA_BITS] qcb2csr_dbg_a;
output [`FIRE_DBG_DATA_BITS] qcb2csr_dbg_b;
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
wire [`FIRE_DBG_DATA_BITS] qcb2csr_dbg_a, qcb2csr_dbg_b;
reg [`FIRE_DLC_MMU_CSR_DS_BITS] dbg_sel [0:1];
reg [`FIRE_DBG_DATA_BITS] dbg_bus [0:1];
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
wire qcb2csr_paq = qpc2qmc_vld[0];
wire qcb2csr_vaq = qvc2qmc_vld[0];
wire vaq_full = qvc2qmc_vld[`FIRE_DLC_MMU_VAQ_DPTH-2];
wire rdq_full = qrc2qmc_vld[`FIRE_DLC_MMU_RDQ_DPTH-2];
wire qcb2irb_full = vaq_full | rdq_full;
wire enq = tcb2qcb_vld[`FIRE_DLC_MMU_PLS_DPTH];
always @ (orb2qcb_full or qpc2qmc_vld or enq or deq) begin
case ({enq, deq}) // synopsys parallel_case
2'b00 : nxt_deq = qpc2qmc_vld[0] & ~orb2qcb_full;
2'b01 : nxt_deq = qpc2qmc_vld[1] & ~orb2qcb_full;
2'b10 : nxt_deq = ~orb2qcb_full;
2'b11 : nxt_deq = ~orb2qcb_full;
always @ (orb2qcb_full or tcb2qcb_vld or qpc2qmc_vld ) begin
case (tcb2qcb_vld) // synopsys parallel_case
3'b000 : qcb2tcb_hld = 1'b0;
3'b001 : qcb2tcb_hld = qpc2qmc_vld[3];
3'b010 : qcb2tcb_hld = qpc2qmc_vld[3];
3'b011 : qcb2tcb_hld = qpc2qmc_vld[2];
3'b100 : qcb2tcb_hld = qpc2qmc_vld[3];
3'b101 : qcb2tcb_hld = qpc2qmc_vld[2];
3'b110 : qcb2tcb_hld = qpc2qmc_vld[2];
3'b111 : qcb2tcb_hld = qpc2qmc_vld[1];
wire qcb2tcb_vld = qvc2qmc_vld[0];
wire qmc2qrc_enq = irb2qcb_enq;
wire qmc2qvc_enq = irb2qcb_enq;
wire qmc2qvc_deq = qvc2qmc_vld[0] & ~tcb2qcb_hld;
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
always @ (csr2qcb_ds_a or csr2qcb_ds_b) begin
dbg_sel[0] = csr2qcb_ds_a;
dbg_sel[1] = csr2qcb_ds_b;
assign qcb2csr_dbg_a = dbg_bus[0];
assign qcb2csr_dbg_b = dbg_bus[1];
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
always @ (posedge clk) begin
if(~rst_l) begin : dbg_rst
for (j = 0; j < 2; j = j + 1) begin
for (i = 0; i < 2; i = i + 1) begin
case (dbg_sel[i]) // synopsys infer_mux
3'b000: dbg_bus[i] <= { qpc2qmc_vld, qvc2qmc_vld };
3'b001: dbg_bus[i] <= qrc2qmc_vld;
3'b010: dbg_bus[i] <= 8'h00;
3'b011: dbg_bus[i] <= 8'h00;
3'b100: dbg_bus[i] <= 8'h00;
3'b101: dbg_bus[i] <= 8'h00;
3'b110: dbg_bus[i] <= 8'h00;
3'b111: dbg_bus[i] <= 8'h00;
endmodule // dmu_mmu_qcb_qmc