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// OpenSPARC T2 Processor File: dmu_tmu_dim_xfrfsm.v
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module dmu_tmu_dim_xfrfsm (
//synopsys sync_set_reset "rst_l"
// >>>>>>>>>>>>>>>>>>>>>>>>> Parameter Declarations <<<<<<<<<<<<<<<<<<<<<<<<<
parameter // summit enum xfr_enum
// >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//------------------------------------------------------------------------
// Clock and Reset Signals
//------------------------------------------------------------------------
//------------------------------------------------------------------------
// record interface to ILU
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//------------------------------------------------------------------------
input diu_dma_full; // from bufmgr.v
input diu_int_full; // from bufmgr.v
output int_cl_req; // to bufmgr.v
input rcd_is_msg; // from rcdbldr.v
input rcd_is_msi; // from rcdbldr.v
input rcd_is_cpld; // from rcdbldr.v
input rcd_is_dmawr; // from rcdbldr.v
output data_start; // to datafsm.v
input data_done; // from datafsm.v
input rcd_empty; // from rcdbldr.v
output rcd_deq; // to rcdbldr.v
//------------------------------------------------------------------------
//------------------------------------------------------------------------
input [2:0] low_dbg_sel_a;
input [2:0] low_dbg_sel_b;
output [`FIRE_DBG_DATA_BITS] xfrfsm_dbg_a;
output [`FIRE_DBG_DATA_BITS] xfrfsm_dbg_b;
//------------------------------------------------------------------------
//------------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<<
// ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
reg [STATE_NUM-1:0] xfr_state; // 0in one_hot
reg data_inprogress; // data fsm is busy
reg [`FIRE_DBG_DATA_BITS] dbg_bus [0:1];
// ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - NON-FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~
reg [STATE_NUM-1:0] nxt_xfr_state;
reg [`FIRE_DBG_DATA_BITS] nxt_dbg_bus [0:1];
// ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// >>>>>>>>>>>>>>>>>>>>>>>>> Zero In Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
// #0in back_pressure -back_pressure rm2tm_rcd_full -xmit_ready tm2rm_rcd_enq -min 1 -max 1
// 0in assert_follower -leader rm2tm_rcd_full -follower ~tm2rm_rcd_enq -min 1 -max 1
/* 0in state -var xfr_state -val (3'b1 << IDLE) -next
/* 0in state -var xfr_state -val (3'b1 << DATA) -next
/* 0in state -var xfr_state -val (3'b1 << DEQ) -next
// >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<<
//---------------------------------------------------------------------
//---------------------------------------------------------------------
// summit state_vector xfr_state enum xfr_enum
xfr_state <= {STATE_NUM{1'b0}};
xfr_state <= nxt_xfr_state;
assign rcd_has_payld = rcd_is_msi | rcd_is_cpld | rcd_is_dmawr;
assign diu_no_space = (rcd_is_dmawr & diu_dma_full) |
((rcd_is_msg | rcd_is_msi) & diu_int_full);
always @ (xfr_state or rcd_empty or data_inprogress or rm2tm_rcd_full or
rcd_has_payld or diu_no_space)
nxt_xfr_state = {STATE_NUM{1'b0}};
case (1'b1) // 0in < case -full // synopsys parallel_case
casez ({rcd_empty, diu_no_space, rm2tm_rcd_full, rcd_has_payld, data_inprogress}) // 0in < case -parallel -full
5'b00011: nxt_xfr_state[IDLE] = 1'b1;
5'b00110: nxt_xfr_state[DATA] = 1'b1;
5'b0000z: nxt_xfr_state[DEQ] = 1'b1;
endcase // casez({rcd_empty, diu_no_space, rm2tm_rcd_full, rcd_has_payld, data_inprogress})
nxt_xfr_state[DATA] = 1'b1;
nxt_xfr_state[DEQ] = 1'b1;
assign rcd_deq = nxt_xfr_state[DEQ];
assign tm2rm_rcd_enq = xfr_state[DEQ];
assign k2y_rcd_deq = xfr_state[DEQ];
assign int_cl_req = nxt_xfr_state[DEQ] & (rcd_is_msi | rcd_is_msg);
assign data_start = (rcd_has_payld & nxt_xfr_state[DEQ] & (~xfr_state[DATA])) |
(nxt_xfr_state[DATA] & (~xfr_state[DATA]));
//---------------------------------------------------------------------
//---------------------------------------------------------------------
if (!rst_l) data_inprogress <= 1'b0;
else if (data_start ^ data_done)
if (data_start) data_inprogress <= 1'b1;
else data_inprogress <= 1'b0;
//---------------------------------------------------------------------
//---------------------------------------------------------------------
always @ (low_dbg_sel_a or low_dbg_sel_b) begin
dbg_sel[0] = low_dbg_sel_a;
dbg_sel[1] = low_dbg_sel_b;
always @ (dbg_sel[0] or dbg_sel[1] or xfr_state or rcd_has_payld
or data_inprogress or rcd_empty or rm2tm_rcd_full or data_done
or diu_no_space or rcd_is_dmawr or diu_dma_full or rcd_is_msg
or rcd_is_msi or diu_int_full or tmu_is_idle)
for (i = 0; i < 2; i = i + 1)
case (dbg_sel[i]) // synopsys infer_mux
3'b000: nxt_dbg_bus[i] = {xfr_state, rcd_is_dmawr, diu_dma_full,
rcd_is_msg, rcd_is_msi, diu_int_full};
3'b001: nxt_dbg_bus[i] = {1'b0, tmu_is_idle, rcd_has_payld,
data_inprogress, rcd_empty,
rm2tm_rcd_full, diu_no_space, data_done};
3'b010: nxt_dbg_bus[i] = 8'h00;
3'b011: nxt_dbg_bus[i] = 8'h00;
3'b100: nxt_dbg_bus[i] = 8'h00;
3'b101: nxt_dbg_bus[i] = 8'h00;
3'b110: nxt_dbg_bus[i] = 8'h00;
3'b111: nxt_dbg_bus[i] = 8'h00;
assign xfrfsm_dbg_a = dbg_bus[0];
assign xfrfsm_dbg_b = dbg_bus[1];
if(~rst_l) begin : dbg_rst
for (i = 0; i < 2; i = i + 1) begin
for (j = 0; j < 2; j = j + 1) begin
dbg_bus[j] <= nxt_dbg_bus[j];
//---------------------------------------------------------------------
//---------------------------------------------------------------------
assign xfrfsm_is_idle = xfr_state[IDLE];
// >>>>>>>>>>>>>>>>>>>>>>>>> Instantiations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
endmodule // dmu_tmu_dim_xfrfsm