// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: l2t_snpd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
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// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
`define TAG_WIDTH_LESS1 27
`define MBD_WIDTH 106 // BS and SR 11/12/03 N2 Xbar Packet format change
// BS and SR 11/12/03 N2 Xbar Packet format change
`define MBD_ECC_HI_PLUS1 106
`define MBD_ECC_HI_PLUS5 110
// BS and SR 11/12/03 N2 Xbar Packet format change
// BS and SR 11/12/03 N2 Xbar Packet format change , maps to bits [128:104] of PCXS packet , ther than RSVD bit
`define ERR_TID_HI 59 // PRM needs to change to reflect this : TID will be bits [59:54] instead of [58:54]
// Phase 2 : SIU Inteface and format change
`define JBI_HDR_SZ 26 // BS and SR 11/12/03 N2 Xbar Packet format change
`define JBI_HDR_SZ_LESS1 25 // BS and SR 11/12/03 N2 Xbar Packet format change
// `define JBI_RSVD 16 NOt used
`define JBI_OPES_LO 27 // 0 = 30, P=29, E=28, S=27
// Phase 2 : SIU Inteface and format change
// BS and SR 11/12/03 N2 Xbar Packet format change :
// `define JBINST_RSVD 8 NOT used
`define JBINST_CTAG_HI 15
`define JBINST_RQ_WR64 18
`define JBINST_OPES_LO 19 // 0 = 22, P=21, E=20, S=19
`define JBINST_OPES_HI 22
`define JBINST_ENTRY_LO 23
`define JBINST_ENTRY_HI 24
snpd_snpq_arbdp_addr_px2,
snpd_snpq_arbdp_inst_px2,
snpd_snpq_arbdp_data_px2,
wire ff_siu_req_delay_scanin;
wire ff_siu_req_delay_scanout;
wire [31:0] rdmat_sii_req_dely;
wire [31:0] muxed_dly_rdmat_sii_req;
wire ff_siu_ecc_delay_scanin;
wire ff_siu_ecc_delay_scanout;
wire [6:0] sii_l2b_ecc_delay;
wire [6:0] muxed_dly_rdmat_sii_ecc;
wire [31:0] rdmat_sii_req_buf;
wire [6:0] sii_l2b_ecc_d1;
wire ff_instr0_entry_scanin;
wire ff_instr0_entry_scanout;
wire ff_addr1_1_MERGED_scanin;
wire ff_addr1_1_MERGED_scanout;
wire ff_instr1_entry_scanin;
wire ff_instr1_entry_scanout;
wire [39:6] snpd_rdmatag_wr_addr_s2_fnl;
wire [7:0] l2t_mb2_wdata_r3;
wire ff_snp_rd_ptr_d1_5_MERGED_scanin;
wire ff_snp_rd_ptr_d1_5_MERGED_scanout;
wire [7:0] l2t_mb2_wdata_r1;
wire [7:0] l2t_mb2_wdata_r2;
wire [39:0] snpd_snpq_arbdp_addr_px2_unbuff;
output [39:0] snpd_snpq_arbdp_addr_px2;
output [`JBI_HDR_SZ-1:0] snpd_snpq_arbdp_inst_px2; // this bus has grown by 1 bit since 2.0
output [63:0] snpd_snpq_arbdp_data_px2;
output [6:0] snpd_ecc_px2;
output snpd_rq_winv_s1; // to snp ctl;
output [39:6] snpd_rdmatag_wr_addr_s2 ;
input [31:0] sii_l2t_req; // Phase 2 : SIU inteface and packet format change 2/7/04
input [ 6:0] sii_l2b_ecc; // RAS implementation 10/14/04
input snp_hdr1_wen0_s0, snp_hdr2_wen0_s1, snp_snp_data1_wen0_s2, snp_snp_data2_wen0_s3 ;
input snp_hdr1_wen1_s0, snp_hdr2_wen1_s1, snp_snp_data1_wen1_s2, snp_snp_data2_wen1_s3 ;
input [1:0] snp_rdmad_wr_entry_s2;
input [7:0] l2t_mb2_wdata;
assign stop = tcu_clk_stop;
assign pce_ov = tcu_pce_ov;
wire [`JBI_HDR_SZ-1:0] instr0;
wire [`JBI_HDR_SZ-1:0] instr1;
wire snp_rd_ptr_d1, snp_rd_ptr_d1_1, snp_rd_ptr_d1_2, snp_rd_ptr_d1_3 ;
//////////////////////////////////////////////////////////////////////////////////////////////////
// data path is 92 bits wide.
//////////////////////////////////////////////////////////////////////////////////////////////////
// Phase 2 : SIU inteface and packet format change 2/7/04
// In cycle 1 write 24 bits of header and 8 bits of address.
//[31] = don't care [31] = don't care [31] = don't care
//[30] = 'O'rdered bit [30] = 'O'rdered bit [30] = 'O'rdered bit
//[29] = 'P'osted bit [29] = 'P'osted bit [29] = 'P'osted bit
//[28] = 'E'rror bit [28] = 'E'rror bit [28] = 'E'rror bit
//[27] = 'S'ource bit (DMU/NIU) [27] = 'S'ource bit (DMU/NIU) [27] = 'S'ource bit (DMU/NIU)
//[26:24] = 3'b100 for WRI [26:24] = 3'b010 for WR8 [26:24] = 3'b001 for RDD
//[23:08] = Tag bits[15:0] [23:16] = Don't care [23:08] = Tag bits[15:0]
//[7:0] = Address[39:32] [15:8] = Bytemasks[7:0] [7:0] = Address[39:32]
// [7:0] = Address[39:32]
//////////////////////////////////////////////////////////////////////////////////////////////////
l2t_snpd_dp_inv_macro__width_1 inv_l2t_siu_delay
l2t_snpd_dp_msff_macro__stack_32c__width_32 ff_siu_req_delay
.scan_in(ff_siu_req_delay_scanin),
.scan_out(ff_siu_req_delay_scanout),
.dout(rdmat_sii_req_dely[31:0]),
l2t_snpd_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_34c__width_32 mux_rdmat_sii_req_dely
.dout (muxed_dly_rdmat_sii_req[31:0]),
.din0 (sii_l2t_req[31:0]),
.din1 (rdmat_sii_req_dely[31:0]),
l2t_snpd_dp_msff_macro__stack_8c__width_7 ff_siu_ecc_delay
.scan_in(ff_siu_ecc_delay_scanin),
.scan_out(ff_siu_ecc_delay_scanout),
.dout(sii_l2b_ecc_delay[6:0]),
l2t_snpd_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_8c__width_7 mux_siu_ecc_dly
.dout (muxed_dly_rdmat_sii_ecc[6:0]),
.din0 (sii_l2b_ecc[6:0]),
.din1 (sii_l2b_ecc_delay[6:0]),
// Phase 2 : SIU inteface and packet format change 2/7/04
// This adds the 1 cycle delay to the req bus from SIU hence lining
l2t_snpd_dp_msff_macro__stack_32c__width_32 ff_siu_req
.scan_in(ff_siu_req_scanin),
.scan_out(ff_siu_req_scanout),
.dout(rdmat_sii_req_buf[31:0]),
.din(muxed_dly_rdmat_sii_req[31:0]),
l2t_snpd_dp_msff_macro__stack_7c__width_7 ff_siu_ecc
.scan_in(ff_siu_ecc_scanin),
.scan_out(ff_siu_ecc_scanout),
.din(muxed_dly_rdmat_sii_ecc[6:0]),
.dout(sii_l2b_ecc_d1[6:0]),
l2t_snpd_dp_msff_macro__stack_39c__width_39 ff_MERGED
.scan_in(ff_MERGED_scanin),
.scan_out(ff_MERGED_scanout),
.din({sii_l2b_ecc_d1[6:0],rdmat_sii_req_buf[`JBI_RQ_POISON],rdmat_sii_req_buf[`JBI_OPES_HI:`JBI_SZ_LO],rdmat_sii_req_buf[`JBI_ADDR_HI:`JBI_ADDR_LO]}),
.dout({instr0_ecc[6:0],instr0[`JBI_HDR_SZ-1],instr0[`JBI_HDR_SZ-4:0],addr0[39:32]}),
// Phase 2 : SIU inteface and packet format change 2/7/04
l2t_snpd_dp_msff_macro__stack_2c__width_2 ff_instr0_entry
.scan_in(ff_instr0_entry_scanin),
.scan_out(ff_instr0_entry_scanout),
.din(snp_rdmad_wr_entry_s2[1:0]), .clk(l2clk),
.dout(instr0[`JBI_HDR_SZ-2:`JBI_HDR_SZ-3]),
.en(snp_snp_data1_wen0_s2),
// 32 bits of addr <31:0>
l2t_snpd_dp_msff_macro__stack_32c__width_32 ff_addr0_2
.scan_in(ff_addr0_2_scanin),
.scan_out(ff_addr0_2_scanout),
.din(rdmat_sii_req_buf[31:0]), .clk(l2clk),
// 32 bits of data <63:32>
l2t_snpd_dp_msff_macro__dmsff_16x__stack_32c__width_32 ff_data0_1
.scan_in(ff_data0_1_scanin),
.scan_out(ff_data0_1_scanout),
.din(rdmat_sii_req_buf[31:0]), .clk(l2clk),
.en(snp_snp_data1_wen0_s2),
// 32 bits of data <31:0>
l2t_snpd_dp_msff_macro__dmsff_16x__stack_32c__width_32 ff_data0_2
.scan_in(ff_data0_2_scanin),
.scan_out(ff_data0_2_scanout),
.din(rdmat_sii_req_buf[31:0]), .clk(l2clk),
.en(snp_snp_data2_wen0_s3),
// In cycle 1 write 24 bits of header and 8 bits of address.
// Header = wr64 wr8 rd CTAG<11:0> RSVD SZ<7:0>
l2t_snpd_dp_msff_macro__stack_39c__width_39 ff_addr1_1_MERGED
.scan_in(ff_addr1_1_MERGED_scanin),
.scan_out(ff_addr1_1_MERGED_scanout),
.din({sii_l2b_ecc_d1[6:0],rdmat_sii_req_buf[`JBI_OPES_HI:`JBI_SZ_LO],rdmat_sii_req_buf[`JBI_ADDR_HI:`JBI_ADDR_LO],rdmat_sii_req_buf[`JBI_RQ_POISON]}),
.dout({instr1_ecc[6:0],instr1[`JBI_HDR_SZ-4:0],addr1[39:32],instr1[`JBI_HDR_SZ-1]}),
// Phase 2 : SIU inteface and packet format change 2/7/04
l2t_snpd_dp_msff_macro__stack_2c__width_2 ff_instr1_entry
.scan_in(ff_instr1_entry_scanin),
.scan_out(ff_instr1_entry_scanout),
.din(snp_rdmad_wr_entry_s2[1:0]), .clk(l2clk),
.dout(instr1[`JBI_HDR_SZ-2:`JBI_HDR_SZ-3]),
.en(snp_snp_data1_wen1_s2),
// 32 bits of addr <31:0>
l2t_snpd_dp_msff_macro__stack_32c__width_32 ff_addr1_2
(.din(rdmat_sii_req_buf[31:0]), .clk(l2clk),
.scan_in(ff_addr1_2_scanin),
.scan_out(ff_addr1_2_scanout),
// 32 bits of data <63:32>
l2t_snpd_dp_msff_macro__dmsff_16x__stack_32c__width_32 ff_data1_1
.scan_in(ff_data1_1_scanin),
.scan_out(ff_data1_1_scanout),
.din(rdmat_sii_req_buf[31:0]), .clk(l2clk),
.en(snp_snp_data1_wen1_s2),
// 32 bits of data <31:0>
l2t_snpd_dp_msff_macro__dmsff_16x__stack_32c__width_32 ff_data1_2
.scan_in(ff_data1_2_scanin),
.scan_out(ff_data1_2_scanout),
.din(rdmat_sii_req_buf[31:0]), .clk(l2clk),
.en(snp_snp_data2_wen1_s3),
/////////////////////////////////////////////////
// A 34 bit mux is used to mux out the address
// of the request that is being sent from the siu.
// Hence wr ptr is used for this mux.
// If this request happens to be a WR64, the
// address is written into the rdma tags.
/////////////////////////////////////////////////
l2t_snpd_dp_inv_macro__width_2 snp_wr_ptr_inv_slice
.dout ({l2t_mb2_run_r1_n,snp_wr_ptr_n}),
.din ({l2t_mb2_run_r1,snp_wr_ptr})
l2t_snpd_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_35c__width_35 mux_MERGED
(.dout ({snpd_rdmatag_wr_addr_s2_fnl[39:6],snpd_rq_winv_s1}) ,
.din0({addr0[39:6],instr0[`JBINST_RQ_WR64]}), // entry0
.din1({addr1[39:6],instr1[`JBINST_RQ_WR64]}), // entry1
.sel0(snp_wr_ptr_n), // entry 0 is being written
.sel1(snp_wr_ptr)) ; // entry 1 is being written
l2t_snpd_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_34c__width_34 mux_snpd_rdmatag_wr_addr_s2
.dout (snpd_rdmatag_wr_addr_s2[39:6]),
.din0 (snpd_rdmatag_wr_addr_s2_fnl[39:6]),
.din1 ({l2t_mb2_wdata_r3[1:0],{4{l2t_mb2_wdata_r3[7:0]}}}),
.sel0 (l2t_mb2_run_r1_n),
/////////////////////////////////////////////////
// The snp q output is a mux between the
// rd pointer is updated when arb_snpsel_c1
/////////////////////////////////////////////////
l2t_snpd_dp_msff_macro__dmsff_32x__stack_32c__width_32 ff_snp_rd_ptr_d1_5_MERGED
.scan_in(ff_snp_rd_ptr_d1_5_MERGED_scanin),
.scan_out(ff_snp_rd_ptr_d1_5_MERGED_scanout),
.din({l2t_mb2_wdata[7:0],l2t_mb2_wdata_r1[7:0],l2t_mb2_wdata_r2[7:0],
l2t_mb2_run,snp_rd_ptr,snp_rd_ptr,snp_rd_ptr,
snp_rd_ptr,snp_rd_ptr,snp_rd_ptr,snp_rd_ptr_n}),
.dout({l2t_mb2_wdata_r1[7:0],l2t_mb2_wdata_r2[7:0],l2t_mb2_wdata_r3[7:0],
l2t_mb2_run_r1,snp_rd_ptr_d1_5,
snp_rd_ptr_d1_4,snp_rd_ptr_d1_3,snp_rd_ptr_d1_2,
snp_rd_ptr_d1_1,snp_rd_ptr_d1,snp_rd_ptr_d1_n}),
l2t_snpd_dp_inv_macro__width_1 snp_rd_ptr_inv_slice
l2t_snpd_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_27c__width_26 mux_instr_px2
(.dout (snpd_snpq_arbdp_inst_px2[`JBI_HDR_SZ-1:0]),
.din0(instr0[`JBI_HDR_SZ-1:0]), // entry0
.din1(instr1[`JBI_HDR_SZ-1:0]), // entry1
.sel0(snp_rd_ptr_d1_n), // entry 0 is being written
.sel1(snp_rd_ptr_d1)) ; // entry 1 is being written
l2t_snpd_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_7c__width_7 mux_snp_ecc_px2
(.dout (snpd_ecc_px2[6:0]),
.din0 (instr0_ecc[6:0]), // entry0
.din1 (instr1_ecc[6:0]), // entry1
.sel0 (snp_rd_ptr_d1_n), // entry 0 is being written
.sel1 (snp_rd_ptr_d1)) ; // entry 1 is being written
// 1) use an 8x flop for snp_rd_ptr_d1_4, snp_rd_ptr_d1_5
// The above signals can be used for the more critical address bits <17:8>
// transmit the selects close to the affected bits before flopping them so
// as to save time in PX2.
// 2) The 2-1 addr mux ( use a 2x mux) can be performed between ~addr0 and ~addr1.
// The result can be driven using a 40x buffer
l2t_snpd_dp_inv_macro__width_1 snp_rd_ptr_d1_1_inv_slice
.dout (snp_rd_ptr_d1_1_n ),
//buff_macro buff_snpd_snpq_arbdp_addr_px2_1 (width=30,stack=30c,dbuff=32x)
// .dout ({snpd_snpq_arbdp_addr_px2[39:18],snpd_snpq_arbdp_addr_px2[7:0]}) ,
// .din ({snpd_snpq_arbdp_addr_px2_unbuff[39:18],snpd_snpq_arbdp_addr_px2_unbuff[7:0]}) ,
assign snpd_snpq_arbdp_addr_px2[39:0] = snpd_snpq_arbdp_addr_px2_unbuff[39:0];
l2t_snpd_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_30c__width_30 mux_addr_px2_39_18_MERGED
.dout ({snpd_snpq_arbdp_addr_px2_unbuff[39:18],snpd_snpq_arbdp_addr_px2_unbuff[7:0]}) ,
.din0({addr0[39:18],addr0[7:0]}), // entry0
.din1({addr1[39:18],addr1[7:0]}), // entry1
.sel0(snp_rd_ptr_d1_1_n) // entry 0 is being read
); // entry 1 is being read
l2t_snpd_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_5c__width_5 mux_addr_px2_17_13
(.dout (snpd_snpq_arbdp_addr_px2_unbuff[17:13]) ,
.din0(addr1[17:13]), // entry1
.din1(addr0[17:13]), // entry0
.sel0(snp_rd_ptr_d1_4) // entry 0 is being read
) ; // entry 1 is being read
l2t_snpd_dp_inv_macro__width_1 snp_rd_ptr_d1_5_inv_slice
.dout (snp_rd_ptr_d1_5_n ),
l2t_snpd_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_5c__width_5 mux_addr_px2_12_8
(.dout (snpd_snpq_arbdp_addr_px2_unbuff[12:8]) ,
.din0(addr0[12:8]), // entry0
.din1(addr1[12:8]), // entry1
.sel0(snp_rd_ptr_d1_5_n) // entry 0 is being read
) ; // entry 1 is being read
l2t_snpd_dp_inv_macro__width_1 snp_rd_ptr_d1_2_inv_slice
.dout (snp_rd_ptr_d1_2_n ),
l2t_snpd_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_32c__width_32 mux_data_px2_0
(.dout (snpd_snpq_arbdp_data_px2[31:0]) ,
.din0(data0[31:0]), // entry0
.din1(data1[31:0]), // entry1
.sel0(snp_rd_ptr_d1_2_n) // entry 0 is being written
) ; // entry 1 is being written
l2t_snpd_dp_inv_macro__width_1 snp_rd_ptr_d1_3_inv_slice
.dout (snp_rd_ptr_d1_3_n ),
l2t_snpd_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_32c__width_32 mux_data_px2_1
.dout (snpd_snpq_arbdp_data_px2[63:32]) ,
.din0(data0[63:32]), // entry0
.din1(data1[63:32]), // entry1
.sel0(snp_rd_ptr_d1_3_n) // entry 0 is being written
//buff_macro buff_snpd_snpq_arbdp_data_px2_1 (width=32,stack=32c,dbuff=32x)
// .dout (snpd_snpq_arbdp_data_px2[63:32]),
// .din (snpd_snpq_arbdp_data_px2_unbuff[63:32])
//buff_macro buff_snpd_snpq_arbdp_data_px2_2 (width=32,stack=32c,dbuff=32x)
// .dout (snpd_snpq_arbdp_data_px2[31:0]),
// .din (snpd_snpq_arbdp_data_px2_unbuff[31:0])
assign ff_siu_req_delay_scanin = scan_in ;
assign ff_siu_ecc_delay_scanin = ff_siu_req_delay_scanout ;
assign ff_siu_req_scanin = ff_siu_ecc_delay_scanout ;
assign ff_siu_ecc_scanin = ff_siu_req_scanout ;
assign ff_MERGED_scanin = ff_siu_ecc_scanout ;
assign ff_instr0_entry_scanin = ff_MERGED_scanout ;
assign ff_addr0_2_scanin = ff_instr0_entry_scanout ;
assign ff_data0_1_scanin = ff_addr0_2_scanout ;
assign ff_data0_2_scanin = ff_data0_1_scanout ;
assign ff_addr1_1_MERGED_scanin = ff_data0_2_scanout ;
assign ff_instr1_entry_scanin = ff_addr1_1_MERGED_scanout;
assign ff_addr1_2_scanin = ff_instr1_entry_scanout ;
assign ff_data1_1_scanin = ff_addr1_2_scanout ;
assign ff_data1_2_scanin = ff_data1_1_scanout ;
assign ff_snp_rd_ptr_d1_5_MERGED_scanin = ff_data1_2_scanout ;
assign scan_out = ff_snp_rd_ptr_d1_5_MERGED_scanout;
module l2t_snpd_dp_inv_macro__width_1 (
// any PARAMS parms go into naming of macro
module l2t_snpd_dp_msff_macro__stack_32c__width_32 (
.so({so[30:0],scan_out}),
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_snpd_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_34c__width_32 (
cl_dp1_muxbuff2_8x c0_0 (
// any PARAMS parms go into naming of macro
module l2t_snpd_dp_msff_macro__stack_8c__width_7 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_snpd_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_8c__width_7 (
cl_dp1_muxbuff2_8x c0_0 (
// any PARAMS parms go into naming of macro
module l2t_snpd_dp_msff_macro__stack_7c__width_7 (
// any PARAMS parms go into naming of macro
module l2t_snpd_dp_msff_macro__stack_39c__width_39 (
.so({so[37:0],scan_out}),
// any PARAMS parms go into naming of macro
module l2t_snpd_dp_msff_macro__stack_2c__width_2 (
// any PARAMS parms go into naming of macro
module l2t_snpd_dp_msff_macro__dmsff_16x__stack_32c__width_32 (
.so({so[30:0],scan_out}),
module l2t_snpd_dp_inv_macro__width_2 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_snpd_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_35c__width_35 (
cl_dp1_muxbuff2_8x c0_0 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_snpd_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_34c__width_34 (
cl_dp1_muxbuff2_8x c0_0 (
// any PARAMS parms go into naming of macro
module l2t_snpd_dp_msff_macro__dmsff_32x__stack_32c__width_32 (
.so({so[30:0],scan_out}),
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_snpd_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_27c__width_26 (
cl_dp1_muxbuff2_8x c0_0 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_snpd_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_7c__width_7 (
cl_dp1_muxbuff2_8x c0_0 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_snpd_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_30c__width_30 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_snpd_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_5c__width_5 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_snpd_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_32c__width_32 (