// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: l2t_tagd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
`define DRAM_DATA_LO 8'h00
`define DRAM_DATA_HI 8'h7f
`define HASH_TBL_NRAM_CSR 8'h81
`define ENET_MAC_CSR 8'h83
`define ENET_ING_CSR 8'h84
`define ENET_EGR_CMD_CSR 8'h85
`define ENET_EGR_DP_CSR 8'h86
`define RESERVED_2_LO 8'h87
`define RESERVED_2_HI 8'h92
`define RAND_GEN_CSR 8'h95
`define CLOCK_UNIT_CSR 8'h96
`define IOB_MAN_CSR 8'h98
`define RESERVED_4_L0 8'h9a
`define RESERVED_4_HI 8'h9d
`define IOB_INT_CSR 8'h9f
//Cache Crossbar Width and Field Defines
//======================================
`define PCX_WIDTH 130 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
`define PCX_WIDTH_LESS1 129 //PCX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
`define CPX_WIDTH 146 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
`define CPX_WIDTH_LESS1 145 //CPX payload packet width, BS and SR 11/12/03 N2 Xbar Packet format change
`define CPX_WIDTH11c 134c
`define CPX_WIDTHc 146c //CPX payload packet width , BS and SR 11/12/03 N2 Xbar Packet format change
`define PCX_VLD 123 //PCX packet valid
`define PCX_RQ_HI 122 //PCX request type field
`define PCX_NC 117 //PCX non-cacheable bit
`define PCX_R 117 //PCX read/!write bit
`define PCX_CP_HI 116 //PCX cpu_id field
`define PCX_TH_HI 113 //PCX Thread field
`define PCX_BF_HI 111 //PCX buffer id field
`define PCX_WY_HI 108 //PCX replaced L1 way field
`define PCX_P_HI 108 //PCX packet ID, 1st STQ - 10, 2nd - 01
`define PCX_SZ_HI 106 //PCX load/store size field
`define PCX_ERR_HI 106 //PCX error field
`define PCX_AD_HI 103 //PCX address field
`define PCX_DA_HI 63 //PCX Store data
`define PCX_SZ_1B 3'b000 // encoding for 1B access
`define PCX_SZ_2B 3'b001 // encoding for 2B access
`define PCX_SZ_4B 3'b010 // encoding for 4B access
`define PCX_SZ_8B 3'b011 // encoding for 8B access
`define PCX_SZ_16B 3'b100 // encoding for 16B access
`define CPX_VLD 145 //CPX payload packet valid
`define CPX_RQ_HI 144 //CPX Request type
`define CPX_ERR_HI 140 //CPX error field
`define CPX_NC 137 //CPX non-cacheable
`define CPX_R 137 //CPX read/!write bit
`define CPX_TH_HI 136 //CPX thread ID field
//bits 133:128 are shared by different fields
//for different packet types.
`define CPX_IN_HI 133 //CPX Interrupt source
`define CPX_WYVLD 133 //CPX replaced way valid
`define CPX_WY_HI 132 //CPX replaced I$/D$ way
`define CPX_BF_HI 130 //CPX buffer ID field - 3 bits
`define CPX_SI_HI 132 //L1 set ID - PA[10:6]- 5 bits
`define CPX_SI_LO 128 //used for invalidates
`define CPX_P_HI 131 //CPX packet ID, 1st STQ - 10, 2nd - 01
`define CPX_ASI 130 //CPX forward request to ASI
`define CPX_INV_PA_HI 116
`define CPX_INV_PA_LO 112
`define CPX_INV_IDX_HI 117
`define CPX_INV_IDX_LO 112
`define CPX_DA_HI 127 //CPX data payload
`define MMU_RQ 5'b01000 // BS and SR 11/12/03 N2 Xbar Packet format change
`define IMISS_RQ 5'b10000
`define STORE_RQ 5'b00001
`define STRLOAD_RQ 5'b00100
`define STRST_RQ 5'b00101
`define IFILL_RET 4'b0001
`define EVICT_REQ 4'b0011
//`define INVAL_ACK 4'b1000
`define INVAL_ACK 4'b0100
`define STRLOAD_RET 4'b0010
`define STRST_ACK 4'b0110
`define FWD_RQ_RET 4'b1010
`define FWD_RPY_RET 4'b1011
//End cache crossbar defines
// Number of COS supported by EECU
`define MAX_XFER_LEN 7'b0
`define EICU_CTAG_PRE 5'b11101
`define EIPU_CTAG_PRE 3'b011
`define EECU_CTAG_PRE 8'b11010000
`define EEPU_CTAG_PRE 6'b010000
`define L2C_CTAG_PRE 2'b00
`define JBI_CTAG_PRE 2'b10
// reinstated temporarily
`define PCI_CTAG_PRE 7'b1101100
`define BSC_L2_REQ `BSC_L2_REQ_SZ // used by rams in L2 code
`define BSC_L2_CTAG_HI 61
`define BSC_L2_CTAG_LO 50
`define L2_BSC_CBA_HI 14 // CBA - Critical Byte Address
`define L2_BSC_CTAG_HI 11
// Enet Egress Command Unit
// Enet Egress Packet Unit
`define EEPU_R_TLEN_HI 54
`define EEPU_R_TLEN_LO 48
`define EEPU_R_PORT_HI 45
`define EEPU_R_PORT_LO 44
// This is cleaved in between Egress Datapath Ack's
`define EEDP_A_PORT_WIDTH 2
// In-Order / Ordered Queue: EEPU
// Tag is: TLEN, SOF, EOF, QID = 15
`define EEPU_TAG_ARY (7+1+1+6)
// Nack + Tag Info + CTag
`define IOQ_TAG_ARY (1+`EEPU_TAG_ARY+12)
`define EEPU_TAG_LOC (`EEPU_P_IDX+`EEPU_E_IDX)
// ENET Ingress Queue Management Req
`define EICU_R_CTAG_HI 61
`define EICU_R_CTAG_LO 50
// ENET Ingress Queue Management Ack
`define EICU_A_CTAG_HI 11
// Enet Ingress Packet Unit
`define EIPU_R_CTAG_HI 58
`define EIPU_R_CTAG_LO 50
// ENET Ingress Packet Unit Ack
// In-Order / Ordered Queue: PCI
`define BSC_MAX_REQ_SZ 62
`define BSC_REQ_ARY_INDEX 6
`define BSC_REQ_ARY_DEPTH 64
`define BSC_REQ_ARY_WIDTH 62
`define BSC_REQ_NXT_WIDTH 12
`define BSC_ACK_ARY_INDEX 6
`define BSC_ACK_ARY_DEPTH 64
`define BSC_ACK_ARY_WIDTH 14
`define BSC_ACK_NXT_WIDTH 12
`define BSC_PAY_ARY_INDEX 6
`define BSC_PAY_ARY_DEPTH 64
`define BSC_PAY_ARY_WIDTH 256
// ECC syndrome bits per memory element
`define BSC_PAY_MEM_WIDTH (`BSC_PAY_ECC+`BSC_PAY_ARY_WIDTH)
// Bits 7 to 4 of curr_port_id
`define BSC_PORT_NULL 4'h0
`define BSC_PORT_EICU 4'h2
`define BSC_PORT_EIPU 4'h3
`define BSC_PORT_EECU 4'h4
`define BSC_PORT_EEPU 4'h8
`define BSC_PORT_PCI 4'h9
// Number of ports of each type
`define BSC_PORT_SC_CNT 8
// Bits needed to represent above
`define BSC_PORT_SC_IDX 3
// How wide the linked list pointers are
// 60b for no payload (2CoS)
// 80b for payload (2CoS)
`define BSC_PTR_WIDTH 192
`define BSC_PTR_REQ_HI 191
`define BSC_PTR_REQ_LO 144
`define BSC_PTR_REQP_HI 143
`define BSC_PTR_REQP_LO 96
`define BSC_PTR_ACK_HI 95
`define BSC_PTR_ACK_LO 48
`define BSC_PTR_ACKP_HI 47
`define BSC_PTR_ACKP_LO 0
`define BSC_PORT_SC_PTR 96 // R, R+P
`define BSC_PORT_EECU_PTR 48 // A+P
`define BSC_PORT_EICU_PTR 96 // A, A+P
`define BSC_PORT_EIPU_PTR 48 // A
`define I2C_CMD_NOP 4'b0000
`define I2C_CMD_START 4'b0001
`define I2C_CMD_STOP 4'b0010
`define I2C_CMD_WRITE 4'b0100
`define I2C_CMD_READ 4'b1000
`define IOB_ADDR_WIDTH 40
`define IOB_LOCAL_ADDR_WIDTH 32
`define IOB_CPUTHR_INDEX 5
`define IOB_CPUTHR_WIDTH 32
`define IOB_MONDO_DATA_INDEX 5
`define IOB_MONDO_DATA_DEPTH 32
`define IOB_MONDO_DATA_WIDTH 64
`define IOB_MONDO_SRC_WIDTH 5
`define IOB_INT_TAB_INDEX 6
`define IOB_INT_TAB_DEPTH 64
`define IOB_INT_STAT_WIDTH 32
`define IOB_INT_STAT_HI 31
`define IOB_INT_STAT_LO 0
`define IOB_INT_VEC_WIDTH 6
`define IOB_INT_CPU_WIDTH 5
`define IOB_INT_CPU_HI 12
`define IOB_DISP_TYPE_HI 17
`define IOB_DISP_TYPE_LO 16
`define IOB_DISP_THR_HI 12
`define IOB_DISP_THR_LO 8
`define IOB_DISP_VEC_HI 5
`define IOB_DISP_VEC_LO 0
`define IOB_RESET_STAT_WIDTH 3
`define IOB_RESET_STAT_HI 3
`define IOB_RESET_STAT_LO 1
`define IOB_SERNUM_WIDTH 64
`define IOB_FUSE_WIDTH 22
`define IOB_TMSTAT_THERM 63
`define IOB_POR_TT 6'b01 // power-on-reset trap type
`define IOB_CPU_BUF_INDEX 4
`define IOB_INT_BUF_INDEX 4
`define IOB_INT_BUF_WIDTH 153 // interrupt table read result buffer width
`define IOB_IO_BUF_INDEX 4
`define IOB_IO_BUF_WIDTH 153 // io-2-cpu return buffer width
`define IOB_L2_VIS_BUF_INDEX 5
`define IOB_L2_VIS_BUF_WIDTH 48 // l2 visibility buffer width
`define IOB_INT_AVEC_WIDTH 16 // availibility vector width
`define IOB_ACK_AVEC_WIDTH 16 // availibility vector width
// fixme - double check address mapping
// CREG in `IOB_INT_CSR space
`define IOB_DEV_ADDR_MASK 32'hfffffe07
`define IOB_CREG_INTSTAT 32'h00000000
`define IOB_CREG_MDATA0 32'h00000400
`define IOB_CREG_MDATA1 32'h00000500
`define IOB_CREG_MBUSY 32'h00000900
`define IOB_THR_ADDR_MASK 32'hffffff07
`define IOB_CREG_MDATA0_ALIAS 32'h00000600
`define IOB_CREG_MDATA1_ALIAS 32'h00000700
`define IOB_CREG_MBUSY_ALIAS 32'h00000b00
// CREG in `IOB_MAN_CSR space
`define IOB_CREG_INTMAN 32'h00000000
`define IOB_CREG_INTCTL 32'h00000400
`define IOB_CREG_INTVECDISP 32'h00000800
`define IOB_CREG_RESETSTAT 32'h00000810
`define IOB_CREG_SERNUM 32'h00000820
`define IOB_CREG_TMSTATCTRL 32'h00000828
`define IOB_CREG_COREAVAIL 32'h00000830
`define IOB_CREG_SSYSRESET 32'h00000838
`define IOB_CREG_FUSESTAT 32'h00000840
`define IOB_CREG_JINTV 32'h00000a00
`define IOB_CREG_DBG_L2VIS_CTRL 32'h00001800
`define IOB_CREG_DBG_L2VIS_MASKA 32'h00001820
`define IOB_CREG_DBG_L2VIS_MASKB 32'h00001828
`define IOB_CREG_DBG_L2VIS_CMPA 32'h00001830
`define IOB_CREG_DBG_L2VIS_CMPB 32'h00001838
`define IOB_CREG_DBG_L2VIS_TRIG 32'h00001840
`define IOB_CREG_DBG_IOBVIS_CTRL 32'h00001000
`define IOB_CREG_DBG_ENET_CTRL 32'h00002000
`define IOB_CREG_DBG_ENET_IDLEVAL 32'h00002008
`define IOB_CREG_DBG_JBUS_CTRL 32'h00002100
`define IOB_CREG_DBG_JBUS_LO_MASK0 32'h00002140
`define IOB_CREG_DBG_JBUS_LO_MASK1 32'h00002160
`define IOB_CREG_DBG_JBUS_LO_CMP0 32'h00002148
`define IOB_CREG_DBG_JBUS_LO_CMP1 32'h00002168
`define IOB_CREG_DBG_JBUS_LO_CNT0 32'h00002150
`define IOB_CREG_DBG_JBUS_LO_CNT1 32'h00002170
`define IOB_CREG_DBG_JBUS_HI_MASK0 32'h00002180
`define IOB_CREG_DBG_JBUS_HI_MASK1 32'h000021a0
`define IOB_CREG_DBG_JBUS_HI_CMP0 32'h00002188
`define IOB_CREG_DBG_JBUS_HI_CMP1 32'h000021a8
`define IOB_CREG_DBG_JBUS_HI_CNT0 32'h00002190
`define IOB_CREG_DBG_JBUS_HI_CNT1 32'h000021b0
`define IOB_CREG_TESTSTUB 32'h80000000
// Address map for TAP access of SPARC ASI
`define IOB_ASI_PC 4'b0000
`define IOB_ASI_BIST 4'b0001
`define IOB_ASI_MARGIN 4'b0010
`define IOB_ASI_DEFEATURE 4'b0011
`define IOB_ASI_L1DD 4'b0100
`define IOB_ASI_L1ID 4'b0101
`define IOB_ASI_L1DT 4'b0110
`define IOB_EECU_WIDTH 16 // ethernet egress command
`define EECU_IOB_WIDTH 16
`define IOB_NRAM_WIDTH 16 // NRAM (RLDRAM previously)
`define IOB_JBI_WIDTH 16 // JBI
`define IOB_ENET_ING_WIDTH 32 // ethernet ingress
`define ENET_ING_IOB_WIDTH 8
`define IOB_ENET_EGR_WIDTH 4 // ethernet egress
`define ENET_EGR_IOB_WIDTH 4
`define IOB_ENET_MAC_WIDTH 4 // ethernet MAC
`define ENET_MAC_IOB_WIDTH 4
`define IOB_DRAM_WIDTH 4 // DRAM controller
`define IOB_BSC_WIDTH 4 // BSC
`define IOB_SPI_WIDTH 4 // SPI (Boot ROM)
`define IOB_CLK_WIDTH 4 // clk unit
`define IOB_CLSP_WIDTH 4 // clk spine unit
`define IOB_TAP_WIDTH 8 // TAP
`define UCB_BID_CMP 2'b00
`define UCB_BID_TAP 2'b01
// Caution: DUMMY_DEV_ID has to be 9 bit wide
// for fields to line up properly in the IOB.
`define DUMMY_DEV_ID 9'h10 // 16
`define UNCOR_ECC_DEV_ID 7'd17 // 17
// Soft Error related definitions
// ==============================
`define COR_ECC_CNT_WIDTH 16
`define CMP_CLK_PERIOD 1333
`define DRAM_CLK_PERIOD 6000
`define NRAM_IO_DQ_WIDTH 32
`define IO_NRAM_DQ_WIDTH 32
`define NRAM_IO_ADDR_WIDTH 15
`define NRAM_IO_BA_WIDTH 2
`define NRAM_ENET_DATA_WIDTH 64
`define ENET_NRAM_ADDR_WIDTH 20
`define NRAM_DBG_DATA_WIDTH 40
`define FCRAM_DATA1_HI 63
`define FCRAM_DATA1_LO 32
`define FCRAM_DATA0_HI 31
// Load/store size encodings
// -------------------------
`define LDST_SZ_BYTE 3'b000
`define LDST_SZ_HALF_WORD 3'b001
`define LDST_SZ_WORD 3'b010
`define LDST_SZ_DOUBLE_WORD 3'b011
`define LDST_SZ_QUAD 3'b100
// =======================
// Outbound Header Format
`define JBI_BTU_OUT_ADDR_LO 0
`define JBI_BTU_OUT_ADDR_HI 42
`define JBI_BTU_OUT_RSV0_LO 43
`define JBI_BTU_OUT_RSV0_HI 43
`define JBI_BTU_OUT_TYPE_LO 44
`define JBI_BTU_OUT_TYPE_HI 48
`define JBI_BTU_OUT_RSV1_LO 49
`define JBI_BTU_OUT_RSV1_HI 51
`define JBI_BTU_OUT_REPLACE_LO 52
`define JBI_BTU_OUT_REPLACE_HI 56
`define JBI_BTU_OUT_RSV2_LO 57
`define JBI_BTU_OUT_RSV2_HI 59
`define JBI_BTU_OUT_BTU_ID_LO 60
`define JBI_BTU_OUT_BTU_ID_HI 71
`define JBI_BTU_OUT_DATA_RTN 72
`define JBI_BTU_OUT_RSV3_LO 73
`define JBI_BTU_OUT_RSV3_HI 75
`define JBI_BTU_OUT_CE 76
`define JBI_BTU_OUT_RSV4_LO 77
`define JBI_BTU_OUT_RSV4_HI 79
`define JBI_BTU_OUT_UE 80
`define JBI_BTU_OUT_RSV5_LO 81
`define JBI_BTU_OUT_RSV5_HI 83
`define JBI_BTU_OUT_DRAM 84
`define JBI_BTU_OUT_RSV6_LO 85
`define JBI_BTU_OUT_RSV6_HI 127
`define JBI_SCTAG_IN_ADDR_LO 0
`define JBI_SCTAG_IN_ADDR_HI 39
`define JBI_SCTAG_IN_SZ_LO 40
`define JBI_SCTAG_IN_SZ_HI 42
`define JBI_SCTAG_IN_RSV0 43
`define JBI_SCTAG_IN_TAG_LO 44
`define JBI_SCTAG_IN_TAG_HI 55
`define JBI_SCTAG_IN_REQ_LO 56
`define JBI_SCTAG_IN_REQ_HI 58
`define JBI_SCTAG_IN_POISON 59
`define JBI_SCTAG_IN_RSV1_LO 60
`define JBI_SCTAG_IN_RSV1_HI 63
`define JBI_SCTAG_REQ_WRI 3'b100
`define JBI_SCTAG_REQ_WR8 3'b010
`define JBI_SCTAG_REQ_RDD 3'b001
`define JBI_SCTAG_REQ_WRI_BIT 2
`define JBI_SCTAG_REQ_WR8_BIT 1
`define JBI_SCTAG_REQ_RDD_BIT 0
// JBI->IOB Mondo Header Format
// ============================
`define JBI_IOB_MONDO_RSV1_HI 15 // reserved 1
`define JBI_IOB_MONDO_RSV1_LO 13
`define JBI_IOB_MONDO_TRG_HI 12 // interrupt target
`define JBI_IOB_MONDO_TRG_LO 8
`define JBI_IOB_MONDO_RSV0_HI 7 // reserved 0
`define JBI_IOB_MONDO_RSV0_LO 5
`define JBI_IOB_MONDO_SRC_HI 4 // interrupt source
`define JBI_IOB_MONDO_SRC_LO 0
`define JBI_IOB_MONDO_RSV1_WIDTH 3
`define JBI_IOB_MONDO_TRG_WIDTH 5
`define JBI_IOB_MONDO_RSV0_WIDTH 3
`define JBI_IOB_MONDO_SRC_WIDTH 5
// JBI->IOB Mondo Bus Width/Cycle
// ==============================
`define JBI_IOB_MONDO_BUS_WIDTH 8
`define JBI_IOB_MONDO_BUS_CYCLE 18 // 2 header + 16 data
`define TAG_WIDTH_LESS1 27
`define MBD_WIDTH 106 // BS and SR 11/12/03 N2 Xbar Packet format change
// BS and SR 11/12/03 N2 Xbar Packet format change
`define MBD_ECC_HI_PLUS1 106
`define MBD_ECC_HI_PLUS5 110
// BS and SR 11/12/03 N2 Xbar Packet format change
// BS and SR 11/12/03 N2 Xbar Packet format change , maps to bits [128:104] of PCXS packet , ther than RSVD bit
`define ERR_TID_HI 59 // PRM needs to change to reflect this : TID will be bits [59:54] instead of [58:54]
// Phase 2 : SIU Inteface and format change
`define JBI_HDR_SZ 26 // BS and SR 11/12/03 N2 Xbar Packet format change
`define JBI_HDR_SZ_LESS1 25 // BS and SR 11/12/03 N2 Xbar Packet format change
// `define JBI_RSVD 16 NOt used
`define JBI_OPES_LO 27 // 0 = 30, P=29, E=28, S=27
// Phase 2 : SIU Inteface and format change
// BS and SR 11/12/03 N2 Xbar Packet format change :
// `define JBINST_RSVD 8 NOT used
`define JBINST_CTAG_HI 15
`define JBINST_RQ_WR64 18
`define JBINST_OPES_LO 19 // 0 = 22, P=21, E=20, S=19
`define JBINST_OPES_HI 22
`define JBINST_ENTRY_LO 23
`define JBINST_ENTRY_HI 24
arbadr_ncu_l2t_pm_n_dist,
arbadr_2bnk_true_enbld_dist,
arbadr_4bnk_true_enbld_dist,
arbadr_arbdp_tagdata_px2,
tagdp_tag_quad_muxsel_c3,
tagd_lkup_row_addr_dcd_c3,
tagd_lkup_row_addr_icd_c3,
tagd_mbdata_inst_tecc_c8,
arbadr_arbdp_tag_idx_px2,
tagd_arbdp_tag_idx_px2_buf_1,
tagd_arbdp_tag_idx_px2_buf_2,
tagd_mbist_l2t_index_buf,
tagd_arb_tag_way_px2_buf,
tagd_mbist_l2t_dec_way_buf,
tagd_mbist_l2t_write_buf,
tagd_mbist_write_data_buf,
wire ff_wrdata_tag_c1_scanin;
wire ff_wrdata_tag_c1_scanout;
wire [29:6] tmp_lkup_tag_c1_unused;
wire arbadr_ncu_l2t_pm_n;
wire arbadr_4bnk_true_enbld;
wire arbadr_2bnk_true_enbld;
wire ff_tagd_lkup_addr_c4_scanin;
wire ff_tagd_lkup_addr_c4_scanout;
wire ff_tag_array_read_data_scanin;
wire ff_tag_array_read_data_scanout;
wire [27:0] tag_array_read_data;
wire [36:0] piped_vuad_data_input;
wire [7:0] tagd_mbist_write_data_r1;
wire [7:0] tagd_mbist_write_data_r2;
wire [7:0] tagd_mbist_write_data_r3;
wire mbist_l2tag_fail_unreg;
wire [7:0] tagd_mbist_write_data_r4;
wire [36:0] piped_vuad_data_output;
wire ff_piped_vuad0_scanin;
wire ff_piped_vuad0_scanout;
wire ff_piped_vuad1_scanin;
wire ff_piped_vuad1_scanout;
wire mbist_l2tag_fail_raw;
wire mbist_l2t_read_r4_n;
wire ff_tagd_evict_tag_c4_scanin;
wire ff_tagd_evict_tag_c4_scanout;
wire [27:0] tagd_evict_tag_c4;
wire ff_tagd_diag_data_c52_scanin;
wire ff_tagd_diag_data_c52_scanout;
wire ff_tagd_diag_data_c6_scanin;
wire ff_tagd_diag_data_c6_scanout;
wire ff_tagd_diag_data_c7_scanin;
wire ff_tagd_diag_data_c7_scanout;
wire ff_ecc_staging1_4_scanin;
wire ff_ecc_staging1_4_scanout;
wire ff_ecc_staging5_8_scanin;
wire ff_ecc_staging5_8_scanout;
input arbadr_ncu_l2t_pm_n_dist; // BS 03/25/04 for partial bank/core modes support
input arbadr_2bnk_true_enbld_dist;// BS 03/25/04 for partial bank/core modes support
input arbadr_4bnk_true_enbld_dist; // BS 03/25/04 for partial bank/core modes support
input [39:7] arbadr_dir_cam_addr_c3; // from arbaddr
input [10:0] arbadr_arbaddr_idx_c3; // from arbaddr
input [`TAG_WIDTH-1:6] arbadr_arbdp_tagdata_px2 ; // write data for tag.
input [`TAG_WIDTH-1:0] tagl_tag_quad0_c3;
input [`TAG_WIDTH-1:0] tagl_tag_quad1_c3;
input [`TAG_WIDTH-1:0] tagl_tag_quad2_c3;
input [`TAG_WIDTH-1:0] tagl_tag_quad3_c3;
input [3:0] tagdp_tag_quad_muxsel_c3 ; // to tagd
output [`TAG_WIDTH-1:0] tagd_dmo_evict_tag_c4; // to wbdata.
output [`TAG_WIDTH-1:0] tagd_diag_data_c7; // to oque
output [17:9] tagd_lkup_addr_c4; // to the directory, BS and SR 11/18/03 Reverse Directory change
output [2:0] tagd_lkup_row_addr_dcd_c3, tagd_lkup_row_addr_icd_c3;
output [5:0] tagd_mbdata_inst_tecc_c8; // to miss buffer data.
// tagd_lkup_tag_c1[`TAG_WIDTH-1:6] replaces wrdata_tag_c1;
output [`TAG_WIDTH-1:1] tagd_lkup_tag_c1; // to tag.
input [8:0] arbadr_arbdp_tag_idx_px2; // BS & SR 10/28/03
input [8:0] mbist_l2t_index; // BS & SR 10/28/03
input [15:0] arb_tag_way_px2; // BS & SR 10/28/03
input [15:0] mbist_l2t_dec_way; // BS & SR 10/28/03
input [27:0] arbadr_tag_wrdata_px2;
input [7:0] mbist_write_data;
output [8:0] tagd_arbdp_tag_idx_px2_buf_1; // BS & SR 10/28/03
output [8:0] tagd_arbdp_tag_idx_px2_buf_2; // BS & SR 10/28/03
output [8:0] tagd_mbist_l2t_index_buf; // BS & SR 10/28/03
output [15:0] tagd_arb_tag_way_px2_buf; // BS & SR 10/28/03
output [15:0] tagd_mbist_l2t_dec_way_buf; // BS & SR 10/28/03
output tagd_arb_tag_rd_px2_buf;
output tagd_mbist_l2t_read_buf;
output tagd_arb_tag_wr_px2_buf;
output tagd_mbist_l2t_write_buf;
output [27:0] tagd_tag_wrdata_px2_buf;
output [7:0] tagd_mbist_write_data_buf;
output [27:0] tagd_evict_tag_c3;
assign stop = tcu_clk_stop;
assign pce_ov = tcu_pce_ov;
assign muxtst = tcu_muxtest;
assign test = tcu_dectest;
wire [5:0] tag_acc_ecc_c1, tag_acc_ecc_c2, tag_acc_ecc_c3;
wire [5:0] tag_acc_ecc_c4, tag_acc_ecc_c5, tag_acc_ecc_c52, tag_acc_ecc_c6; // BS 03/11/04 extra cycle for mem access
wire [5:0] tag_acc_ecc_c7;
wire [`TAG_WIDTH-1:0] tagd_evict_tag_c3, tagd_diag_data_c6, tagd_diag_data_c52; // to oque
wire [39:7] evict_addr_c3;
wire [21:0] tagd_evict_tag_orig_c3;
wire [39:7] lkup_addr_c3;
wire [`TAG_WIDTH-1:6] wrdata_tag_c1;
wire [8:0] lkup_addr_c3_tmp;
//****************************************************************
// reduced the width of this flop.
l2t_tagd_dp_msff_macro__dmsff_32x__stack_22r__width_22 ff_wrdata_tag_c1 // int 5.0 changes
(.din(arbadr_arbdp_tagdata_px2[`TAG_WIDTH-1:6]), .clk(l2clk),
.scan_in(ff_wrdata_tag_c1_scanin),
.scan_out(ff_wrdata_tag_c1_scanout),
.dout(wrdata_tag_c1[`TAG_WIDTH-1:6]), .en(1'b1),
.din({2'b0,wrdata_tag_c1[`TAG_WIDTH-1:6]}),
.dout(tmp_lkup_tag_c1_unused[29:6]),
assign tag_acc_ecc_c1 = { parity_c1[4:0], parity_c1[5] } ;
/////////////////////////////////////////////////////////
// To prevent the tag_acc_ecc_c1 bits from being
// part of the critical path in the tag compare operation,
// the overall parity bit P is not compared
// The check bits in tag_acc_ecc_c1 take 4 levels of XOR
// to compute whereas the overall parity P takes 5 levels.
// Not comparing P means that a hit could be signalled
// inspite of an error in the P bit. This requires the
// parity computation in C2 to account for this case
// and not cause any Miss Buffer insertions.
/////////////////////////////////////////////////////////
assign tagd_lkup_tag_c1[`TAG_WIDTH-1:6] = wrdata_tag_c1[`TAG_WIDTH-1:6] ;
assign tagd_lkup_tag_c1[5:1] = tag_acc_ecc_c1[5:1] ;
/////////////////////////////////////////////
// Directory lkup address
/////////////////////////////////////////////
l2t_tagd_dp_mux_macro__mux_aonpe__ports_3__stack_22r__width_22 mux_tagd_evict_tag_orig_c3
(.dout (tagd_evict_tag_orig_c3[21:0]) ,
.din0(tagd_evict_tag_c3[`TAG_WIDTH-1:6]), // original idx , all banks enabled
.din1({1'b0,tagd_evict_tag_c3[`TAG_WIDTH-1:7]}),
// 1 bit shifted idx in case of 4 banks enabled
.din2({2'b0,tagd_evict_tag_c3[`TAG_WIDTH-1:8]}),
// 2 bit shifted idx in case of 2 banks enabled
.sel0(arbadr_ncu_l2t_pm_n),
.sel1(arbadr_4bnk_true_enbld),
.sel2(arbadr_2bnk_true_enbld)
assign evict_addr_c3[39:7] = { tagd_evict_tag_orig_c3[21:0],
arbadr_arbaddr_idx_c3[10:0] } ;
l2t_tagd_dp_inv_macro__width_1 arb_evict_c3_inv_slice (
l2t_tagd_dp_mux_macro__mux_aonpe__ports_2__stack_33r__width_33 mux_cam_addr_c3
( .dout (lkup_addr_c3[39:7]),
.din0(arbadr_dir_cam_addr_c3[39:7]), .din1(evict_addr_c3[39:7]),
.sel0(arb_evict_c3_n), .sel1(arb_evict_c3));
// BS 03/25/04 for partial bank/core modes support
// index shift before writing to Directory
l2t_tagd_dp_mux_macro__mux_aonpe__ports_3__stack_10r__width_9 mux_lkup_addr_c3_tmp
(.dout (lkup_addr_c3_tmp[8:0]) ,
.din0(lkup_addr_c3[17:9]), // original idx , all banks enabled
.din1(lkup_addr_c3[16:8]), // 1 bit shifted idx in case of 4 banks enabled
.din2(lkup_addr_c3[15:7]), // 2 bit shifted idx in case of 2 banks enabled
.sel0(arbadr_ncu_l2t_pm_n),
.sel1(arbadr_4bnk_true_enbld),
.sel2(arbadr_2bnk_true_enbld)
l2t_tagd_dp_msff_macro__stack_9r__width_9 ff_tagd_lkup_addr_c4 // BS and SR 11/18/03 Reverse Directory change
(.din(lkup_addr_c3_tmp[8:0]), .clk(l2clk),
.scan_in(ff_tagd_lkup_addr_c4_scanin),
.scan_out(ff_tagd_lkup_addr_c4_scanout),
.dout(tagd_lkup_addr_c4[17:9]), .en(1'b1),
/////////////////////////////////////////////
/////////////////////////////////////////////
l2t_tagd_dp_msff_macro__stack_28r__width_28 ff_tag_array_read_data
(.din(tagd_evict_tag_c3[`TAG_WIDTH-1:0]), .clk(l2clk),
.scan_in(ff_tag_array_read_data_scanin),
.scan_out(ff_tag_array_read_data_scanout),
.dout(tag_array_read_data[`TAG_WIDTH-1:0]), .en(1'b1),
//////////////////////////////////////////////////////////////////////////////////////////////////
//assign piped_vuad_data_input[36:0] = {mbist_write_data[7:0],tagd_mbist_write_data_r1[7:0],
// tagd_mbist_write_data_r2[7:0],tagd_mbist_write_data_r3[7:0],
// mbist_l2t_read,mbist_l2t_read_r1,mbist_l2t_read_r2,
// mbist_l2t_read_r3,mbist_l2tag_fail_unreg};
//assign piped_vuad_data_output[36:0] = {tagd_mbist_write_data_r1[7:0],tagd_mbist_write_data_r2[7:0],
// tagd_mbist_write_data_r3[7:0],tagd_mbist_write_data_r4[7:0],
// mbist_l2t_read_r1,mbist_l2t_read_r2,mbist_l2t_read_r3,
// mbist_l2t_read_r4,mbist_l2tag_fail};
//msff_macro ff_piped_vuad (width=37,stack=38r)
// (.din({mbist_write_data[7:0],tagd_mbist_write_data_r1[7:0],
// tagd_mbist_write_data_r2[7:0],tagd_mbist_write_data_r3[7:0],
// mbist_l2t_read,mbist_l2t_read_r1,mbist_l2t_read_r2,
// mbist_l2t_read_r3,mbist_l2tag_fail_unreg}),
// .scan_in(ff_piped_vuad_scanin),
// .scan_out(ff_piped_vuad_scanout),
// .dout({tagd_mbist_write_data_r1[7:0],tagd_mbist_write_data_r2[7:0],
// tagd_mbist_write_data_r3[7:0],tagd_mbist_write_data_r4[7:0],
// mbist_l2t_read_r1,mbist_l2t_read_r2,mbist_l2t_read_r3,
// mbist_l2t_read_r4,mbist_l2tag_fail}),
//////////////////////////////////////////////////////////////////////////////////////////////////
assign piped_vuad_data_input[36:0] = {mbist_write_data[7:0],tagd_mbist_write_data_r1[7:0],
tagd_mbist_write_data_r2[7:0],tagd_mbist_write_data_r3[7:0],
mbist_l2t_read,mbist_l2t_read_r1,mbist_l2t_read_r2,
mbist_l2t_read_r3,mbist_l2tag_fail_unreg};
assign {tagd_mbist_write_data_r1[7:0],tagd_mbist_write_data_r2[7:0],
tagd_mbist_write_data_r3[7:0],tagd_mbist_write_data_r4[7:0],
mbist_l2t_read_r1,mbist_l2t_read_r2,mbist_l2t_read_r3,
mbist_l2t_read_r4,mbist_l2tag_fail} = piped_vuad_data_output[36:0];
l2t_tagd_dp_msff_macro__stack_28r__width_28 ff_piped_vuad0
.scan_in(ff_piped_vuad0_scanin),
.scan_out(ff_piped_vuad0_scanout),
.din(piped_vuad_data_input[27:0]),
.dout(piped_vuad_data_output[27:0]),
l2t_tagd_dp_msff_macro__stack_10r__width_9 ff_piped_vuad1
.scan_in(ff_piped_vuad1_scanin),
.scan_out(ff_piped_vuad1_scanout),
.din(piped_vuad_data_input[36:28]),
.dout(piped_vuad_data_output[36:28]),
l2t_tagd_dp_cmp_macro__width_32 cmp_mbist_data
.dout (mbist_l2tag_fail_raw),
.din0 ({4'b0,tag_array_read_data[`TAG_WIDTH-1:0]}),
.din1 ({4'b0,tagd_mbist_write_data_r4[3:0],{3{tagd_mbist_write_data_r4[7:0]}}})
l2t_tagd_dp_inv_macro__width_1 inv_mbist_l2t_read_r4
.dout (mbist_l2t_read_r4_n),
l2t_tagd_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__width_1 mux_l2tag_fail_mbist
.dout (mbist_l2tag_fail_unreg),
.din0 (mbist_l2tag_fail_raw),
.sel0 (mbist_l2t_read_r4),
.sel1 (mbist_l2t_read_r4_n)
/////////////////////////////////////////////
/////////////////////////////////////////////
l2t_tagd_dp_mux_macro__mux_pgpe__ports_4__stack_28r__width_28 mux_lru_tag // ATPG clean up
(.dout (tagd_evict_tag_c3[`TAG_WIDTH-1:0]),
.din0(tagl_tag_quad0_c3[`TAG_WIDTH-1:0]),
.din1(tagl_tag_quad1_c3[`TAG_WIDTH-1:0]),
.din2(tagl_tag_quad2_c3[`TAG_WIDTH-1:0]),
.din3(tagl_tag_quad3_c3[`TAG_WIDTH-1:0]),
.sel0(tagdp_tag_quad_muxsel_c3[0]),
.sel1(tagdp_tag_quad_muxsel_c3[1]),
.sel2(tagdp_tag_quad_muxsel_c3[2]),
//.sel3(tagdp_tag_quad_muxsel_c3[3])
//////////////////////////////////////////////////////////////////////////////////////////////
// Tag Diagnostic data pipeline
//------------------------------------------------------------------------------------------
// C1 C2 C3 C4 C5 C6 C7 C8 C9
//------------------------------------------------------------------------------------------
// diag px2 rd tag prepare mux flop flop mux data ret.
// decode idx mux way mux out tag with
//------------------------------------------------------------------------------------------
//////////////////////////////////////////////////////////////////////////////////////////////
l2t_tagd_dp_msff_macro__stack_28r__width_28 ff_tagd_evict_tag_c4
(.din(tagd_evict_tag_c3[`TAG_WIDTH-1:0]), .clk(l2clk),
.scan_in(ff_tagd_evict_tag_c4_scanin),
.scan_out(ff_tagd_evict_tag_c4_scanout),
.dout(tagd_evict_tag_c4[`TAG_WIDTH-1:0]), .en(1'b1),
assign tagd_dmo_evict_tag_c4[`TAG_WIDTH-1:0] = tagd_evict_tag_c4[`TAG_WIDTH-1:0];
l2t_tagd_dp_msff_macro__minbuff_1__stack_28r__width_28 ff_tagd_diag_data_c52
(.din(tagd_evict_tag_c4[`TAG_WIDTH-1:0]), .clk(l2clk),
.scan_in(ff_tagd_diag_data_c52_scanin),
.scan_out(ff_tagd_diag_data_c52_scanout),
.dout(tagd_diag_data_c52[`TAG_WIDTH-1:0]), .en(1'b1),
l2t_tagd_dp_msff_macro__stack_28r__width_28 ff_tagd_diag_data_c6
(.din(tagd_diag_data_c52[`TAG_WIDTH-1:0]), .clk(l2clk),
.scan_in(ff_tagd_diag_data_c6_scanin),
.scan_out(ff_tagd_diag_data_c6_scanout),
.dout(tagd_diag_data_c6[`TAG_WIDTH-1:0]), .en(1'b1),
l2t_tagd_dp_msff_macro__stack_28r__width_28 ff_tagd_diag_data_c7
(.din(tagd_diag_data_c6[`TAG_WIDTH-1:0]), .clk(l2clk),
.scan_in(ff_tagd_diag_data_c7_scanin),
.scan_out(ff_tagd_diag_data_c7_scanout),
.dout(tagd_diag_data_c7[`TAG_WIDTH-1:0]), .en(1'b1),
/////////////////////////////////////////////
// DP is 32 bits wide. The following
// logic and flops are pushed to one side.
/////////////////////////////////////////////
l2t_tagd_dp_msff_macro__stack_24r__width_24 ff_ecc_staging1_4
.scan_in(ff_ecc_staging1_4_scanin),
.scan_out(ff_ecc_staging1_4_scanout),
.din ({tag_acc_ecc_c1[5:0],tag_acc_ecc_c2[5:0],
tag_acc_ecc_c3[5:0],tag_acc_ecc_c4[5:0]}),
.dout ({tag_acc_ecc_c2[5:0],tag_acc_ecc_c3[5:0],
tag_acc_ecc_c4[5:0],tag_acc_ecc_c5[5:0]}),
l2t_tagd_dp_msff_macro__stack_27r__width_27 ff_ecc_staging5_8
.scan_in(ff_ecc_staging5_8_scanin),
.scan_out(ff_ecc_staging5_8_scanout),
.din({arbadr_ncu_l2t_pm_n_dist,arbadr_2bnk_true_enbld_dist,arbadr_4bnk_true_enbld_dist,
tag_acc_ecc_c5[5:0],tag_acc_ecc_c52[5:0],tag_acc_ecc_c6[5:0],tag_acc_ecc_c7[5:0]}),
.dout({arbadr_ncu_l2t_pm_n,arbadr_2bnk_true_enbld,arbadr_4bnk_true_enbld,
tag_acc_ecc_c52[5:0],tag_acc_ecc_c6[5:0],tag_acc_ecc_c7[5:0],tagd_mbdata_inst_tecc_c8[5:0]}),
assign tagd_lkup_row_addr_dcd_c3[2:0] = lkup_addr_c3[11:9];
assign tagd_lkup_row_addr_icd_c3[2:0] = lkup_addr_c3[11:9];
////////////////////////////////////////////////////////////
// The following signals need to be bufferred before
// INput pins are arranged on the top.
// Try to align with the data path cell placement information
////////////////////////////////////////////////////////////
// repeater row1 ( 24 bits wide ) arranged as follows from left to right.
//assign tagd_arbdp_tag_idx_px2_buf[8:0] = arbadr_arbdp_tag_idx_px2[8:0] ; // BS & SR 10/28/03
//assign tagd_arb_tag_way_px2_buf[15:0] = arb_tag_way_px2[15:0] ; // BS & SR 10/28/03
//assign tagd_arb_tag_rd_px2_buf = arb_tag_rd_px2;
//assign tagd_arb_tag_wr_px2_buf = arb_tag_wr_px2;
//buff_macro buff_tagd_arbdp_tag_idx_way_rd_wr_buf (width=36,dbuff=32x)
// .dout ({tagd_arbdp_tag_idx_px2_buf_1[8:0],tagd_arbdp_tag_idx_px2_buf_2[8:0],tagd_arb_tag_way_px2_buf[15:0],
// tagd_arb_tag_rd_px2_buf,tagd_arb_tag_wr_px2_buf}),
// .din ({arbadr_arbdp_tag_idx_px2[8:0],arbadr_arbdp_tag_idx_px2[8:0],arb_tag_way_px2[15:0],
// arb_tag_rd_px2,arb_tag_wr_px2})
l2t_tagd_dp_buff_macro__dbuff_32x__width_18 buff_tagd_arbdp_tag_idx_way_rd_wr_buf
.dout ({tagd_arb_tag_way_px2_buf[15:0],tagd_arb_tag_rd_px2_buf,tagd_arb_tag_wr_px2_buf}),
.din ({arb_tag_way_px2[15:0],arb_tag_rd_px2,arb_tag_wr_px2})
l2t_tagd_dp_inv_macro__dinv_32x__width_18 inv_arbadr_arbdp_tag_idx_px2
.dout ({tagd_arbdp_tag_idx_px2_buf_1[8:0],tagd_arbdp_tag_idx_px2_buf_2[8:0]}),
.din ({arbadr_arbdp_tag_idx_px2[8:0],arbadr_arbdp_tag_idx_px2[8:0]})
// repeater row2 ( 24 bits wide ) arranged as follows from left to right.
//assign tagd_mbist_l2t_index_buf[8:0] = mbist_l2t_index[8:0] ; // BS & SR 10/28/03
//assign tagd_mbist_l2t_dec_way_buf[15:0] = mbist_l2t_dec_way[15:0] ; // BS & SR 10/28/03
//assign tagd_mbist_l2t_read_buf = mbist_l2t_read;
//assign tagd_mbist_l2t_write_buf = mbist_l2t_write;
l2t_tagd_dp_buff_macro__dbuff_16x__width_27 buff_mbist_tagd_arbdp_tag_idx_way_rd_wr_buf
.dout ({tagd_mbist_l2t_index_buf[8:0],tagd_mbist_l2t_dec_way_buf[15:0],
tagd_mbist_l2t_read_buf,tagd_mbist_l2t_write_buf}),
.din ({mbist_l2t_index[8:0],mbist_l2t_dec_way[15:0],
mbist_l2t_read,mbist_l2t_write})
// repeater row 3 ( 28 bits wide ) arranged as follows from left to right.
// assign tagd_tag_wrdata_px2_buf = arbadr_tag_wrdata_px2 ;
l2t_tagd_dp_buff_macro__dbuff_16x__width_28 buff_tagd_tag_wrdata_px2_buf
.dout (tagd_tag_wrdata_px2_buf[27:0]),
.din (arbadr_tag_wrdata_px2[27:0])
// repeater row 4 ( 8 bits wide ) arranged as follows from left to right.
//assign tagd_mbist_write_data_buf = mbist_write_data;
l2t_tagd_dp_buff_macro__dbuff_16x__width_8 buff_tagd_mbist_write_data_buf
.dout (tagd_mbist_write_data_buf[7:0]),
.din (mbist_write_data[7:0])
assign ff_wrdata_tag_c1_scanin = scan_in ;
assign ff_tagd_lkup_addr_c4_scanin = ff_wrdata_tag_c1_scanout ;
assign ff_tag_array_read_data_scanin = ff_tagd_lkup_addr_c4_scanout;
assign ff_piped_vuad0_scanin = ff_tag_array_read_data_scanout;
assign ff_piped_vuad1_scanin = ff_piped_vuad0_scanout ;
assign ff_tagd_evict_tag_c4_scanin = ff_piped_vuad1_scanout ;
assign ff_tagd_diag_data_c52_scanin = ff_tagd_evict_tag_c4_scanout;
assign ff_tagd_diag_data_c6_scanin = ff_tagd_diag_data_c52_scanout;
assign ff_tagd_diag_data_c7_scanin = ff_tagd_diag_data_c6_scanout;
assign ff_ecc_staging1_4_scanin = ff_tagd_diag_data_c7_scanout;
assign ff_ecc_staging5_8_scanin = ff_ecc_staging1_4_scanout;
assign scan_out = ff_ecc_staging5_8_scanout;
// any PARAMS parms go into naming of macro
module l2t_tagd_dp_msff_macro__dmsff_32x__stack_22r__width_22 (
.so({so[20:0],scan_out}),
// xor macro for ports = 2,3
module l2t_tagd_dp_xor_macro__dxor_8x__ports_3__width_1 (
// xor macro for ports = 2,3
module l2t_tagd_dp_xor_macro__dxor_8x__ports_2__width_1 (
// xor macro for ports = 2,3
module l2t_tagd_dp_xor_macro__dxor_16x__ports_3__width_1 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_tagd_dp_mux_macro__mux_aonpe__ports_3__stack_22r__width_22 (
cl_dp1_muxbuff3_8x c0_0 (
module l2t_tagd_dp_inv_macro__width_1 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_tagd_dp_mux_macro__mux_aonpe__ports_2__stack_33r__width_33 (
cl_dp1_muxbuff2_8x c0_0 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_tagd_dp_mux_macro__mux_aonpe__ports_3__stack_10r__width_9 (
cl_dp1_muxbuff3_8x c0_0 (
// any PARAMS parms go into naming of macro
module l2t_tagd_dp_msff_macro__stack_9r__width_9 (
// any PARAMS parms go into naming of macro
module l2t_tagd_dp_msff_macro__stack_28r__width_28 (
.so({so[26:0],scan_out}),
// any PARAMS parms go into naming of macro
module l2t_tagd_dp_msff_macro__stack_10r__width_9 (
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module l2t_tagd_dp_cmp_macro__width_32 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_tagd_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__width_1 (
cl_dp1_muxbuff2_8x c0_0 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_tagd_dp_mux_macro__mux_pgpe__ports_4__stack_28r__width_28 (
// any PARAMS parms go into naming of macro
module l2t_tagd_dp_msff_macro__minbuff_1__stack_28r__width_28 (
.so({so[26:0],scan_out}),
// any PARAMS parms go into naming of macro
module l2t_tagd_dp_msff_macro__stack_24r__width_24 (
.so({so[22:0],scan_out}),
// any PARAMS parms go into naming of macro
module l2t_tagd_dp_msff_macro__stack_27r__width_27 (
.so({so[25:0],scan_out}),
module l2t_tagd_dp_buff_macro__dbuff_32x__width_18 (
module l2t_tagd_dp_inv_macro__dinv_32x__width_18 (
module l2t_tagd_dp_buff_macro__dbuff_16x__width_27 (
module l2t_tagd_dp_buff_macro__dbuff_16x__width_28 (
module l2t_tagd_dp_buff_macro__dbuff_16x__width_8 (
projects / OpenSPARC-T2-DV / blob