// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: mcu_bscan_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// choice is available it will apply instead, Sun elects to use only
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// ========== Copyright Header End ============================================
output [9:0] mcu_fsr0_cfgtx_bstx;
output [9:0] mcu_fsr1_cfgtx_bstx;
input [13:0] fsr0_mcu_stsrx_bsrxp;
input [13:0] fsr1_mcu_stsrx_bsrxp;
input [13:0] fsr0_mcu_stsrx_bsrxn;
input [13:0] fsr1_mcu_stsrx_bsrxn;
assign se = tcu_sbs_scan_en;
assign siclk = tcu_sbs_aclk;
assign soclk = tcu_sbs_bclk;
assign updateclk = tcu_sbs_uclk;
mcu_bscan_ctl_l1clkhdr_ctl_macro clkgen (
cl_sc1_bs_cell2_4x bstx00 (
.q(mcu_fsr0_cfgtx_bstx[0]),
cl_sc1_bs_cell2_4x bstx01 (
.q(mcu_fsr0_cfgtx_bstx[1]),
cl_sc1_bs_cell2_4x bstx02 (
.q(mcu_fsr0_cfgtx_bstx[2]),
cl_sc1_bs_cell2_4x bstx03 (
.q(mcu_fsr0_cfgtx_bstx[3]),
cl_sc1_bs_cell2_4x bstx04 (
.q(mcu_fsr0_cfgtx_bstx[4]),
cl_sc1_bs_cell2_4x bstx05 (
.q(mcu_fsr0_cfgtx_bstx[5]),
cl_sc1_bs_cell2_4x bstx06 (
.q(mcu_fsr0_cfgtx_bstx[6]),
cl_sc1_bs_cell2_4x bstx07 (
.q(mcu_fsr0_cfgtx_bstx[7]),
cl_sc1_bs_cell2_4x bstx08 (
.q(mcu_fsr0_cfgtx_bstx[8]),
cl_sc1_bs_cell2_4x bstx09 (
.q(mcu_fsr0_cfgtx_bstx[9]),
cl_sc1_bs_cell2_4x bstx10 (
.q(mcu_fsr1_cfgtx_bstx[0]),
cl_sc1_bs_cell2_4x bstx11 (
.q(mcu_fsr1_cfgtx_bstx[1]),
cl_sc1_bs_cell2_4x bstx12 (
.q(mcu_fsr1_cfgtx_bstx[2]),
cl_sc1_bs_cell2_4x bstx13 (
.q(mcu_fsr1_cfgtx_bstx[3]),
cl_sc1_bs_cell2_4x bstx14 (
.q(mcu_fsr1_cfgtx_bstx[4]),
cl_sc1_bs_cell2_4x bstx15 (
.q(mcu_fsr1_cfgtx_bstx[5]),
cl_sc1_bs_cell2_4x bstx16 (
.q(mcu_fsr1_cfgtx_bstx[6]),
cl_sc1_bs_cell2_4x bstx17 (
.q(mcu_fsr1_cfgtx_bstx[7]),
cl_sc1_bs_cell2_4x bstx18 (
.q(mcu_fsr1_cfgtx_bstx[8]),
cl_sc1_bs_cell2_4x bstx19 (
.q(mcu_fsr1_cfgtx_bstx[9]),
cl_sc1_bs_cell2_4x bsrxp00 (
.d(fsr0_mcu_stsrx_bsrxp[0]),
cl_sc1_bs_cell2_4x bsrxp01 (
.d(fsr0_mcu_stsrx_bsrxp[1]),
cl_sc1_bs_cell2_4x bsrxp02 (
.d(fsr0_mcu_stsrx_bsrxp[2]),
cl_sc1_bs_cell2_4x bsrxp03 (
.d(fsr0_mcu_stsrx_bsrxp[3]),
cl_sc1_bs_cell2_4x bsrxp04 (
.d(fsr0_mcu_stsrx_bsrxp[4]),
cl_sc1_bs_cell2_4x bsrxp05 (
.d(fsr0_mcu_stsrx_bsrxp[5]),
cl_sc1_bs_cell2_4x bsrxp06 (
.d(fsr0_mcu_stsrx_bsrxp[6]),
cl_sc1_bs_cell2_4x bsrxp07 (
.d(fsr0_mcu_stsrx_bsrxp[7]),
cl_sc1_bs_cell2_4x bsrxp08 (
.d(fsr0_mcu_stsrx_bsrxp[8]),
cl_sc1_bs_cell2_4x bsrxp09 (
.d(fsr0_mcu_stsrx_bsrxp[9]),
cl_sc1_bs_cell2_4x bsrxp10 (
.d(fsr0_mcu_stsrx_bsrxp[10]),
cl_sc1_bs_cell2_4x bsrxp11 (
.d(fsr0_mcu_stsrx_bsrxp[11]),
cl_sc1_bs_cell2_4x bsrxp12 (
.d(fsr0_mcu_stsrx_bsrxp[12]),
cl_sc1_bs_cell2_4x bsrxp13 (
.d(fsr0_mcu_stsrx_bsrxp[13]),
cl_sc1_bs_cell2_4x bsrxn00 (
.d(fsr0_mcu_stsrx_bsrxn[0]),
cl_sc1_bs_cell2_4x bsrxn01 (
.d(fsr0_mcu_stsrx_bsrxn[1]),
cl_sc1_bs_cell2_4x bsrxn02 (
.d(fsr0_mcu_stsrx_bsrxn[2]),
cl_sc1_bs_cell2_4x bsrxn03 (
.d(fsr0_mcu_stsrx_bsrxn[3]),
cl_sc1_bs_cell2_4x bsrxn04 (
.d(fsr0_mcu_stsrx_bsrxn[4]),
cl_sc1_bs_cell2_4x bsrxn05 (
.d(fsr0_mcu_stsrx_bsrxn[5]),
cl_sc1_bs_cell2_4x bsrxn06 (
.d(fsr0_mcu_stsrx_bsrxn[6]),
cl_sc1_bs_cell2_4x bsrxn07 (
.d(fsr0_mcu_stsrx_bsrxn[7]),
cl_sc1_bs_cell2_4x bsrxn08 (
.d(fsr0_mcu_stsrx_bsrxn[8]),
cl_sc1_bs_cell2_4x bsrxn09 (
.d(fsr0_mcu_stsrx_bsrxn[9]),
cl_sc1_bs_cell2_4x bsrxn10 (
.d(fsr0_mcu_stsrx_bsrxn[10]),
cl_sc1_bs_cell2_4x bsrxn11 (
.d(fsr0_mcu_stsrx_bsrxn[11]),
cl_sc1_bs_cell2_4x bsrxn12 (
.d(fsr0_mcu_stsrx_bsrxn[12]),
cl_sc1_bs_cell2_4x bsrxn13 (
.d(fsr0_mcu_stsrx_bsrxn[13]),
cl_sc1_bs_cell2_4x bsrxp14 (
.d(fsr1_mcu_stsrx_bsrxp[0]),
cl_sc1_bs_cell2_4x bsrxp15 (
.d(fsr1_mcu_stsrx_bsrxp[1]),
cl_sc1_bs_cell2_4x bsrxp16 (
.d(fsr1_mcu_stsrx_bsrxp[2]),
cl_sc1_bs_cell2_4x bsrxp17 (
.d(fsr1_mcu_stsrx_bsrxp[3]),
cl_sc1_bs_cell2_4x bsrxp18 (
.d(fsr1_mcu_stsrx_bsrxp[4]),
cl_sc1_bs_cell2_4x bsrxp19 (
.d(fsr1_mcu_stsrx_bsrxp[5]),
cl_sc1_bs_cell2_4x bsrxp20 (
.d(fsr1_mcu_stsrx_bsrxp[6]),
cl_sc1_bs_cell2_4x bsrxp21 (
.d(fsr1_mcu_stsrx_bsrxp[7]),
cl_sc1_bs_cell2_4x bsrxp22 (
.d(fsr1_mcu_stsrx_bsrxp[8]),
cl_sc1_bs_cell2_4x bsrxp23 (
.d(fsr1_mcu_stsrx_bsrxp[9]),
cl_sc1_bs_cell2_4x bsrxp24 (
.d(fsr1_mcu_stsrx_bsrxp[10]),
cl_sc1_bs_cell2_4x bsrxp25 (
.d(fsr1_mcu_stsrx_bsrxp[11]),
cl_sc1_bs_cell2_4x bsrxp26 (
.d(fsr1_mcu_stsrx_bsrxp[12]),
cl_sc1_bs_cell2_4x bsrxp27 (
.d(fsr1_mcu_stsrx_bsrxp[13]),
cl_sc1_bs_cell2_4x bsrxn14 (
.d(fsr1_mcu_stsrx_bsrxn[0]),
cl_sc1_bs_cell2_4x bsrxn15 (
.d(fsr1_mcu_stsrx_bsrxn[1]),
cl_sc1_bs_cell2_4x bsrxn16 (
.d(fsr1_mcu_stsrx_bsrxn[2]),
cl_sc1_bs_cell2_4x bsrxn17 (
.d(fsr1_mcu_stsrx_bsrxn[3]),
cl_sc1_bs_cell2_4x bsrxn18 (
.d(fsr1_mcu_stsrx_bsrxn[4]),
cl_sc1_bs_cell2_4x bsrxn19 (
.d(fsr1_mcu_stsrx_bsrxn[5]),
cl_sc1_bs_cell2_4x bsrxn20 (
.d(fsr1_mcu_stsrx_bsrxn[6]),
cl_sc1_bs_cell2_4x bsrxn21 (
.d(fsr1_mcu_stsrx_bsrxn[7]),
cl_sc1_bs_cell2_4x bsrxn22 (
.d(fsr1_mcu_stsrx_bsrxn[8]),
cl_sc1_bs_cell2_4x bsrxn23 (
.d(fsr1_mcu_stsrx_bsrxn[9]),
cl_sc1_bs_cell2_4x bsrxn24 (
.d(fsr1_mcu_stsrx_bsrxn[10]),
cl_sc1_bs_cell2_4x bsrxn25 (
.d(fsr1_mcu_stsrx_bsrxn[11]),
cl_sc1_bs_cell2_4x bsrxn26 (
.d(fsr1_mcu_stsrx_bsrxn[12]),
cl_sc1_bs_cell2_4x bsrxn27 (
.d(fsr1_mcu_stsrx_bsrxn[13]),
// any PARAMS parms go into naming of macro
module mcu_bscan_ctl_l1clkhdr_ctl_macro (