design/sys/iop/ncu/rtl/ncu_eccchk6_ctl.v

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// OpenSPARC T2 Processor File: ncu_eccchk6_ctl.v
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module ncu_eccchk6_ctl (
  din,
  ci,
  ue,
  ce,
  dout,
  co) ;
wire [4:0] e;


input  [5:0]    din;
input  [4:0]    ci;

output          ue;
output          ce;

output [5:0]    dout;
output [4:0]    co;


reg             ue;
reg             ce;
reg [5:0]       dout;
reg [4:0]       co;


assign  e[4] = ^{din[5:0],ci[4:0]} ;
assign  e[3] = ^{din[5:4],ci[3]} ;
assign  e[2] = ^{din[3:1],ci[2]} ;
assign  e[1] = ^{din[5],din[3:2],din[0],ci[1]} ;
assign  e[0] = ^{din[4:3],din[1:0],ci[0]} ;

always@(e or din or ci) begin
    dout[5:0]=din[5:0];
    co[4:0]=ci[4:0];
    ue=1'b0;
    ce=1'b1;
    case(e[4:0])
    {1'b0,4'd0} : begin
                  ue=1'b0;
                  ce=1'b0;
                  dout[5:0]=din[5:0];
                  co[4:0]=ci[4:0];
                  end
    {1'b1,4'd0} : co[4]    = ~ci[4];
    {1'b1,4'd1} : co[0]    = ~ci[0];
    {1'b1,4'd2} : co[1]    = ~ci[1];
    {1'b1,4'd3} : dout[0]  = ~din[0];
    {1'b1,4'd4} : co[2]    = ~ci[2];
    {1'b1,4'd5} : dout[1]  = ~din[1];
    {1'b1,4'd6} : dout[2]  = ~din[2];
    {1'b1,4'd7} : dout[3]  = ~din[3];
    {1'b1,4'd8} : co[3]    = ~ci[3];
    {1'b1,4'd9} : dout[4]  = ~din[4];
    {1'b1,4'd10}: dout[5]  = ~din[5];
    default : begin
              dout[5:0]=din[5:0];
              co[4:0]=ci[4:0];
              ue=1'b1;
              ce=1'b0;
              end
    endcase
end

endmodule