// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: ncu_ssiuif_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
`define RF_RDEN_OFFSTATE 1'b1
//====================================
`define NCU_INTMANRF_DEPTH 128
`define NCU_INTMANRF_DATAWIDTH 16
`define NCU_INTMANRF_ADDRWIDTH 7
//====================================
//====================================
`define NCU_MONDORF_DEPTH 64
`define NCU_MONDORF_DATAWIDTH 72
`define NCU_MONDORF_ADDRWIDTH 6
//====================================
//====================================
`define NCU_CPUBUFRF_DEPTH 32
`define NCU_CPUBUFRF_DATAWIDTH 144
`define NCU_CPUBUFRF_ADDRWIDTH 5
//====================================
//====================================
`define NCU_IOBUFRF_DEPTH 32
`define NCU_IOBUFRF_DATAWIDTH 144
`define NCU_IOBUFRF_ADDRWIDTH 5
//====================================
//====================================
`define NCU_IOBUF1RF_DEPTH 32
`define NCU_IOBUF1RF_DATAWIDTH 32
`define NCU_IOBUF1RF_ADDRWIDTH 5
//====================================
//====================================
`define NCU_INTBUFRF_DEPTH 32
`define NCU_INTBUFRF_DATAWIDTH 144
`define NCU_INTBUFRF_ADDRWIDTH 5
//====================================
//== fix me : need to remove when warm //
//== becomes available //
`define WMR_LENGTH 10'd999
`define WMR_LENGTH_P1 10'd1000
//// NCU CSR_MAN address 80_0000_xxxx ////
`define NCU_CSR_MAN 16'h0000
`define NCU_CREG_INTMAN 16'h0000
//`define NCU_CREG_INTVECDISP 16'h0800
`define NCU_CREG_MONDOINVEC 16'h0a00
`define NCU_CREG_SERNUM 16'h1000
`define NCU_CREG_FUSESTAT 16'h1008
`define NCU_CREG_COREAVAIL 16'h1010
`define NCU_CREG_BANKAVAIL 16'h1018
`define NCU_CREG_BANK_ENABLE 16'h1020
`define NCU_CREG_BANK_ENABLE_STATUS 16'h1028
`define NCU_CREG_L2_HASH_ENABLE 16'h1030
`define NCU_CREG_L2_HASH_ENABLE_STATUS 16'h1038
`define NCU_CREG_MEM32_BASE 16'h2000
`define NCU_CREG_MEM32_MASK 16'h2008
`define NCU_CREG_MEM64_BASE 16'h2010
`define NCU_CREG_MEM64_MASK 16'h2018
`define NCU_CREG_IOCON_BASE 16'h2020
`define NCU_CREG_IOCON_MASK 16'h2028
`define NCU_CREG_MMUFSH 16'h2030
`define NCU_CREG_ESR 16'h3000
`define NCU_CREG_ELE 16'h3008
`define NCU_CREG_EIE 16'h3010
`define NCU_CREG_EJR 16'h3018
`define NCU_CREG_FEE 16'h3020
`define NCU_CREG_PER 16'h3028
`define NCU_CREG_SIISYN 16'h3030
`define NCU_CREG_NCUSYN 16'h3038
`define NCU_CREG_SCKSEL 16'h3040
`define NCU_CREG_DBGTRIG_EN 16'h4000
//// NUC CSR_MONDO address 80_0004_xxxx ////
`define NCU_CSR_MONDO 16'h0004
`define NCU_CREG_MDATA0 16'h0000
`define NCU_CREG_MDATA1 16'h0200
`define NCU_CREG_MDATA0_ALIAS 16'h0400
`define NCU_CREG_MDATA1_ALIAS 16'h0600
`define NCU_CREG_MBUSY 16'h0800
`define NCU_CREG_MBUSY_ALIAS 16'h0a00
// ASI shared reg 90_xxxx_xxxx//
`define NCU_ASI_A_HIT 10'h104 // 6-bits cpuid and thread id are "x"
`define NCU_ASI_B_HIT 10'h1CC // 6-bits cpuid and thread id are "x"
`define NCU_ASI_C_HIT 10'h114 // 6-bits cpuid and thread id are "x"
`define NCU_ASI_COREAVAIL 16'h0000
`define NCU_ASI_CORE_ENABLE_STATUS 16'h0010
`define NCU_ASI_CORE_ENABLE 16'h0020
`define NCU_ASI_XIR_STEERING 16'h0030
`define NCU_ASI_CORE_RUNNINGRW 16'h0050
`define NCU_ASI_CORE_RUNNING_STATUS 16'h0058
`define NCU_ASI_CORE_RUNNING_W1S 16'h0060
`define NCU_ASI_CORE_RUNNING_W1C 16'h0068
`define NCU_ASI_INTVECDISP 16'h0000
`define NCU_ASI_ERR_STR 16'h1000
`define NCU_ASI_WMR_VEC_MASK 16'h0018
`define NCU_ASI_CMP_TICK_ENABLE 16'h0038
//// UCB packet type ////
`define UCB_READ_NACK 4'b0000 // ack/nack types
`define UCB_READ_ACK 4'b0001
`define UCB_WRITE_ACK 4'b0010
`define UCB_IFILL_ACK 4'b0011
`define UCB_IFILL_NACK 4'b0111
`define UCB_READ_REQ 4'b0100 // req types
`define UCB_WRITE_REQ 4'b0101
`define UCB_IFILL_REQ 4'b0110
`define UCB_INT 4'b1000 // plain interrupt
`define UCB_INT_VEC 4'b1100 // interrupt with vector
`define UCB_INT_SOC_UE 4'b1001 // soc interrup ue
`define UCB_INT_SOC_CE 4'b1010 // soc interrup ce
`define UCB_RESET_VEC 4'b0101 // reset with vector
`define UCB_IDLE_VEC 4'b1110 // idle with vector
`define UCB_RESUME_VEC 4'b1111 // resume with vector
`define UCB_INT_SOC 4'b1101 // soc interrup ce
//// PCX packet type ////
`define PCX_LOAD_RQ 5'b00000
`define PCX_IMISS_RQ 5'b10000
`define PCX_STORE_RQ 5'b00001
`define PCX_FWD_RQs 5'b01101
`define PCX_FWD_RPYs 5'b01110
//// CPX packet type ////
//`define CPX_LOAD_RET 4'b0000
`define CPX_LOAD_RET 4'b1000
`define CPX_ST_ACK 4'b0100
//`define CPX_IFILL_RET 4'b0001
`define CPX_IFILL_RET 4'b1001
`define CPX_INT_RET 4'b0111
`define CPX_INT_SOC 4'b1101
//`define CPX_FWD_RQ_RET 4'b1010
//`define CPX_FWD_RPY_RET 4'b1011
//// Global CSR decode ////
/////8'hA0 ~ BF L2 CSR////
`define DMU_PIO 4'hC // C0 ~ CF
`define SSI_ADDR 12'hFF_F
`define SSI_ADDR_TIMEOUT_REG 40'hFF_0001_0088
`define SSI_ADDR_LOG_REG 40'hFF_0000_0018
`define SSI_REQ_PAR 3'b101
`define SSI_ACK_PAR 3'b010
ucbif_ucb_ifill_nack_vld,
wire timeout_reg_addr_match;
wire [24:0] next_timeout_reg;
wire [23:0] timeout_timeval;
wire next_ucbif_sif_rdata_accpt;
wire next_ucbif_sif_timeout_accpt;
wire [5:0] next_ucbif_ucb_thr_id_out;
wire [1:0] next_ucbif_ucb_buf_id_out;
wire ucbif_ucb_thr_id_out_en;
wire ucbif_ucb_buf_id_out_en;
wire ext_int_l_negedge_rst_l;
wire next_ext_int_l_negedge;
wire u_dff_io_jbi_ext_int_l_pre_sync_scanin;
wire u_dff_io_jbi_ext_int_l_pre_sync_scanout;
wire io_jbi_ext_int_l_pre_sync;
wire u_dff_io_jbi_ext_int_l_sync_scanin;
wire u_dff_io_jbi_ext_int_l_sync_scanout;
wire io_jbi_ext_int_l_sync;
wire u_dff_timeout_reg_scanin;
wire u_dff_timeout_reg_scanout;
wire u_dff_log_parity_reg_scanin;
wire u_dff_log_parity_reg_scanout;
wire u_dff_log_tout_reg_scanin;
wire u_dff_log_tout_reg_scanout;
wire u_dff_ext_int_l_scanin;
wire u_dff_ext_int_l_scanout;
wire u_dff_ext_int_l_d1_scanin;
wire u_dff_ext_int_l_d1_scanout;
wire u_dff_ext_int_l_d2_scanin;
wire u_dff_ext_int_l_d2_scanout;
wire u_dff_ext_int_l_d3_scanin;
wire u_dff_ext_int_l_d3_scanout;
wire u_dff_ext_int_l_d4_scanin;
wire u_dff_ext_int_l_d4_scanout;
wire u_dff_ext_int_l_d5_scanin;
wire u_dff_ext_int_l_d5_scanout;
wire u_dff_ext_int_l_d6_scanin;
wire u_dff_ext_int_l_d6_scanout;
wire u_dff_ext_int_l_d7_scanin;
wire u_dff_ext_int_l_d7_scanout;
wire u_dffrl_if_sm_scanin;
wire u_dffrl_if_sm_scanout;
wire u_dffrl_ucbif_sif_rdata_accpt_scanin;
wire u_dffrl_ucbif_sif_rdata_accpt_scanout;
wire u_dffrl_ucbif_sif_timeout_accpt_scanin;
wire u_dffrl_ucbif_sif_timeout_accpt_scanout;
wire u_dffrl_err_int_scanin;
wire u_dffrl_err_int_scanout;
wire n_ext_int_l_negedge;
wire u_dffrl_ext_int_l_negedge_scanin;
wire u_dffrl_ext_int_l_negedge_scanout;
wire toreg_ld0_ff_scanin;
wire toreg_ld0_ff_scanout;
wire toreg_ld1_ff_scanin;
wire toreg_ld1_ff_scanout;
wire u_dffrle_ifill_scanin;
wire u_dffrle_ifill_scanout;
wire u_dffrle_ucbif_ucb_thr_id_out_scanin;
wire u_dffrle_ucbif_ucb_thr_id_out_scanout;
wire u_dffrle_ucbif_ucb_buf_id_out_scanin;
wire u_dffrle_ucbif_ucb_buf_id_out_scanout;
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
input ucb_ucbif_rd_req_vld;
input ucb_ucbif_ifill_req_vld; // 4-byte read
input ucb_ucbif_wr_req_vld;
input [5:0] ucb_ucbif_thr_id_in;
input [1:0] ucb_ucbif_buf_id_in;
input [2:0] ucb_ucbif_size_in;
input [39:0] ucb_ucbif_addr_in;
input [63:0] ucb_ucbif_data_in;
input ucb_ucbif_ack_busy;
input ucb_ucbif_int_busy;
output ucbif_ucb_req_acpted;
output ucbif_ucb_rd_ack_vld;
output ucbif_ucb_rd_nack_vld;
output ucbif_ucb_ifill_ack_vld;
output ucbif_ucb_ifill_nack_vld;
output [5:0] ucbif_ucb_thr_id_out;
output [1:0] ucbif_ucb_buf_id_out;
output [63:0] ucbif_ucb_data_out;
output ucbif_ucb_int_vld;
output [3:0] ucbif_ucb_int_type;
output [8:0] ucbif_ucb_dev_id;
output ucbif_sif_rw; //instr w/o data will have no dlen asserted
output [1:0] ucbif_sif_size;
output [27:0] ucbif_sif_addr;
output [63:0] ucbif_sif_wdata;
input [63:0] sif_ucbif_rdata;
input sif_ucbif_rdata_vld;
output ucbif_sif_rdata_accpt;
output ucbif_sif_timeout_accpt;
input sif_ucbif_timeout_rw;
output [23:0] ucbif_sif_timeval;
//parameter SSI_ADDR = 12'hFF_F,
//SSI_ADDR_TIMEOUT_REG = 40'hFF_0001_0088,
//SSI_ADDR_LOG_REG = 40'hFF_0000_0018;
//parameter IF_IDLE = 2'b00,
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
reg [63:0] ucbif_ucb_data_out;
reg [8:0] ucbif_ucb_dev_id;
reg [1:0] ucbif_sif_size;
//-----------------------
//-----------------------
assign timeout_reg_en = if_sm[1:0] == `IF_ACPT
//assign next_timeout_reg[24:0] = ~toreg_ld1_n ? 25'h080_0000 :
assign next_timeout_reg[24:0] = ~toreg_ld1_n ? 25'h020_0000 :
timeout_reg_en ? ucb_ucbif_data_in[24:0] : timeout_reg[24:0] ;
assign timeout_timeval[23:0] = timeout_reg[23:0];
assign timeout_erren = timeout_reg[24];
assign ucbif_sif_timeval = timeout_timeval;
//*******************************************************************************
//*******************************************************************************
always @(/*AUTOSENSE*/if_sm or sif_ucbif_busy or ssi_addr_match
or ucb_ucbif_ack_busy or ucb_ucbif_ifill_req_vld
or ucb_ucbif_rd_req_vld or ucb_ucbif_size_in
or ucb_ucbif_wr_req_vld) begin
if ((ucb_ucbif_rd_req_vld
| ucb_ucbif_ifill_req_vld)
if ( (~ucb_ucbif_ifill_req_vld
& ucb_ucbif_size_in == 3'b111) //drop all 16-byte req and nack reads
| (ucb_ucbif_ifill_req_vld
& ~ssi_addr_match)) //drop ifill access to ssi csr
next_if_sm[1:0] = `IF_DROP ;
next_if_sm[1:0] = `IF_ACPT ;
next_if_sm[1:0] = `IF_IDLE ;
next_if_sm[1:0] = `IF_IDLE ;
next_if_sm[1:0] = `IF_ACPT ; // wait until ~ack_busy to accept reg read
next_if_sm[1:0] = `IF_IDLE ;
if ( (ucb_ucbif_rd_req_vld | ucb_ucbif_ifill_req_vld)
next_if_sm[1:0] = `IF_DROP ;
next_if_sm[1:0] = `IF_IDLE ;
assign ucbif_ucb_req_acpted = (if_sm[1:0] == `IF_ACPT
& ~( ~ssi_addr_match // reg read
| ( if_sm[1:0] == `IF_DROP
& next_if_sm[1:0] == `IF_IDLE);
assign ifill_en = next_if_sm[1:0] == `IF_ACPT ;
assign next_ifill = ucb_ucbif_ifill_req_vld;
assign timeout_reg_addr_match = ucb_ucbif_addr_in[39:0] == `SSI_ADDR_TIMEOUT_REG ;
assign log_reg_addr_match = ucb_ucbif_addr_in[39:0] == `SSI_ADDR_LOG_REG ;
assign ssi_addr_match = ucb_ucbif_addr_in[39:28] == `SSI_ADDR ;
//-----------------------
//-----------------------
assign log_reg[1] = log_parity_reg;
assign log_reg[0] = log_tout_reg;
assign log_reg_en = if_sm[1:0] == `IF_ACPT
assign log_par_err = sif_ucbif_par_err
| ucbif_sif_rdata_accpt);
assign log_timeout = sif_ucbif_timeout
& ucbif_sif_timeout_accpt
always @ ( /*AUTOSENSE*/log_par_err or log_parity_reg or log_reg_en
or ucb_ucbif_data_in) begin
if (log_reg_en & ucb_ucbif_data_in[1])
next_log_parity_reg = 1'b0;
next_log_parity_reg = 1'b1;
next_log_parity_reg = log_parity_reg;
always @ ( /*AUTOSENSE*/log_reg_en or log_timeout or log_tout_reg
or ucb_ucbif_data_in) begin
if (log_reg_en & ucb_ucbif_data_in[0])
next_log_tout_reg = 1'b0;
next_log_tout_reg = 1'b1;
next_log_tout_reg = log_tout_reg;
//------------------------
// Launch SSI Transaction
//------------------------
assign ucbif_sif_vld = if_sm[1:0] == `IF_IDLE
& next_if_sm[1:0] == `IF_ACPT
assign ucbif_sif_rw = ~ucb_ucbif_wr_req_vld;
assign ucbif_sif_addr = ucb_ucbif_addr_in[27:0];
assign ucbif_sif_wdata = ucb_ucbif_data_in[63:0];
always @ ( /*AUTOSENSE*/ucb_ucbif_ifill_req_vld or ucb_ucbif_size_in) begin
if (ucb_ucbif_ifill_req_vld)
ucbif_sif_size = ucb_ucbif_size_in[1:0];
//*******************************************************************************
//*******************************************************************************
assign ack_vld = (sif_ucbif_rdata_vld
& ~ucb_ucbif_ack_busy) //SSI rd return
| (if_sm[1:0] == `IF_ACPT
& ~ssi_addr_match // reg addr match
assign ucbif_ucb_rd_ack_vld = ack_vld & ~sif_ucbif_par_err & ~ifill;
assign ucbif_ucb_ifill_ack_vld = ack_vld & ~sif_ucbif_par_err & ifill;
assign ucbif_ucb_rd_nack_vld = ( ~ifill
& ( (ack_vld & sif_ucbif_par_err)
| (if_sm[1:0] == `IF_DROP
assign ucbif_ucb_ifill_nack_vld = (ifill
& ( (ack_vld & sif_ucbif_par_err)
| (if_sm[1:0] == `IF_DROP
& ucb_ucbif_ifill_req_vld
always @(/*AUTOSENSE*/if_sm or log_reg or sif_ucbif_rdata
or sif_ucbif_timeout or timeout_reg or ucb_ucbif_addr_in) begin
if (if_sm[1:0] == `IF_IDLE)
ucbif_ucb_data_out[63:0] = sif_ucbif_rdata[63:0];
else if (sif_ucbif_timeout)
ucbif_ucb_data_out[63:0] = 64'b0;
case (ucb_ucbif_addr_in[39:0])
`SSI_ADDR_TIMEOUT_REG: ucbif_ucb_data_out[63:0] = { 39'b0, timeout_reg[24:0] };
`SSI_ADDR_LOG_REG: ucbif_ucb_data_out[63:0] = { 62'b0, log_reg[1:0] };
default: ucbif_ucb_data_out[63:0] = 64'b0;
assign next_ucbif_sif_rdata_accpt = sif_ucbif_rdata_vld
assign next_ucbif_sif_timeout_accpt = sif_ucbif_timeout
& ~ucbif_sif_timeout_accpt
& ( ~sif_ucbif_timeout_rw
assign next_ucbif_ucb_thr_id_out[5:0] = ucb_ucbif_thr_id_in[5:0];
assign next_ucbif_ucb_buf_id_out[1:0] = ucb_ucbif_buf_id_in[1:0];
assign ucbif_ucb_thr_id_out_en = next_if_sm[1:0] != `IF_IDLE ;
assign ucbif_ucb_buf_id_out_en = next_if_sm[1:0] != `IF_IDLE ;
//*******************************************************************************
//*******************************************************************************
assign err_int_rst_l = ~err_int_accpt;
assign next_err_int = err_int | log_par_err | log_timeout;
assign ext_int_l_negedge_rst_l = ~ext_int_accpt;
assign next_ext_int_l_negedge = ~ext_int_l
// - for simplicity, always give error interrupts priority
assign err_int_accpt = ~ucb_ucbif_int_busy & err_int;
assign ext_int_accpt = ~ucb_ucbif_int_busy & ~err_int & ext_int_l_negedge;
assign ucbif_ucb_int_vld = err_int_accpt | ext_int_accpt;
always @ ( /*AUTOSENSE*/err_int_accpt) begin
//original IOB in N1 only looks at the lower 2 bit of the dev_id
//ucbif_ucb_dev_id = 9'd17;
//ucbif_ucb_dev_id = 9'd30;
assign ucbif_ucb_int_type = 4'b1000;
//*******************************************************************************
//*******************************************************************************
ncu_ssiuif_ctl_msff_ctl_macro__width_1 u_dff_io_jbi_ext_int_l_pre_sync
.scan_in(u_dff_io_jbi_ext_int_l_pre_sync_scanin),
.scan_out(u_dff_io_jbi_ext_int_l_pre_sync_scanout),
.dout (io_jbi_ext_int_l_pre_sync),
ncu_ssiuif_ctl_msff_ctl_macro__width_1 u_dff_io_jbi_ext_int_l_sync
.scan_in(u_dff_io_jbi_ext_int_l_sync_scanin),
.scan_out(u_dff_io_jbi_ext_int_l_sync_scanout),
.dout (io_jbi_ext_int_l_sync),
.din (io_jbi_ext_int_l_pre_sync),
//*******************************************************************************
//*******************************************************************************
ncu_ssiuif_ctl_msff_ctl_macro__width_25 u_dff_timeout_reg
.scan_in(u_dff_timeout_reg_scanin),
.scan_out(u_dff_timeout_reg_scanout),
.dout (timeout_reg[24:0]),
.din (next_timeout_reg[24:0]),
ncu_ssiuif_ctl_msff_ctl_macro__width_1 u_dff_log_parity_reg
.scan_in(u_dff_log_parity_reg_scanin),
.scan_out(u_dff_log_parity_reg_scanout),
.din (next_log_parity_reg),
ncu_ssiuif_ctl_msff_ctl_macro__width_1 u_dff_log_tout_reg
.scan_in(u_dff_log_tout_reg_scanin),
.scan_out(u_dff_log_tout_reg_scanout),
.din (next_log_tout_reg),
ncu_ssiuif_ctl_msff_ctl_macro__width_1 u_dff_ext_int_l
.scan_in(u_dff_ext_int_l_scanin),
.scan_out(u_dff_ext_int_l_scanout),
.din (io_jbi_ext_int_l_sync),
ncu_ssiuif_ctl_msff_ctl_macro__width_1 u_dff_ext_int_l_d1
.scan_in(u_dff_ext_int_l_d1_scanin),
.scan_out(u_dff_ext_int_l_d1_scanout),
ncu_ssiuif_ctl_msff_ctl_macro__width_1 u_dff_ext_int_l_d2
.scan_in(u_dff_ext_int_l_d2_scanin),
.scan_out(u_dff_ext_int_l_d2_scanout),
ncu_ssiuif_ctl_msff_ctl_macro__width_1 u_dff_ext_int_l_d3
.scan_in(u_dff_ext_int_l_d3_scanin),
.scan_out(u_dff_ext_int_l_d3_scanout),
ncu_ssiuif_ctl_msff_ctl_macro__width_1 u_dff_ext_int_l_d4
.scan_in(u_dff_ext_int_l_d4_scanin),
.scan_out(u_dff_ext_int_l_d4_scanout),
ncu_ssiuif_ctl_msff_ctl_macro__width_1 u_dff_ext_int_l_d5
.scan_in(u_dff_ext_int_l_d5_scanin),
.scan_out(u_dff_ext_int_l_d5_scanout),
ncu_ssiuif_ctl_msff_ctl_macro__width_1 u_dff_ext_int_l_d6
.scan_in(u_dff_ext_int_l_d6_scanin),
.scan_out(u_dff_ext_int_l_d6_scanout),
ncu_ssiuif_ctl_msff_ctl_macro__width_1 u_dff_ext_int_l_d7
.scan_in(u_dff_ext_int_l_d7_scanin),
.scan_out(u_dff_ext_int_l_d7_scanout),
//*******************************************************************************
//*******************************************************************************
ncu_ssiuif_ctl_msff_ctl_macro__width_2 u_dffrl_if_sm
.scan_in(u_dffrl_if_sm_scanin),
.scan_out(u_dffrl_if_sm_scanout),
ncu_ssiuif_ctl_msff_ctl_macro__width_1 u_dffrl_ucbif_sif_rdata_accpt
.scan_in(u_dffrl_ucbif_sif_rdata_accpt_scanin),
.scan_out(u_dffrl_ucbif_sif_rdata_accpt_scanout),
.dout (ucbif_sif_rdata_accpt),
.din (next_ucbif_sif_rdata_accpt),
ncu_ssiuif_ctl_msff_ctl_macro__width_1 u_dffrl_ucbif_sif_timeout_accpt
.scan_in(u_dffrl_ucbif_sif_timeout_accpt_scanin),
.scan_out(u_dffrl_ucbif_sif_timeout_accpt_scanout),
.dout (ucbif_sif_timeout_accpt),
.din (next_ucbif_sif_timeout_accpt),
assign n_err_int = err_int_rst_l ? next_err_int : 1'b0 ;
ncu_ssiuif_ctl_msff_ctl_macro__width_1 u_dffrl_err_int
.scan_in(u_dffrl_err_int_scanin),
.scan_out(u_dffrl_err_int_scanout),
assign n_ext_int_l_negedge = ext_int_l_negedge_rst_l ? next_ext_int_l_negedge : 1'b0 ;
ncu_ssiuif_ctl_msff_ctl_macro__width_1 u_dffrl_ext_int_l_negedge
.scan_in(u_dffrl_ext_int_l_negedge_scanin),
.scan_out(u_dffrl_ext_int_l_negedge_scanout),
.dout (ext_int_l_negedge),
.din (n_ext_int_l_negedge),
ncu_ssiuif_ctl_msff_ctl_macro__width_1 toreg_ld0_ff
.scan_in(toreg_ld0_ff_scanin),
.scan_out(toreg_ld0_ff_scanout),
ncu_ssiuif_ctl_msff_ctl_macro__width_1 toreg_ld1_ff
.scan_in(toreg_ld1_ff_scanin),
.scan_out(toreg_ld1_ff_scanout),
//*******************************************************************************
//*******************************************************************************
ncu_ssiuif_ctl_msff_ctl_macro__en_1__width_1 u_dffrle_ifill
.scan_in(u_dffrle_ifill_scanin),
.scan_out(u_dffrle_ifill_scanout),
ncu_ssiuif_ctl_msff_ctl_macro__en_1__width_6 u_dffrle_ucbif_ucb_thr_id_out
.scan_in(u_dffrle_ucbif_ucb_thr_id_out_scanin),
.scan_out(u_dffrle_ucbif_ucb_thr_id_out_scanout),
.dout (ucbif_ucb_thr_id_out[5:0]),
.en (ucbif_ucb_thr_id_out_en),
.din (next_ucbif_ucb_thr_id_out[5:0]),
ncu_ssiuif_ctl_msff_ctl_macro__en_1__width_2 u_dffrle_ucbif_ucb_buf_id_out
.scan_in(u_dffrle_ucbif_ucb_buf_id_out_scanin),
.scan_out(u_dffrle_ucbif_ucb_buf_id_out_scanout),
.dout (ucbif_ucb_buf_id_out[1:0]),
.en (ucbif_ucb_buf_id_out_en),
.din (next_ucbif_ucb_buf_id_out[1:0]),
//*******************************************************************************
//*******************************************************************************
//always @ ( /*AUTOSENSE*/if_sm or sif_ucbif_rdata_vld) begin
//if (if_sm == IF_ACPT & sif_ucbif_rdata_vld)
//$dispmon ("jbi_ssi_ucbif", 49, "%d %m: ERROR - unexpected read return in IF_ACPT state", $time);
/**** adding clock header ****/
ncu_ssiuif_ctl_l1clkhdr_ctl_macro clkgen (
/*** building tcu port ***/
assign pce_ov = tcu_pce_ov;
assign stop = tcu_clk_stop;
assign u_dff_io_jbi_ext_int_l_pre_sync_scanin = scan_in ;
assign u_dff_io_jbi_ext_int_l_sync_scanin = u_dff_io_jbi_ext_int_l_pre_sync_scanout;
assign u_dff_timeout_reg_scanin = u_dff_io_jbi_ext_int_l_sync_scanout;
assign u_dff_log_parity_reg_scanin = u_dff_timeout_reg_scanout;
assign u_dff_log_tout_reg_scanin = u_dff_log_parity_reg_scanout;
assign u_dff_ext_int_l_scanin = u_dff_log_tout_reg_scanout;
assign u_dff_ext_int_l_d1_scanin = u_dff_ext_int_l_scanout ;
assign u_dff_ext_int_l_d2_scanin = u_dff_ext_int_l_d1_scanout;
assign u_dff_ext_int_l_d3_scanin = u_dff_ext_int_l_d2_scanout;
assign u_dff_ext_int_l_d4_scanin = u_dff_ext_int_l_d3_scanout;
assign u_dff_ext_int_l_d5_scanin = u_dff_ext_int_l_d4_scanout;
assign u_dff_ext_int_l_d6_scanin = u_dff_ext_int_l_d5_scanout;
assign u_dff_ext_int_l_d7_scanin = u_dff_ext_int_l_d6_scanout;
assign u_dffrl_if_sm_scanin = u_dff_ext_int_l_d7_scanout;
assign u_dffrl_ucbif_sif_rdata_accpt_scanin = u_dffrl_if_sm_scanout ;
assign u_dffrl_ucbif_sif_timeout_accpt_scanin = u_dffrl_ucbif_sif_rdata_accpt_scanout;
assign u_dffrl_err_int_scanin = u_dffrl_ucbif_sif_timeout_accpt_scanout;
assign u_dffrl_ext_int_l_negedge_scanin = u_dffrl_err_int_scanout ;
assign toreg_ld0_ff_scanin = u_dffrl_ext_int_l_negedge_scanout;
assign toreg_ld1_ff_scanin = toreg_ld0_ff_scanout ;
assign u_dffrle_ifill_scanin = toreg_ld1_ff_scanout ;
assign u_dffrle_ucbif_ucb_thr_id_out_scanin = u_dffrle_ifill_scanout ;
assign u_dffrle_ucbif_ucb_buf_id_out_scanin = u_dffrle_ucbif_ucb_thr_id_out_scanout;
assign scan_out = u_dffrle_ucbif_ucb_buf_id_out_scanout;
// verilog-library-directories:("." "../../common/rtl")
// verilog-auto-sense-defines-constant:t
// any PARAMS parms go into naming of macro
module ncu_ssiuif_ctl_msff_ctl_macro__width_1 (
assign fdin[0:0] = din[0:0];
// any PARAMS parms go into naming of macro
module ncu_ssiuif_ctl_msff_ctl_macro__width_25 (
assign fdin[24:0] = din[24:0];
.so({so[23:0],scan_out}),
// any PARAMS parms go into naming of macro
module ncu_ssiuif_ctl_msff_ctl_macro__width_2 (
assign fdin[1:0] = din[1:0];
// any PARAMS parms go into naming of macro
module ncu_ssiuif_ctl_msff_ctl_macro__en_1__width_1 (
assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}});
// any PARAMS parms go into naming of macro
module ncu_ssiuif_ctl_msff_ctl_macro__en_1__width_6 (
assign fdin[5:0] = (din[5:0] & {6{en}}) | (dout[5:0] & ~{6{en}});
// any PARAMS parms go into naming of macro
module ncu_ssiuif_ctl_msff_ctl_macro__en_1__width_2 (
assign fdin[1:0] = (din[1:0] & {2{en}}) | (dout[1:0] & ~{2{en}});
// any PARAMS parms go into naming of macro
module ncu_ssiuif_ctl_l1clkhdr_ctl_macro (