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// OpenSPARC T2 Processor File: niu_ipp_ffl_arbiter.v
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/**********************************************************
***********************************************************
File name : niu_ipp_ffl_arbiter.v
Module(s) name : niu_ipp_ffl_arbiter
Original: : ipp_arbiter.v main.32, label: IPP_RTL_2.3 IPP_VERIF_2.5
Parent modules : niu_ipp_top.v
Author's name : Jonathan Shen, George Chu
Description : 4_to_1 round-robin arbiter for fflp.
************************************************************
***********************************************************/
module niu_ipp_ffl_arbiter(
-req ipp_ffl_req0 ipp_ffl_req1 ipp_ffl_req2 ipp_ffl_req3
-gnt ffl_arb_ack0_pre ffl_arb_ack1_pre ffl_arb_ack2_pre ffl_arb_ack3_pre
-clock clk -reset reset -message "IPP_FFL arbiter"
input [127:0] ipp_fflp_data0;
input [11:0] ipp_fflp_mac_default0;
input [127:0] ipp_fflp_data1;
input [11:0] ipp_fflp_mac_default1;
input [127:0] ipp_fflp_data2;
input [11:0] ipp_fflp_mac_default2;
input [127:0] ipp_fflp_data3;
input [11:0] ipp_fflp_mac_default3;
output [127:0] ipp_fflp_data;
output [1:0] ipp_fflp_port;
output [11:0] ipp_fflp_mac_default;
reg [127:0] ipp_fflp_data_pre;
reg [1:0] ipp_fflp_port_pre;
reg [11:0] ipp_fflp_mac_default_pre;
wire [127:0] ipp_fflp_data;
wire [1:0] ipp_fflp_port;
wire [11:0] ipp_fflp_mac_default;
assign sel[0] = ffl_arb_ack0;
assign sel[1] = ffl_arb_ack1;
assign sel[2] = ffl_arb_ack2;
assign sel[3] = ffl_arb_ack3;
/****** state machine ******/
always @ (ipp_ffl_req0 or ipp_ffl_req1 or ipp_ffl_req2 or
ipp_ffl_req3 or cur_state)
case (cur_state) // synopsys parallel_case full_case
if (ipp_ffl_req0 == 1'h1)
else if (ipp_ffl_req1 == 1'h1)
else if (ipp_ffl_req2 == 1'h1)
else if (ipp_ffl_req3 == 1'h1)
if (ipp_ffl_req1 == 1'h1)
else if (ipp_ffl_req2 == 1'h1)
else if (ipp_ffl_req3 == 1'h1)
else if (ipp_ffl_req0 == 1'h1)
if (ipp_ffl_req2 == 1'h1)
else if (ipp_ffl_req3 == 1'h1)
else if (ipp_ffl_req0 == 1'h1)
else if (ipp_ffl_req1 == 1'h1)
if (ipp_ffl_req3 == 1'h1)
else if (ipp_ffl_req0 == 1'h1)
else if (ipp_ffl_req1 == 1'h1)
else if (ipp_ffl_req2 == 1'h1)
cur_state[1:0] <= nex_state[1:0];
/****** end of state machine ******/
/****** 4:1 mux for ipp_fflp_dvalid ******/
always @ (sel or ipp_fflp_dvalid0 or ipp_fflp_dvalid1 or ipp_fflp_dvalid2
case (sel[3:0]) // synopsys parallel_case full_case
4'b0001: ipp_fflp_dvalid_pre = ipp_fflp_dvalid0;
4'b0010: ipp_fflp_dvalid_pre = ipp_fflp_dvalid1;
4'b0100: ipp_fflp_dvalid_pre = ipp_fflp_dvalid2;
4'b1000: ipp_fflp_dvalid_pre = ipp_fflp_dvalid3;
default: ipp_fflp_dvalid_pre = ipp_fflp_dvalid0;
/****** 4:1 mux for data ******/
always @ (sel or ipp_fflp_data0 or ipp_fflp_data1 or ipp_fflp_data2
case (sel[3:0]) // synopsys parallel_case full_case
4'b0001: ipp_fflp_data_pre[127:0] = ipp_fflp_data0[127:0];
4'b0010: ipp_fflp_data_pre[127:0] = ipp_fflp_data1[127:0];
4'b0100: ipp_fflp_data_pre[127:0] = ipp_fflp_data2[127:0];
4'b1000: ipp_fflp_data_pre[127:0] = ipp_fflp_data3[127:0];
default: ipp_fflp_data_pre[127:0] = ipp_fflp_data0[127:0];
/****** 4:1 mux port ******/
case (sel[3:0]) // synopsys parallel_case full_case
4'b0001: ipp_fflp_port_pre[1:0] = 2'b00;
4'b0010: ipp_fflp_port_pre[1:0] = 2'b01;
4'b0100: ipp_fflp_port_pre[1:0] = 2'b10;
4'b1000: ipp_fflp_port_pre[1:0] = 2'b11;
default: ipp_fflp_port_pre[1:0] = 2'b00;
/****** 4:1 mux for mac_default ******/
always @ (sel or ipp_fflp_mac_default0 or ipp_fflp_mac_default1 or
ipp_fflp_mac_default2 or ipp_fflp_mac_default3)
case (sel[3:0]) // synopsys parallel_case full_case
4'b0001: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default0[11:0];
4'b0010: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default1[11:0];
4'b0100: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default2[11:0];
4'b1000: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default3[11:0];
default: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default0[11:0];
assign ffl_arb_ack0 = ffl_arb_ack0_pre;
assign ffl_arb_ack1 = ffl_arb_ack1_pre;
assign ffl_arb_ack2 = ffl_arb_ack2_pre;
assign ffl_arb_ack3 = ffl_arb_ack3_pre;
assign sel[0] = ffl_arb_ack0;
assign sel[1] = ffl_arb_ack1;
/****** state machine ******/
always @ (ipp_ffl_req0 or ipp_ffl_req1 or
case (cur_state) // synopsys parallel_case full_case
if (ipp_ffl_req0 == 1'h1)
else if (ipp_ffl_req1 == 1'h1)
if (ipp_ffl_req1 == 1'h1)
else if (ipp_ffl_req0 == 1'h1)
/****** end of state machine ******/
/****** 2:1 mux for ipp_fflp_dvalid ******/
always @ (sel or ipp_fflp_dvalid0 or ipp_fflp_dvalid1)
case (sel[1:0]) // synopsys parallel_case
2'b01: ipp_fflp_dvalid_pre = ipp_fflp_dvalid0;
2'b10: ipp_fflp_dvalid_pre = ipp_fflp_dvalid1;
default: ipp_fflp_dvalid_pre = ipp_fflp_dvalid0;
/****** 2:1 mux for data ******/
always @ (sel or ipp_fflp_data0 or ipp_fflp_data1)
case (sel[1:0]) // synopsys parallel_case
2'b01: ipp_fflp_data_pre[127:0] = ipp_fflp_data0[127:0];
2'b10: ipp_fflp_data_pre[127:0] = ipp_fflp_data1[127:0];
default: ipp_fflp_data_pre[127:0] = ipp_fflp_data0[127:0];
/****** 2:1 mux port ******/
case (sel[1:0]) // synopsys parallel_case
2'b01: ipp_fflp_port_pre[1:0] = 2'b0;
2'b10: ipp_fflp_port_pre[1:0] = 2'b1;
default: ipp_fflp_port_pre[1:0] = 2'b0;
/****** 2:1 mux for mac_default ******/
always @ (sel or ipp_fflp_mac_default0 or ipp_fflp_mac_default1)
case (sel[1:0]) // synopsys parallel_case full_case
2'b01: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default0[11:0];
2'b10: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default1[11:0];
default: ipp_fflp_mac_default_pre[11:0] = ipp_fflp_mac_default0[11:0];
assign ffl_arb_ack0 = ffl_arb_ack0_pre;
assign ffl_arb_ack1 = ffl_arb_ack1_pre;
ipp_reg_r_1 reg_r_1_dva (.di(ipp_fflp_dvalid_pre), .rs(reset),.ck(clk),.qo(ipp_fflp_dvalid));
ipp_reg_r_128 reg_r_128_dat (.di(ipp_fflp_data_pre[127:0]), .rs(reset),.ck(clk),.qo(ipp_fflp_data[127:0]));
ipp_reg_r_2 reg_r_2_por (.di(ipp_fflp_port_pre[1:0]), .rs(reset),.ck(clk),.qo(ipp_fflp_port[1:0]));
ipp_reg_r_12 reg_r_12_def (.di(ipp_fflp_mac_default_pre[11:0]),.rs(reset),.ck(clk),.qo(ipp_fflp_mac_default[11:0]));