// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: niu_ipp_lib.v
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/*********************************************************
***********************************************************
File name : niu_ipp_lib.v
Module(s) name : niu_ipp_lib
Original: : ipp_lib.v main.11, label:
Author's name : Jonathan Shen, George Chu
************************************************************
***********************************************************/
module ipp_FD1(D, CP, Q);
/***********************************
***********************************/
module ipp_RegDff (din, clk, qout);
output [dwidth-1:0] qout;
//*****************************
//*****************************
module ipp_xREG (din, clk, en, reset, qout);
output [dwidth-1:0] qout;
endmodule // end of ipp_xREG
//*****************************
// Register ipp_RAC_Plus1_Reg
//*****************************
module ipp_RAC_Plus1_Reg (clk, reset, iInc, iAutoClrEn, iMaxValue,
iLoad, iLoadValue, oDout, oMaxValueReached);
input clk,reset; // global signals
input iInc; // Count Enable
input [dwidth-1:0] iMaxValue; // compared value
input [dwidth-1:0] iLoadValue; // compared value
output[dwidth-1:0] oDout;
wire oMaxValueReached = (oDout == iMaxValue);
else if (oMaxValueReached)
oDout <= oDout; // Stay at max value.
oDout <= oDout; // Hold the value.
endmodule // end of ipp_RAC_Plus1_Reg
/************************************
*************************************/
module ipp_puls_gen (reset, clk, signal_in, puls_out);
input reset, clk, signal_in;
wire puls_out = signal_in & Qb;
/************************************
*************************************/
module ipp_falling_edge_puls_gen (reset, clk, signal_in, puls_out);
input reset, clk, signal_in;
wire puls_out = ~signal_in & Q;
//*****************************
//*****************************
module ipp_PlsGen2 (sig_in, clk, lead, trail);
ipp_FD1 sig_out_FD1(.D(sig_in),.CP(clk),.Q(sig_out));
assign lead = sig_in & ~sig_out;
assign trail = ~sig_in & sig_out;
//*****************************
//*****************************
module ipp_RSFF (reset, clk, set, rst, Q);
input reset, clk, set, rst;
endmodule // end of Reset Set Flip Flop
//*****************************
//*****************************
module ipp_RAC_FF (clk, reset, set, rst,
input clk, reset; // global signals
input load_data; // compared value
/****************************************************************
* ipp_phase_sm2: Use this state machine to count phases.
*****************************************************************/
module ipp_phase_sm2 (clk, reset, valid, rx_tag,
rd_eop, rd_status, cur_state);
reg [1:0] cur_state, nex_state;
parameter StIdle = 2'b00;
parameter StWait1stTag = 2'b01;
parameter StWait2ndTag = 2'b10;
always @ (valid or rx_tag or cur_state)
case (cur_state) // synopsys parallel_case full_case
nex_state = StWait1stTag; // 'h1
nex_state = cur_state; // 'h0
nex_state = cur_state; // 'h1
nex_state = StIdle; // 'h0
// $display("ERROR: MAC status is ahead of end of packet at simtime = %d", $time);
nex_state = StWait2ndTag; // 'h2
nex_state = StIdle; // 'h0
nex_state = cur_state; // 'h2
nex_state = StIdle; // 'h0
if (rx_tag[1:0] == 2'b01)
nex_state = StIdle; // 'h0
nex_state = cur_state; // 'h2
endcase // end major endcase
endmodule // end of ipp_phase_sm2
module ipp_spare(di, reset, clk, qo);
ipp_reg_r_1 ipp_reg_r_1_dum (.di(di), .rs(reset), .ck(clk), .qo(qo));
// =====================================================================
// This is a FSM for controlling IPP_EN
// Original: : ipp_en_rst_fsm in ipp.v main.70, label: IPP_VERIF_1.84
module niu_ipp_en_rst_fsm (clk, reset, ipp_enable,
wr_ipp_en_bit0, mac_stat, IFG,
rst_ipp_en, ipp_en_rst_fsm_curstate);
output [1:0] ipp_en_rst_fsm_curstate;
wire [1:0] ipp_en_rst_fsm_curstate = cur_state[1:0];
always @(cur_state or ipp_enable or wr_ipp_en_bit0 or mac_stat or IFG)
casex(cur_state) // synopsys parallel_case full_case
casex ({wr_ipp_en_bit0, IFG})
2'b0x: nex_state = cur_state;
2'b10: nex_state = StIppEn2;
// =====================================================================
module ipp_reg_r_1 (di, rs, ck, qo);
module ipp_reg_r_2 (di, rs, ck, qo);
module ipp_reg_r_10 (di, rs, ck, qo);
module ipp_reg_r_11 (di, rs, ck, qo);
module ipp_reg_r_12 (di, rs, ck, qo);
module ipp_reg_r_16 (di, rs, ck, qo);
module ipp_reg_r_128 (di, rs, ck, qo);
module ipp_reg_r_130 (di, rs, ck, qo);
module ipp_reg_w_r_32 (di, wr, rs, ck, qo);
module ipp_reg_w_s_17 (di, wr, rs, ck, qo);
module ipp_reg_w_sti_r_rac_1 (di, wr, rs, rac, ck, qo);
else if (wr && !wrote) begin
module ipp_reg_w_sti_r_rac_5 (di, wr, rs, rac, ck, qo);
else if (wr && !wrote) begin
module ipp_reg_w_sti_r_rac_6 (di, wr, rs, rac, ck, qo);
else if (wr && !wrote) begin
module ipp_reg_w_sti_r_rac_11 (di, wr, rs, rac, ck, qo);
else if (wr && !wrote) begin
module ipp_reg_w_sti_r_rac_12 (di, wr, rs, rac, ck, qo);
else if (wr && !wrote) begin
module ipp_reg_w_sti_r_rac_16 (di, wr, rs, rac, ck, qo);
else if (wr && !wrote) begin
module niu_ipp_reset_blk (reset_l, clk, reset);