design/sys/iop/niu/rtl/niu_pio_reset.v

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// OpenSPARC T2 Processor File: niu_pio_reset.v
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/*********************************************************************
 *
 *  niu_pio_reset.v
 *
 *  Reset Block, includes LogicVision Reset Gating
 *
 *  Orignal Author(s):   Rahoul Puri
 *  Modifier(s):         Maya Suresh
 *  Project(s):          Neptune/Niagara 2
 *
 *  Copyright (c) 2003   Sun Microsystems, Inc.
 *
 *  All Rights Reserved.
 *
 *  This verilog model is the confidential and proprietary property of
 *  Sun Microsystems, Inc., and the possession or use of this model
 *  requires a written license from Sun Microsystems, Inc.
 *
 **********************************************************************/

module niu_pio_reset (
        SysClk,
        niu_reset_l,
        FUNC_MODE,
        Reset_L
       );

// Clock & Reset
input   SysClk;
input   niu_reset_l;
input   FUNC_MODE;

output  Reset_L;

/*--------------------------------------------------------------*/
// Registers & Wires
/*--------------------------------------------------------------*/
wire   iReset_L;

reg    resetDlyOneCycle_l;

/*--------------------------------------------------------------*/
// Assigns
/*--------------------------------------------------------------*/
assign iReset_L = ((resetDlyOneCycle_l & FUNC_MODE) | ~FUNC_MODE);

/*--------------------------------------------------------------*/
// Control Logic
/*--------------------------------------------------------------*/
 always @ (posedge SysClk)
   begin
     resetDlyOneCycle_l <= niu_reset_l;
   end

`ifdef NEPTUNE
   RTS_ROOT_BUF pio_reset_CTS_ROOT  (.Z(Reset_L)  ,.A(iReset_L));
`else
   assign Reset_L = iReset_L;

`endif


endmodule