// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: niu_rdmc_cache_acc_ctrl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// ========== Copyright Header End ============================================
module niu_rdmc_cache_acc_ctrl (
fetch_desp_resp_valid_array,
input[15:0] cache_rd_req;
input[7:0] cache_rd_ptr0;
input[7:0] cache_rd_ptr1;
input[7:0] cache_rd_ptr2;
input[7:0] cache_rd_ptr3;
input[7:0] cache_rd_ptr4;
input[7:0] cache_rd_ptr5;
input[7:0] cache_rd_ptr6;
input[7:0] cache_rd_ptr7;
input[7:0] cache_rd_ptr8;
input[7:0] cache_rd_ptr9;
input[7:0] cache_rd_ptr10;
input[7:0] cache_rd_ptr11;
input[7:0] cache_rd_ptr12;
input[7:0] cache_rd_ptr13;
input[7:0] cache_rd_ptr14;
input[7:0] cache_rd_ptr15;
input muxed_cache_rd_strobe_r;
input[147:0] cache_rd_data;
input[7:0] cache_wr_ptr0;
input[7:0] cache_wr_ptr1;
input[7:0] cache_wr_ptr2;
input[7:0] cache_wr_ptr3;
input[7:0] cache_wr_ptr4;
input[7:0] cache_wr_ptr5;
input[7:0] cache_wr_ptr6;
input[7:0] cache_wr_ptr7;
input[7:0] cache_wr_ptr8;
input[7:0] cache_wr_ptr9;
input[7:0] cache_wr_ptr10;
input[7:0] cache_wr_ptr11;
input[7:0] cache_wr_ptr12;
input[7:0] cache_wr_ptr13;
input[7:0] cache_wr_ptr14;
input[7:0] cache_wr_ptr15;
input[15:0] fetch_desp_resp_valid_array;
input rdmc_resp_data_valid;
output[7:0] cache_wr_addr;
output[7:0] cache_rd_addr;
output[15:0] cache_buf_rd_gnt;
output[147:0] cache_rd_data_reg;
reg[15:0] cache_buf_rd_gnt;
reg[147:0] cache_rd_data_reg;
wire[15:0] start_mask = 16'h1111;
wire[3:0] start_slide_num;
wire[15:0] start_mask_slide;
wire is_req = |cache_rd_req;
wire[15:0] pre_cache_rd_gnt;
always @ (state or is_req)
case (state) //synopsys parallel_case full_case
niu_rdmc_encode_32 encode_32_inst_a (
niu_rdmc_barrel_shl_32 barrel_shl_32_inst_a (
.shift (start_slide_num),
assign right_req = cache_rd_req & ~start_mask_slide;
assign left_req = cache_rd_req & start_mask_slide;
assign sel_left = !(left_req == 16'b0);
assign req_tmp = sel_left ? left_req : right_req;
niu_rdmc_pri_encode_32 pri_encode_32_inst_a (
token <= {token[14:0], token[15]};
cache_buf_rd_gnt <= 16'h0;
cache_buf_rd_gnt <= pre_cache_rd_gnt;
cache_buf_rd_gnt <= 16'h0;
wire[7:0] cache_rd_addr_tmp = {8{cache_buf_rd_gnt[0]}} & cache_rd_ptr0 |
{8{cache_buf_rd_gnt[1]}} & cache_rd_ptr1 |
{8{cache_buf_rd_gnt[2]}} & cache_rd_ptr2 |
{8{cache_buf_rd_gnt[3]}} & cache_rd_ptr3 |
{8{cache_buf_rd_gnt[4]}} & cache_rd_ptr4 |
{8{cache_buf_rd_gnt[5]}} & cache_rd_ptr5 |
{8{cache_buf_rd_gnt[6]}} & cache_rd_ptr6 |
{8{cache_buf_rd_gnt[7]}} & cache_rd_ptr7 |
{8{cache_buf_rd_gnt[8]}} & cache_rd_ptr8 |
{8{cache_buf_rd_gnt[9]}} & cache_rd_ptr9 |
{8{cache_buf_rd_gnt[10]}} & cache_rd_ptr10 |
{8{cache_buf_rd_gnt[11]}} & cache_rd_ptr11 |
{8{cache_buf_rd_gnt[12]}} & cache_rd_ptr12 |
{8{cache_buf_rd_gnt[13]}} & cache_rd_ptr13 |
{8{cache_buf_rd_gnt[14]}} & cache_rd_ptr14 |
{8{cache_buf_rd_gnt[15]}} & cache_rd_ptr15;
cache_rd_addr <= cache_rd_addr_tmp;
cache_rd_addr <= cache_rd_addr;
cache_rd_data_reg <= 148'b0;
else if (muxed_cache_rd_strobe_r)
cache_rd_data_reg <= cache_rd_data;
cache_rd_data_reg <= cache_rd_data_reg;
wire[7:0] cache_wr_addr_tmp = {8{fetch_desp_resp_valid_array[0]}} & cache_wr_ptr0 |
{8{fetch_desp_resp_valid_array[1]}} & cache_wr_ptr1 |
{8{fetch_desp_resp_valid_array[2]}} & cache_wr_ptr2 |
{8{fetch_desp_resp_valid_array[3]}} & cache_wr_ptr3 |
{8{fetch_desp_resp_valid_array[4]}} & cache_wr_ptr4 |
{8{fetch_desp_resp_valid_array[5]}} & cache_wr_ptr5 |
{8{fetch_desp_resp_valid_array[6]}} & cache_wr_ptr6 |
{8{fetch_desp_resp_valid_array[7]}} & cache_wr_ptr7 |
{8{fetch_desp_resp_valid_array[8]}} & cache_wr_ptr8 |
{8{fetch_desp_resp_valid_array[9]}} & cache_wr_ptr9 |
{8{fetch_desp_resp_valid_array[10]}} & cache_wr_ptr10 |
{8{fetch_desp_resp_valid_array[11]}} & cache_wr_ptr11 |
{8{fetch_desp_resp_valid_array[12]}} & cache_wr_ptr12 |
{8{fetch_desp_resp_valid_array[13]}} & cache_wr_ptr13 |
{8{fetch_desp_resp_valid_array[14]}} & cache_wr_ptr14 |
{8{fetch_desp_resp_valid_array[15]}} & cache_wr_ptr15;
else if (rdmc_resp_data_valid)
cache_wr_addr <= cache_wr_addr_tmp;
cache_wr_addr <= cache_wr_addr;
cache_wr_strobe <= rdmc_resp_data_valid;