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// OpenSPARC T2 Processor File: niu_rdmc_fetch_desp_sm.v
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module niu_rdmc_fetch_desp_sm (
rdmc_resp_accept_sm, //use rdmc_resp_accept if timing
input[4:0] dma_chnl_grp_id;
input[4:0] fetch_desp_num;
input rdmc_resp_rdy_valid;
input[4:0] rdmc_resp_cmd;
input[3:0] rdmc_resp_cmd_status;
input[3:0] rdmc_resp_data_status;
input[4:0] rdmc_resp_dma_num;
input rdmc_resp_data_valid;
input[15:0] rdmc_resp_byteenable;
input rdmc_resp_trans_comp;
input resp_data_in_process;
output rdmc_resp_accept_sm;
output fetch_desp_resp_vld;
output fetch_desp_req_sm;
output fetch_desp_pre_done;
output[3:0] resp_bus_err_type;
reg fetch_desp_resp_valid_sm;
wire[3:0] vaild_bit_array;
wire[3:0] resp_bus_err_type;
wire resp_id_match = (dma_chnl_grp_id == rdmc_resp_dma_num);
wire rdmc_resp_cmd_err = (rdmc_resp_cmd_status == 4'b1111) | !(rdmc_resp_cmd[4:0] == 5'b00101);
DESP_RESP_DATA1 = 3'b011,
DESP_RESP_DATA2 = 3'b101,
desp_init_valid or fetch_desp_trig or
fetch_desp_gnt or rdmc_resp_rdy_valid or
rdmc_resp_comp or rdmc_resp_trans_comp or
resp_data_in_process or resp_id_match or
dma_fatal_err or rdmc_req_err or rdmc_resp_cmd_err)
fetch_desp_req_sm = 1'b0;
rdmc_resp_accept_sm = 1'b0;
fetch_desp_resp_valid_sm= 1'b0;
fetch_desp_pre_done = 1'b0;
case (state) //synopsys parallel_case full_case
if (desp_init_valid & !dma_fatal_err)
fetch_desp_req_sm = 1'b1;
if (resp_data_in_process)
rdmc_resp_accept_sm = 1'b0;
fetch_desp_resp_valid_sm = 1'b0;
rdmc_resp_accept_sm = 1'b0;
fetch_desp_resp_valid_sm = 1'b0;
else if (rdmc_resp_rdy_valid & resp_id_match & rdmc_resp_cmd_err)
rdmc_resp_accept_sm = 1'b1;
fetch_desp_resp_valid_sm = 1'b0;
else if (rdmc_resp_rdy_valid & resp_id_match)
rdmc_resp_accept_sm = 1'b1;
fetch_desp_resp_valid_sm = 1'b1;
next_state = DESP_RESP_DATA1;
if (rdmc_resp_comp & rdmc_resp_trans_comp)
fetch_desp_pre_done = 1'b1;
next_state = DESP_RESP_DONE;
if (resp_data_in_process)
rdmc_resp_accept_sm = 1'b0;
fetch_desp_resp_valid_sm = 1'b0;
else if (rdmc_resp_rdy_valid & resp_id_match & rdmc_resp_cmd_err)
rdmc_resp_accept_sm = 1'b1;
fetch_desp_resp_valid_sm = 1'b0;
else if (rdmc_resp_rdy_valid & resp_id_match)
rdmc_resp_accept_sm = 1'b1;
fetch_desp_resp_valid_sm = 1'b1;
next_state = DESP_RESP_DATA2;
if (rdmc_resp_comp & rdmc_resp_trans_comp)
fetch_desp_pre_done = 1'b1;
next_state = DESP_RESP_DONE;
else if (fetch_desp_req_sm)
fetch_desp_req <= fetch_desp_req;
rdmc_resp_accept <= 1'b0;
rdmc_resp_accept <= rdmc_resp_accept_sm;
fetch_desp_resp_vld <= 1'b0;
fetch_desp_resp_vld <= 1'b0;
else if (fetch_desp_resp_valid_sm)
fetch_desp_resp_vld <= 1'b1;
fetch_desp_resp_vld <= 1'b0;
fetch_desp_resp_vld <= fetch_desp_resp_vld;
assign vaild_bit0 = &rdmc_resp_byteenable[3:0];
assign vaild_bit1 = &rdmc_resp_byteenable[7:4];
assign vaild_bit2 = &rdmc_resp_byteenable[11:8];
assign vaild_bit3 = &rdmc_resp_byteenable[15:12];
assign vaild_bit_array = {vaild_bit3, vaild_bit2, vaild_bit1, vaild_bit0};
assign valid_bit_err0 = |rdmc_resp_byteenable[3:0] & !vaild_bit0;
assign valid_bit_err1 = |rdmc_resp_byteenable[7:4] & !vaild_bit1;
assign valid_bit_err2 = |rdmc_resp_byteenable[11:8] & !vaild_bit2;
assign valid_bit_err3 = |rdmc_resp_byteenable[15:12] & !vaild_bit3;
assign valid_bit_err_tmp = valid_bit_err0 | valid_bit_err1 |
valid_bit_err2 | valid_bit_err3 | valid_bit_err;
assign resp_data_cnt_err = !(resp_data_cnt == fetch_desp_num);
always @ (vaild_bit_array)
case (vaild_bit_array) //synopsys parallel_case full_case
4'b0001, 4'b0010, 4'b0100, 4'b1000:
4'b0011, 4'b0110, 4'b1100:
else if (fetch_desp_resp_vld & rdmc_resp_data_valid)
resp_data_cnt <= resp_data_cnt + {2'b0, valid_addr_cnt};
resp_data_cnt <= resp_data_cnt;
else if (fetch_desp_resp_vld & rdmc_resp_data_valid)
valid_bit_err_r <= valid_bit_err_tmp | valid_bit_err_r;
valid_bit_err_r <= valid_bit_err_r;
else if (fetch_desp_resp_vld & rdmc_resp_data_valid & (rdmc_resp_data_status != 4'b0))
resp_data_err <= resp_data_err;
assign resp_bus_err = (resp_cmd_err | resp_data_cnt_err | valid_bit_err_r | resp_data_err) & fetch_desp_done;
assign resp_bus_err_type = {resp_cmd_err, resp_data_cnt_err, valid_bit_err_r, resp_data_err};