// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: niu_tdmc_mbox_context.v
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// ========== Copyright Header End ============================================
/*********************************************************************
* NIU TDMC - DMA Context for Mailbox Writes
* Orignal Author(s): Arvind Srinivasan
* Copyright (c) 2004 Sun Microsystems, Inc.
* This verilog model is the confidential and proprietary property of
* Sun Microsystems, Inc., and the possession or use of this model
* requires a written license from Sun Microsystems, Inc.
**********************************************************************/
module niu_tdmc_mbox_context(/*AUTOARG*/
send_mbox_dma, mbox_dma_data, mbox_dma_data_valid,
mbox_dma_data_done, clear_cfg_dma_mb, set_cfg_dma_mmk,
SysClk, Reset_L, txc_dmc_dma_mark_bit, tx_cfg_dma_mk,
tx_cfg_dma_mmk, tx_cfg_dma_enable_mb, tx_cs_dma, tx_dma_pre_st,
tx_rng_head_dma, tx_rng_tail_dma, tx_dma_rng_err_logh,
tx_dma_rng_err_logl, mbox_ack_dma_received,
mbox_ack_dma_received_error, done_mbox_dma, mbox_dma_scheduled,
input txc_dmc_dma_mark_bit;
input tx_cfg_dma_enable_mb;
input [63:0] tx_dma_pre_st;
input [`PTR_WIDTH:0] tx_rng_head_dma;
input [`PTR_WIDTH:0] tx_rng_tail_dma;
input [63:0] tx_dma_rng_err_logh;
input [63:0] tx_dma_rng_err_logl;
input mbox_ack_dma_received;
input mbox_ack_dma_received_error;
input mbox_dma_scheduled;
output [127:0] mbox_dma_data;
output mbox_dma_data_valid;
output mbox_dma_data_done;
// if(tx_cfg_dma_enable_mb & txc_dmc_dma_mark_bit & tx_cfg_dma_mk)
// if ( done_mbox_dma) clear_cfg_dma_mk;
// if(mbox_dma_scheduled ) // should happen only when send_mbox_dma is set
// copy the registers into a shadow registers
// if another markbit is seen then set_cfg_dma_mmk = 1;
// if( done_mbox_dma) set_pending_flag-
// clear pending flag once ack is received and clear_cfg_dma_mk = 1;
// if pending flag is set- and another markbit is seen- set mmk bit
// To generate data and data valid and complete signal
// set count = 0 if(mbox_ is scheduled)
// incr count everytime data_req is asserted and mbox is scheduled
// for very request- send data and data valid out
// decrement send counter and once it reached 0 generate complete signals
reg [127:0] mbox_dma_data;
reg [63:0] sh_tx_cfg_dma_cs;
reg [63:0] sh_tx_dma_pre_st;
reg [`PTR_WIDTH:0] sh_tx_ring_dma_hdl;
reg [`PTR_WIDTH:0] sh_tx_ring_dma_kick;
reg [63:0] sh_tx_ring_dma_errlog;
reg mbox_dma_scheduled_d;
// synopsys translate_off
IDLE : SEND_STATE = "IDLE";
SEND_DATA:SEND_STATE = "SEND_DATA";
default : SEND_STATE = "UNKNOWN";
always@(posedge SysClk) begin
mbox_dma_scheduled_d <= 1'b0;
else mbox_dma_scheduled_d <= mbox_dma_scheduled;
end // always@ (posedge SysClk)
always@(posedge SysClk) begin
end else begin // if (!Reset_L)
else if(tx_cfg_dma_enable_mb & txc_dmc_dma_mark_bit & !pending_ack) begin
end // if (tx_cfg_dma_enable_mb & txc_dmc_dma_mark_bit & tx_cfg_dma_mk & !pending_ack)
end // else: !if(!Reset_L)
end // always@ (posedge SysClk)
assign clear_cfg_dma_mb = mbox_ack_dma_received;
always@(posedge SysClk) begin
end else begin // if (!Reset_L)
if(tx_cfg_dma_enable_mb) begin
set_cfg_dma_mk <= clear_cfg_dma_mb;
set_cfg_dma_mk <= txc_dmc_dma_mark_bit;
end // else: !if(tx_cfg_dma_enable_mb)
end // else: !if(!Reset_L)
end // always@ (posedge SysClk)
always@(posedge SysClk) begin
set_cfg_dma_mmk <= ( mmk_seen & tx_cfg_dma_mk ) & ~set_cfg_dma_mmk;
always@(posedge SysClk) begin
mmk_seen <= (tx_cfg_dma_enable_mb & txc_dmc_dma_mark_bit & ( pending_ack | send_mbox_dma ) ) |
( ~tx_cfg_dma_enable_mb & txc_dmc_dma_mark_bit & tx_cfg_dma_mk) |
(mmk_seen & ~tx_cfg_dma_mk);
mmk_seen <= (txc_dmc_dma_mark_bit & tx_cfg_dma_mk) | shadow_mark_bit | (mmk_seen & ~tx_cfg_dma_mk);
shadow_mark_bit <= txc_dmc_dma_mark_bit | ( shadow_mark_bit & ~tx_cfg_dma_mk);
end // else: !if(!Reset_L)
end // always@ (posedge SysClk)
always@(posedge SysClk) begin
end else if(done_mbox_dma) begin // if (!Reset_L)
end else if(mbox_ack_dma_received ) begin // if (done_mbox_dma)
end // if (mbox_ack_dma_received )
end // always@ (posedge SysClk)
always@(posedge SysClk) begin
if(mbox_dma_scheduled & !mbox_dma_scheduled_d) begin
sh_tx_cfg_dma_cs <= tx_cs_dma ;
sh_tx_ring_dma_hdl <= tx_rng_head_dma ;
sh_tx_dma_pre_st <= tx_dma_pre_st ;
sh_tx_ring_dma_kick <= tx_rng_tail_dma;
sh_tx_ring_dma_errlog<= {tx_dma_rng_err_logh[31:0],tx_dma_rng_err_logl[31:0]} ;
end // if (mbox_dma_scheduled & !mbox_dma_scheduled_d)
end // always@ (posedge SysClk)
// State machine to send these data to the Meta Bus-
always@(posedge SysClk) begin
if(!mbox_dma_scheduled) req_count <= 3'h0;
else if(mbox_dma_scheduled & meta_data_req)
req_count<= req_count +1;
always@(posedge SysClk) begin
mbox_dma_data_valid <= 1'b0;
mbox_dma_data_done <= 1'b0;
mbox_dma_data_valid <= 1'b0;
mbox_dma_data_done <= 1'b0;
if(mbox_dma_scheduled & meta_data_req) begin
end // if (mbox_dma_scheduled & arb0_tdmc_data_req)
if(!done & (req_count <= send_count) ) begin
mbox_dma_data <= 128'hfeedbeef_feedbeef_feedbeef_feedbeef;
mbox_dma_data_valid <= 1'b0;
mbox_dma_data <= {sh_tx_cfg_dma_cs,sh_tx_dma_pre_st};
mbox_dma_data_valid <= 1'b1;
mbox_dma_data_done <= 1'b0;
mbox_dma_data <= {45'h0,2'h0,sh_tx_ring_dma_hdl, 45'h0, 2'h0,sh_tx_ring_dma_kick};
mbox_dma_data_valid <= 1'b1;
mbox_dma_data_done <= 1'b0;
mbox_dma_data <= {sh_tx_ring_dma_errlog,64'h0};
mbox_dma_data_valid <= 1'b1;
mbox_dma_data_done <= 1'b0;
mbox_dma_data_valid <= 1'b1;
mbox_dma_data_done <= 1'b1;
mbox_dma_data_valid <= 1'b0;
mbox_dma_data_done <= 1'b0;
endcase // case(send_count)
send_count <= send_count + 3'h1;
mbox_dma_data <= 128'hfeedbeef_feedbeef_feedbeef_feedbeef;
mbox_dma_data_valid <= 1'b0;
endcase // case(send_state)
end // else: !if(!Reset_L)
end // always@ (posedge SysClk)