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// OpenSPARC T2 Processor File: xpcs_rxio_ebuffer_sm.v
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// ****************************************************************
// Sun Proprietary/Confidential: Internal Use Only
// ****************************************************************
// Block: XPCS Lane-to-lane deskew Interface
// Module: xpcs_rxio_ebuffer_sm
// File: xpcs_rxio_ebuffer_sm.v
// Description: This block contains the deskew state machine
// compliant to ieee 802.3ae clause 48 fig 48-8.
// ------------------------------------------------------------
// ------------------------------------------------------------
// ****************************************************************
module xpcs_rxio_ebuffer_sm (
output csr_pulse_deskew_error;
parameter DESKEW_LOSS = 8'h00;
parameter ALIGN_DET1 = 8'h01;
parameter ALIGN_DET2 = 8'h02;
parameter ALIGN_DET3 = 8'h04;
parameter DESKEW_OK = 8'h08;
parameter ALIGN_ERR1 = 8'h10;
parameter ALIGN_ERR2 = 8'h20;
parameter ALIGN_ERR3 = 8'h40;
// ************************************************************************
// Snoop data out of deskew fifo to check if align characters are deskewed
// ************************************************************************
assign read_in_0[9:0] = {r_error_0, r_special_0, r_byte_0[7:0]};
assign read_in_1[9:0] = {r_error_1, r_special_1, r_byte_1[7:0]};
assign read_in_2[9:0] = {r_error_2, r_special_2, r_byte_2[7:0]};
assign read_in_3[9:0] = {r_error_3, r_special_3, r_byte_3[7:0]};
// check for comma symbol on all lanes
assign alg_lane0 = (read_in_0[9:0] == `XPCS_DEC_ALG);
assign alg_lane1 = (read_in_1[9:0] == `XPCS_DEC_ALG);
assign alg_lane2 = (read_in_2[9:0] == `XPCS_DEC_ALG);
assign alg_lane3 = (read_in_3[9:0] == `XPCS_DEC_ALG);
assign alg_present = alg_lane0 | alg_lane1 | alg_lane2 | alg_lane3 ;
assign aligned = alg_lane0 & alg_lane1 & alg_lane2 & alg_lane3;
assign csr_deskew_error = alg_present & !aligned;
assign got_deskew_ok = alg_present & aligned;
// ********************************
// Deskew init and done handshake
// ********************************
always @ (posedge rx_clk)
deskew_done_d <= deskew_done;
deskew_init_d <= deskew_init;
deskewing <= deskew_on_pulse ? 1'b1 : deskew_off_pulse ? 1'b0 : deskewing;
assign deskew_off_pulse = deskew_done & !deskew_done_d;
assign deskew_on_pulse = deskew_init & !deskew_init_d;
// *****************************************
// Deskew state machine Clause 48 fig 48-8
// *****************************************
always @ (posedge rx_clk)
wire csr_link_status_temp;
always @ (posedge rx_clk)
csr_link_status <= csr_link_status_temp;
assign {csr_link_status_temp,
nxt_state} = fn_deskew_sm (reset,
function [10:0] fn_deskew_sm;
n_inc_deskew_error = 1'b0;
n_inc_deskew_error = 1'b0;
case (state) // synopsys parallel_case
n_inc_deskew_error = 1'b0;
fn_deskew_sm = {n_status, n_inc_deskew_error, n_init, n_state};
// 0in bits_on -var state -max 1 -clock rx_clk
// 0in state -var state -val DESKEW_LOSS -next ALIGN_DET1 -clock rx_clk -reset (reset |!sync_status)
// 0in state -var state -val ALIGN_DET1 -next DESKEW_LOSS ALIGN_DET2 -clock rx_clk -reset (reset |!sync_status)
// 0in state -var state -val ALIGN_DET2 -next DESKEW_LOSS ALIGN_DET3 -clock rx_clk -reset (reset |!sync_status)
// 0in state -var state -val ALIGN_DET3 -next DESKEW_LOSS DESKEW_OK -clock rx_clk -reset (reset |!sync_status)
// 0in state -var state -val DESKEW_OK -next ALIGN_ERR1 -clock rx_clk -reset (reset |!sync_status)
// 0in state -var state -val ALIGN_ERR1 -next DESKEW_OK ALIGN_ERR2 -clock rx_clk -reset (reset |!sync_status)
// 0in state -var state -val ALIGN_ERR2 -next ALIGN_ERR3 ALIGN_ERR1 -clock rx_clk -reset (reset |!sync_status)
// 0in state -var state -val ALIGN_ERR3 -next DESKEW_LOSS ALIGN_ERR2 -clock rx_clk -reset (reset |!sync_status)