// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_common_ccc_cdp.v
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// ========== Copyright Header End ============================================
module dmu_common_ccc_cdp
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
input [`FIRE_CSR_ADDR_BITS] csr_host_0_addr;
input [`FIRE_CSR_DATA_BITS] csr_host_0_data;
input [`FIRE_CSR_SRCB_BITS] csr_host_0_src_bus_id;
input [`FIRE_CSR_ADDR_BITS] csr_host_1_addr;
input [`FIRE_CSR_DATA_BITS] csr_host_1_data;
input [`FIRE_CSR_SRCB_BITS] csr_host_1_src_bus_id;
input [`FIRE_CSR_ADDR_BITS] csr_host_2_addr;
input [`FIRE_CSR_DATA_BITS] csr_host_2_data;
input [`FIRE_CSR_SRCB_BITS] csr_host_2_src_bus_id;
input [`FIRE_CSR_ADDR_BITS] csr_host_3_addr;
input [`FIRE_CSR_DATA_BITS] csr_host_3_data;
input [`FIRE_CSR_SRCB_BITS] csr_host_3_src_bus_id;
input [`FIRE_CSR_ADDR_BITS] csr_host_bit_check_mask;
input [`FIRE_CSR_SRCB_BITS] arb2cdp_sel;
input [`FIRE_CSR_DATA_BITS] dep2cdp_data;
input [`FIRE_CSR_STTS_BITS] fsm2cdp_stts;
output [`FIRE_CSR_STTS_BITS] csr_host_0_done_status;
output [`FIRE_CSR_DATA_BITS] csr_host_0_read_data;
output [`FIRE_CSR_STTS_BITS] csr_host_1_done_status;
output [`FIRE_CSR_DATA_BITS] csr_host_1_read_data;
output [`FIRE_CSR_STTS_BITS] csr_host_2_done_status;
output [`FIRE_CSR_DATA_BITS] csr_host_2_read_data;
output [`FIRE_CSR_STTS_BITS] csr_host_3_done_status;
output [`FIRE_CSR_DATA_BITS] csr_host_3_read_data;
output [`FIRE_CSR_ADDR_BITS] cdp2pkt_addr;
output [`FIRE_CSR_DATA_BITS] cdp2pkt_data;
output [`FIRE_CSR_SRCB_BITS] cdp2pkt_src_bus;
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
wire [`FIRE_CSR_STTS_BITS] csr_host_0_done_status;
wire [`FIRE_CSR_DATA_BITS] csr_host_0_read_data;
wire [`FIRE_CSR_STTS_BITS] csr_host_1_done_status;
wire [`FIRE_CSR_DATA_BITS] csr_host_1_read_data;
wire [`FIRE_CSR_STTS_BITS] csr_host_2_done_status;
wire [`FIRE_CSR_DATA_BITS] csr_host_2_read_data;
wire [`FIRE_CSR_STTS_BITS] csr_host_3_done_status;
wire [`FIRE_CSR_DATA_BITS] csr_host_3_read_data;
wire [`FIRE_CSR_ADDR_BITS] cdp2pkt_addr;
wire [`FIRE_CSR_DATA_BITS] cdp2pkt_data;
wire [`FIRE_CSR_SRCB_BITS] cdp2pkt_src_bus;
reg [`FIRE_CSR_ADDR_BITS] addr, nxt_addr;
reg [`FIRE_CSR_DATA_BITS] data, nxt_data;
reg [`FIRE_CSR_SRCB_BITS] srcb, nxt_srcb;
reg [`FIRE_CSR_STTS_BITS] host_stts;
reg [`FIRE_CSR_DATA_BITS] host_data;
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// csr host done status and read data
assign csr_host_0_done_status = host_stts;
assign csr_host_0_read_data = host_data;
assign csr_host_1_done_status = host_stts;
assign csr_host_1_read_data = host_data;
assign csr_host_2_done_status = host_stts;
assign csr_host_2_read_data = host_data;
assign csr_host_3_done_status = host_stts;
assign csr_host_3_read_data = host_data;
// finite state machine error
assign cdp2fsm_error = |(nxt_addr & csr_host_bit_check_mask);
// packetizer address, data, source bus id, and write
assign cdp2pkt_addr = addr;
assign cdp2pkt_data = data;
assign cdp2pkt_src_bus = srcb;
// csr host address select
always @ (arb2cdp_sel or csr_host_0_addr or csr_host_1_addr or
csr_host_2_addr or csr_host_3_addr) begin
case (arb2cdp_sel) // synopsys infer_mux
2'b00 : nxt_addr = csr_host_0_addr;
2'b01 : nxt_addr = csr_host_1_addr;
2'b10 : nxt_addr = csr_host_2_addr;
2'b11 : nxt_addr = csr_host_3_addr;
always @ (arb2cdp_sel or csr_host_0_data or csr_host_1_data or
csr_host_2_data or csr_host_3_data) begin
case (arb2cdp_sel) // synopsys infer_mux
2'b00 : nxt_data = csr_host_0_data;
2'b01 : nxt_data = csr_host_1_data;
2'b10 : nxt_data = csr_host_2_data;
2'b11 : nxt_data = csr_host_3_data;
// csr host source bus id select
always @ (arb2cdp_sel or csr_host_0_src_bus_id or csr_host_1_src_bus_id or
csr_host_2_src_bus_id or csr_host_3_src_bus_id) begin
case (arb2cdp_sel) // synopsys infer_mux
2'b00 : nxt_srcb = csr_host_0_src_bus_id;
2'b01 : nxt_srcb = csr_host_1_src_bus_id;
2'b10 : nxt_srcb = csr_host_2_src_bus_id;
2'b11 : nxt_srcb = csr_host_3_src_bus_id;
always @ (arb2cdp_sel or csr_host_0_wr or csr_host_1_wr or
csr_host_2_wr or csr_host_3_wr) begin
case (arb2cdp_sel) // synopsys infer_mux
2'b00 : nxt_wr = csr_host_0_wr;
2'b01 : nxt_wr = csr_host_1_wr;
2'b10 : nxt_wr = csr_host_2_wr;
2'b11 : nxt_wr = csr_host_3_wr;
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
always @ (posedge clk) begin
always @ (posedge clk) begin
host_data <= dep2cdp_data;
host_stts <= fsm2cdp_stts;
endmodule // dmu_common_ccc_cdp