// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_common_scoreboard_controller.v
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module dmu_common_scoreboard_controller
//////////////////////////////////////////////////////////////////////
//************************* Parameters *************************
//////////////////////////////////////////////////////////////////////
// PARAMETERS PASSED IN ON INDIVIDUAL INSTANTIATIONS
parameter CMD_TYPE_WIDTH = 4;
parameter WR_DATA_WIDTH = 48;
parameter RD_DATA_WIDTH = 48;
// for command type definitions in case statement
parameter IDLE = 4'b0000;
parameter DMA_RD = 4'b0001;
parameter DMA_CLR = 4'b0010;
parameter DMA_RD_CLR = 4'b0011;
parameter DMA_WR = 4'b0100;
parameter DMA_TRN_REQ = 4'b0101;
parameter PIO_RD = 4'b1001;
parameter PIO_CLR = 4'b1010;
parameter PIO_RD_CLR = 4'b1011;
parameter PIO_WR = 4'b1100;
parameter PIO_TRN_REQ = 4'b1101;
//////////////////////////////////////////////////////////////////////
//************************* Port Declarations *******************
//////////////////////////////////////////////////////////////////////
input clk; // input clock
input rst_l; // input reset
// Controller external interface inputs
input req_in; // service request signal
input [CMD_TYPE_WIDTH-1:0] cmd_type_in; // command to be serviced from agent
input [TAG_WIDTH-1:0] trn_in; // transaction number unique ID from agent
input [WR_DATA_WIDTH-1:0] wr_data_in; // write data bus from agent
// Controller external interface outputs
output full_out; // full signals to agent
output [TAG_WIDTH-1:0] n_trn_out; // next trn available for issue to agent
output [RD_DATA_WIDTH-1:0] rd_data_out; // read data bus to agent
output grant_out; // service granted signal to agent
// Controller internal interface inputs
input [RD_DATA_WIDTH-1:0] rd_data_in; // read data bus from scoreboard
output wr1_out; // write enable to scoreboard
output wr2_out; // write enable to scoreboard
output [TAG_WIDTH-1:0] trn1_out; // transaction number unique ID to scoreboard
output type_out; // command to be serviced from agent
output [WR_DATA_WIDTH-1:0] wr_data_out; // write data bus to scoreboard
output req_out; // req out to scoreboard
input full_in; // full signals from ttg
input [TAG_WIDTH-1:0] n_trn_in; // next trn available from ttg
// Controller internal interface outputs
output deq_out; // dequeue signal to ttg to get next trn
output [TAG_WIDTH-1:0] trn2_out; // transaction number unique ID to scoreboard
output enq_out; // enqueue signal to ttg to retire trn
output [7:0] dbg_a; // Controller debug output a
output [7:0] dbg_b; // Controller debug output b
input [2:0] dbg_sel_a; // Controller debug select a
input [2:0] dbg_sel_b; // Controller debug select b
//////////////////////////////////////////////////////////////////////
//*********************** Wires and Regs ************************
//////////////////////////////////////////////////////////////////////
// registers that are flops
reg [TAG_WIDTH-1:0] n_trn_out;
reg [RD_DATA_WIDTH-1:0] rd_data_out;
reg [3:0] state,next_state;
// registers that are not flops
reg [TAG_WIDTH-1:0] trn1_out;
wire [CMD_TYPE_WIDTH-1:0] cmd_type_in;
wire [TAG_WIDTH-1:0] trn_in;
wire [WR_DATA_WIDTH-1:0] wr_data_in;
wire [TAG_WIDTH-1:0] trn2_out;
wire [RD_DATA_WIDTH-1:0] rd_data_in;
wire [WR_DATA_WIDTH-1:0] wr_data_out;
wire [TAG_WIDTH-1:0] n_trn_in;
reg [7:0] nxt_dbg_bus [0:1];
wire [7:0] dbg_a; // Controller debug output a
wire [7:0] dbg_b; // Controller debug output b
wire [2:0] dbg_sel_a; // Controller debug select a
wire [2:0] dbg_sel_b; // Controller debug select b
//////////////////////////////////////////////////////////////////////
// ********************* Combinational Logic ***********************
//////////////////////////////////////////////////////////////////////
always @ (dbg_sel_a or dbg_sel_b)
always @ (dbg_sel[0] or dbg_sel[1] or state or next_state or trn_in or n_trn_in
or trn1_out or n_trn_out or grant_out or full_out or req_in or cmd_type_in
or wr1_out or wr2_out or deq_out or enq_out or scbd_idle)
for (i = 0; i < 2; i = i + 1)
case (dbg_sel[i]) // synopsys parallel_case infer_mux
3'b000: nxt_dbg_bus[i] = {next_state, state};
3'b001: nxt_dbg_bus[i] = {3'b0, trn_in};
3'b010: nxt_dbg_bus[i] = {3'b0, n_trn_in};
3'b011: nxt_dbg_bus[i] = {3'b0, trn1_out};
3'b100: nxt_dbg_bus[i] = {3'b0, n_trn_out};
3'b101: nxt_dbg_bus[i] = {1'b0, grant_out, full_out, req_in, cmd_type_in};
3'b110: nxt_dbg_bus[i] = {4'b0, wr1_out, wr2_out, deq_out, enq_out};
3'b111: nxt_dbg_bus[i] = {7'b0, scbd_idle};
assign dbg_a = dbg_bus[0];
assign dbg_b = dbg_bus[1];
assign wr_data_out = wr_data_in; // pass through the write data
assign trn2_out = trn1_out; // connect up inside module
assign type_out = req_in & cmd_type_in[3]; // pass bit out off controller
assign req_out = req_in; // pass through the req
// Decode the command type
always @(state or req_in or full_in or cmd_type_in or full_out)
next_state = cmd_type_in;
if((cmd_type_in == DMA_TRN_REQ || cmd_type_in == PIO_TRN_REQ) && full_in)
DMA_RD_CLR : // Read w/ Clear (DMA)
DMA_TRN_REQ : // TRN Request w/ Write (DMA)
PIO_RD_CLR : // Read w/ Clear(PIO)
PIO_TRN_REQ : // TRN Request w/ Write(PIO)
default : // 0in < fire -message " Error - controller default state entered "
endcase // case(cmd_type_in)
// assign trn out to next trn on a TRN request
always @ (trn_in or cmd_type_in or n_trn_in)
if (cmd_type_in == DMA_TRN_REQ || cmd_type_in == PIO_TRN_REQ)
//////////////////////////////////////////////////////////////////////
// ********************* Sequential Logic ***********************
//////////////////////////////////////////////////////////////////////
// Give grant for request
// for Read and Read w/ Clear
rd_data_out <= {RD_DATA_WIDTH{1'b0}};
rd_data_out <= rd_data_in;
// for TRN Request w/write
n_trn_out <= {TAG_WIDTH{1'b0}};
// Assert full after last trn request is made
for (i = 0; i < 2; i = i + 1)
for (i = 0; i < 2; i = i + 1)
dbg_bus[i] <= nxt_dbg_bus[i];
end // always @ (posedge clk)
endmodule // dmu_common_scoreboard_controller