design/sys/iop/pcie_common/rtl/pcie_common_srq_qdp.v

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//
// OpenSPARC T2 Processor File: pcie_common_srq_qdp.v
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module pcie_common_srq_qdp (
                            clk,
                            rst_l,
                            ld,
                            ds,
                            di,
                            do );

// ----------------------------------------------------------------------------
// Parameters
// ----------------------------------------------------------------------------
  parameter     QD = 4,                         // queue depth
                QW = 2;                         // queue width

// ----------------------------------------------------------------------------
// Ports
// ----------------------------------------------------------------------------
  input                 clk;                    // clock
  input                 rst_l;                  // reset

  input  [QD-1:0]       ld;                     // load
  input  [QD-2:0]       ds;                     // data select

  input  [QW-1:0]       di;                     // data in
  output [QW-1:0]       do;                     // data out

// ----------------------------------------------------------------------------
// Variables
// ----------------------------------------------------------------------------
  reg  [QW-1:0]         que     [0:QD-1];

  integer               i;

// ----------------------------------------------------------------------------
// Combinational
// ----------------------------------------------------------------------------

  wire [QW-1:0]         do = que[0];

// ----------------------------------------------------------------------------
// Sequential
// ----------------------------------------------------------------------------

  always @ (posedge clk) begin
        if (!rst_l) begin : srq_rst
        integer j;
    for (j = 0; j < QD; j = j + 1) begin
      que[j] <= {QW{1'b0}};
    end
   end
else begin
    for (i = 0; i < QD-1; i = i + 1) begin
      if (ld[i]) que[i] <= ds[i] ? que[i+1] : di;
    end
    if (ld[QD-1]) que[QD-1] <= di;
  end
end

endmodule // pcie_common_srq_qdp