design/sys/iop/rtx/rtl/rtx_n2_efuhdr1a_p1_msff_ctl_macro__width_4.v

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// OpenSPARC T2 Processor File: rtx_n2_efuhdr1a_p1_msff_ctl_macro__width_4.v
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// any PARAMS parms go into naming of macro

module rtx_n2_efuhdr1a_p1_msff_ctl_macro__width_4 (
  din,
  l1clk,
  scan_in,
  siclk,
  soclk,
  dout,
  scan_out);
wire [3:0] fdin;
wire [3:1] sout;

  input [ 3 : 0 ] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [ 3 : 0 ] dout;
  output scan_out;
assign fdin[ 3 : 0 ] = din[ 3 : 0 ];


cl_a1_msff_4x d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 0 ]),
.si(sout[ 1 ]),
.so(scan_out),
.q(dout[ 0 ])
);
cl_a1_msff_4x d0_1 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 1 ]),
.si(sout[ 2 ]),
.so(sout[ 1 ]),
.q(dout[ 1 ])
);
cl_a1_msff_4x d0_2 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 2 ]),
.si(sout[ 3 ]),
.so(sout[ 2 ]),
.q(dout[ 2 ])
);
cl_a1_msff_4x d0_3 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[ 3 ]),
.si(scan_in),
.so(sout[ 3 ]),
.q(dout[ 3 ])
);


endmodule