// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: lsu_sed_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
wire dff_prty_bits_scanin;
wire dff_prty_bits_scanout;
wire dff_rd_data_0_scanin;
wire dff_rd_data_0_scanout;
wire dff_rd_data_1_scanin;
wire dff_rd_data_1_scanout;
wire [63:0] stb_ram_data_corr_;
wire [63:0] stb_diag_rd_data;
input [2:0] sbc_diag_wptr_w3;
input [63:0] stb_ram_rd_data;
input [63:0] sec_corr_bit;
input [13:0] stb_ram_rd_ecc;
input stb_ram_rd_cparity;
input [2:0] stb_ram_rd_ctl;
input [63:0] sbd_st_data_b;
input [44:0] stb_cam_data;
input dcc_stb_data_rd_w3;
input dcc_stb_addr_sel_w3;
input [7:0] bist_cmp_data;
output [63:0] stb_ram_data; // Flopped data
output [63:0] stb_ram_data_corr; // Final formatted data
output [2:0] stb_ram_ctl;
output [13:0] sed_ecc_b; // generated ECC bits
output [63:0] stb_ldxa_asi_data_w;
input tcu_pce_ov; // scan signals
input tcu_se_scancollar_out;
lsu_sed_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0 (
.din ({tcu_se_scancollar_out,tcu_pce_ov,spc_aclk,spc_bclk}),
.dout({se,pce_ov,siclk,soclk})
////////////////////////////////////////////////////////////////////////////////
assign {wdh[31:0],wdl[31:0]} = sbd_st_data_b[63:0];
assign inv[6:0] = sbc_inv_ecc[6:0];
lsu_sed_dp_prty_macro__width_16 pgen1_hi_l (
.din ({inv[0],wdh[30],1'b0 ,wdh[28],1'b0 ,wdh[26],wdh[25],1'b0 ,
wdh[23],1'b0 ,wdh[21],1'b0 ,wdh[19],1'b0 ,wdh[17],1'b0 }),
lsu_sed_dp_prty_macro__width_16 pgen1_hi_r (
.din ({wdh[15],1'b0 ,wdh[13],1'b0 ,wdh[11],wdh[10],1'b0 ,wdh[8],
1'b0 ,wdh[6],1'b0 ,wdh[4],wdh[3],1'b0 ,wdh[1],wdh[0]}),
lsu_sed_dp_xor_macro__ports_2__width_1 pgen1_hi (
lsu_sed_dp_prty_macro__width_16 pgen2_hi_l (
.din ({wdh[31],inv[1],1'b0 ,wdh[28],wdh[27],1'b0 ,wdh[25],wdh[24],
1'b0 ,1'b0 ,wdh[21],wdh[20],1'b0 ,1'b0 ,wdh[17],wdh[16]}),
lsu_sed_dp_prty_macro__width_16 pgen2_hi_r (
.din ({1'b0 ,1'b0 ,wdh[13],wdh[12],1'b0 ,wdh[10],wdh[9],1'b0 ,
1'b0 ,wdh[6],wdh[5],1'b0 ,wdh[3],wdh[2],1'b0 ,wdh[0]}),
lsu_sed_dp_xor_macro__ports_2__width_1 pgen2_hi (
lsu_sed_dp_prty_macro__width_16 pgen4_hi_l (
.din ({wdh[31],wdh[30],wdh[29],inv[2],1'b0 ,1'b0 ,wdh[25],wdh[24],
wdh[23],wdh[22],1'b0 ,1'b0 ,1'b0 ,1'b0 ,wdh[17],wdh[16]}),
lsu_sed_dp_prty_macro__width_16 pgen4_hi_r (
.din ({wdh[15],wdh[14],1'b0 ,1'b0 ,1'b0 ,wdh[10],wdh[9],wdh[8],
wdh[7],1'b0 ,1'b0 ,1'b0 ,wdh[3],wdh[2],wdh[1],1'b0 }),
lsu_sed_dp_xor_macro__ports_2__width_1 pgen4_hi (
lsu_sed_dp_prty_macro__width_8 pgen8_hi_l (
.din ({wdh[25],wdh[24],wdh[23],wdh[22],wdh[21],wdh[20],wdh[19],wdh[18]}),
lsu_sed_dp_prty_macro__width_8 pgen8_hi_r (
.din ({inv[3],wdh[10],wdh[9],wdh[8],wdh[7],wdh[6],wdh[5],wdh[4]}),
lsu_sed_dp_xor_macro__ports_2__width_1 pgen8_hi (
assign p16_hi_l = p8_hi_l; // this one can be shared
lsu_sed_dp_prty_macro__width_8 pgen16_hi_r (
.din ({wdh[17],wdh[16],wdh[15],wdh[14],wdh[13],wdh[12],wdh[11],inv[4]}),
lsu_sed_dp_xor_macro__ports_2__width_1 pgen16_hi (
lsu_sed_dp_prty_macro__width_8 pgen32_hi_l (
.din ({wdh[31],wdh[30],wdh[29],wdh[28],wdh[27],wdh[26],inv[5],1'b0 }),
lsu_sed_dp_buff_macro__width_1 pgen32_hi (
lsu_sed_dp_prty_macro__width_16 pgenf_hi_l (
.din ({inv[6],1'b0 ,wdh[29],1'b0 ,wdh[27],wdh[26],1'b0 ,wdh[24],
wdh[23],1'b0 ,wdh[21],1'b0 ,1'b0 ,wdh[18],wdh[17],1'b0 }),
lsu_sed_dp_prty_macro__width_16 pgenf_hi_r (
.din ({1'b0 ,wdh[14],1'b0 ,wdh[12],wdh[11],wdh[10],1'b0 ,1'b0 ,
wdh[7],1'b0 ,wdh[5],wdh[4],1'b0 ,wdh[2],wdh[1],wdh[0]}),
lsu_sed_dp_xor_macro__ports_2__width_1 pgenf_hi (
lsu_sed_dp_prty_macro__width_16 pgen1_lo_l (
.din ({1'b0 ,wdl[30],1'b0 ,wdl[28],1'b0 ,wdl[26],wdl[25],1'b0 ,
wdl[23],1'b0 ,wdl[21],1'b0 ,wdl[19],1'b0 ,wdl[17],1'b0 }),
lsu_sed_dp_prty_macro__width_16 pgen1_lo_r (
.din ({wdl[15],1'b0 ,wdl[13],1'b0 ,wdl[11],wdl[10],1'b0 ,wdl[8],
1'b0 ,wdl[6],1'b0 ,wdl[4],wdl[3],1'b0 ,wdl[1],wdl[0]}),
lsu_sed_dp_xor_macro__ports_2__width_1 pgen1_lo (
lsu_sed_dp_prty_macro__width_16 pgen2_lo_l (
.din ({wdl[31],1'b0 ,1'b0 ,wdl[28],wdl[27],1'b0 ,wdl[25],wdl[24],
1'b0 ,1'b0 ,wdl[21],wdl[20],1'b0 ,1'b0 ,wdl[17],wdl[16]}),
lsu_sed_dp_prty_macro__width_16 pgen2_lo_r (
.din ({1'b0 ,1'b0 ,wdl[13],wdl[12],1'b0 ,wdl[10],wdl[9],1'b0 ,
1'b0 ,wdl[6],wdl[5],1'b0 ,wdl[3],wdl[2],1'b0 ,wdl[0]}),
lsu_sed_dp_xor_macro__ports_2__width_1 pgen2_lo (
lsu_sed_dp_prty_macro__width_16 pgen4_lo_l (
.din ({wdl[31],wdl[30],wdl[29],1'b0 ,1'b0 ,1'b0 ,wdl[25],wdl[24],
wdl[23],wdl[22],1'b0 ,1'b0 ,1'b0 ,1'b0 ,wdl[17],wdl[16]}),
lsu_sed_dp_prty_macro__width_16 pgen4_lo_r (
.din ({wdl[15],wdl[14],1'b0 ,1'b0 ,1'b0 ,wdl[10],wdl[9],wdl[8],
wdl[7],1'b0 ,1'b0 ,1'b0 ,wdl[3],wdl[2],wdl[1],1'b0 }),
lsu_sed_dp_xor_macro__ports_2__width_1 pgen4_lo (
lsu_sed_dp_prty_macro__width_8 pgen8_lo_l (
.din ({wdl[25],wdl[24],wdl[23],wdl[22],wdl[21],wdl[20],wdl[19],wdl[18]}),
lsu_sed_dp_prty_macro__width_8 pgen8_lo_r (
.din ({1'b0 ,wdl[10],wdl[9],wdl[8],wdl[7],wdl[6],wdl[5],wdl[4]}),
lsu_sed_dp_xor_macro__ports_2__width_1 pgen8_lo (
assign p16_lo_l = p8_lo_l; // this one can be shared
lsu_sed_dp_prty_macro__width_8 pgen16_lo_r (
.din ({wdl[17],wdl[16],wdl[15],wdl[14],wdl[13],wdl[12],wdl[11],1'b0 }),
lsu_sed_dp_xor_macro__ports_2__width_1 pgen16_lo (
lsu_sed_dp_prty_macro__width_8 pgen32_lo_l (
.din ({wdl[31],wdl[30],wdl[29],wdl[28],wdl[27],wdl[26],1'b0 ,1'b0 }),
lsu_sed_dp_buff_macro__width_1 pgen32_lo (
lsu_sed_dp_prty_macro__width_16 pgenf_lo_l (
.din ({1'b0 ,1'b0 ,wdl[29],1'b0 ,wdl[27],wdl[26],1'b0 ,wdl[24],
wdl[23],1'b0 ,wdl[21],1'b0 ,1'b0 ,wdl[18],wdl[17],1'b0 }),
lsu_sed_dp_prty_macro__width_16 pgenf_lo_r (
.din ({1'b0 ,wdl[14],1'b0 ,wdl[12],wdl[11],wdl[10],1'b0 ,1'b0 ,
wdl[7],1'b0 ,wdl[5],wdl[4],1'b0 ,wdl[2],wdl[1],wdl[0]}),
lsu_sed_dp_xor_macro__ports_2__width_1 pgenf_lo (
lsu_sed_dp_inv_macro__width_2 mbi_run_buf (
.din ({mbi_run, mbi_run_}),
.dout ({mbi_run_,mbi_run_local})
lsu_sed_dp_mux_macro__buffsel_none__dmux_4x__mux_aonpe__ports_2__width_14 bist_ecc_mx (
.din0 ({mbi_wdata[5:0],mbi_wdata[7:0]}),
.din1 ({pf_hi,p32_hi,p16_hi,p8_hi,p4_hi,p2_hi,p1_hi,
pf_lo,p32_lo,p16_lo,p8_lo,p4_lo,p2_lo,p1_lo}),
////////////////////////////////////////////////////////////////////////////////
assign {rdh[31:0],rdl[31:0]} = stb_ram_rd_data[63:0];
assign ecc[13:0] = stb_ram_rd_ecc[13:0];
lsu_sed_dp_prty_macro__width_16 pchk1_hi_l (
.din ({1'b0 ,rdh[30],1'b0 ,rdh[28],1'b0 ,rdh[26],rdh[25],1'b0 ,
rdh[23],1'b0 ,rdh[21],1'b0 ,rdh[19],1'b0 ,rdh[17],ecc[7]}),
lsu_sed_dp_prty_macro__width_16 pchk1_hi_r (
.din ({rdh[15],1'b0 ,rdh[13],1'b0 ,rdh[11],rdh[10],1'b0 ,rdh[8],
1'b0 ,rdh[6],1'b0 ,rdh[4],rdh[3],1'b0 ,rdh[1],rdh[0]}),
lsu_sed_dp_prty_macro__width_16 pchk2_hi_l (
.din ({rdh[31],1'b0 ,1'b0 ,rdh[28],rdh[27],1'b0 ,rdh[25],rdh[24],
1'b0 ,1'b0 ,rdh[21],rdh[20],1'b0 ,1'b0 ,rdh[17],rdh[16]}),
lsu_sed_dp_prty_macro__width_16 pchk2_hi_r (
.din ({ecc[8],1'b0 ,rdh[13],rdh[12],1'b0 ,rdh[10],rdh[9],1'b0 ,
1'b0 ,rdh[6],rdh[5],1'b0 ,rdh[3],rdh[2],1'b0 ,rdh[0]}),
lsu_sed_dp_prty_macro__width_16 pchk4_hi_l (
.din ({rdh[31],rdh[30],rdh[29],1'b0 ,1'b0 ,1'b0 ,rdh[25],rdh[24],
rdh[23],rdh[22],1'b0 ,1'b0 ,1'b0 ,1'b0 ,rdh[17],rdh[16]}),
lsu_sed_dp_prty_macro__width_16 pchk4_hi_r (
.din ({rdh[15],rdh[14],ecc[9],1'b0 ,1'b0 ,rdh[10],rdh[9],rdh[8],
rdh[7],1'b0 ,1'b0 ,1'b0 ,rdh[3],rdh[2],rdh[1],1'b0 }),
lsu_sed_dp_prty_macro__width_8 pchk8_hi_l (
.din ({rdh[25],rdh[24],rdh[23],rdh[22],rdh[21],rdh[20],rdh[19],rdh[18]}),
lsu_sed_dp_prty_macro__width_8 pchk8_hi_r (
.din ({ecc[10],rdh[10],rdh[9],rdh[8],rdh[7],rdh[6],rdh[5],rdh[4]}),
lsu_sed_dp_prty_macro__width_8 pchk16_hi_r (
.din ({rdh[17],rdh[16],rdh[15],rdh[14],rdh[13],rdh[12],rdh[11],ecc[11]}),
lsu_sed_dp_prty_macro__width_8 pchk32_hi_l (
.din ({rdh[31],rdh[30],rdh[29],rdh[28],rdh[27],rdh[26],1'b0 ,ecc[12]}),
lsu_sed_dp_prty_macro__width_16 pchkf_hi_l (
.din ({rdh[31],rdh[30],rdh[29],rdh[28],rdh[27],rdh[26],rdh[25],rdh[24],
rdh[23],rdh[22],rdh[21],rdh[20],rdh[19],rdh[18],rdh[17],rdh[16]}),
lsu_sed_dp_prty_macro__width_16 pchkf_hi_r (
.din ({rdh[15],rdh[14],rdh[13],rdh[12],rdh[11],rdh[10],rdh[9],rdh[8],
rdh[7],rdh[6],rdh[5],rdh[4],rdh[3],rdh[2],rdh[1],rdh[0]}),
lsu_sed_dp_prty_macro__width_8 pchkf_hi_c (
.din ({ecc[13],ecc[12],ecc[11],ecc[10],ecc[9],ecc[8],ecc[7],1'b0}),
lsu_sed_dp_prty_macro__width_16 pchk1_lo_l (
.din ({1'b0 ,rdl[30],1'b0 ,rdl[28],1'b0 ,rdl[26],rdl[25],1'b0 ,
rdl[23],1'b0 ,rdl[21],1'b0 ,rdl[19],1'b0 ,rdl[17],1'b0}),
lsu_sed_dp_prty_macro__width_16 pchk1_lo_r (
.din ({rdl[15],ecc[0],rdl[13],1'b0 ,rdl[11],rdl[10],1'b0 ,rdl[8],
1'b0 ,rdl[6],1'b0 ,rdl[4],rdl[3],1'b0 ,rdl[1],rdl[0]}),
lsu_sed_dp_prty_macro__width_16 pchk2_lo_l (
.din ({rdl[31],1'b0 ,1'b0 ,rdl[28],rdl[27],1'b0 ,rdl[25],rdl[24],
1'b0 ,1'b0 ,rdl[21],rdl[20],1'b0 ,1'b0,rdl[17],rdl[16]}),
lsu_sed_dp_prty_macro__width_16 pchk2_lo_r (
.din ({ecc[1],1'b0 ,rdl[13],rdl[12],1'b0 ,rdl[10],rdl[9],1'b0 ,
1'b0 ,rdl[6],rdl[5],1'b0 ,rdl[3],rdl[2],1'b0 ,rdl[0]}),
lsu_sed_dp_prty_macro__width_16 pchk4_lo_l (
.din ({rdl[31],rdl[30],rdl[29],1'b0 ,1'b0 ,1'b0 ,rdl[25],rdl[24],
rdl[23],rdl[22],1'b0 ,1'b0 ,1'b0 ,1'b0,rdl[17],rdl[16]}),
lsu_sed_dp_prty_macro__width_16 pchk4_lo_r (
.din ({rdl[15],rdl[14],ecc[2],1'b0 ,1'b0 ,rdl[10],rdl[9],rdl[8],
rdl[7],1'b0 ,1'b0 ,1'b0 ,rdl[3],rdl[2],rdl[1],1'b0 }),
lsu_sed_dp_prty_macro__width_8 pchk8_lo_l (
.din ({rdl[25],rdl[24],rdl[23],rdl[22],rdl[21],rdl[20],rdl[19],rdl[18]}),
lsu_sed_dp_prty_macro__width_8 pchk8_lo_r (
.din ({ecc[3],rdl[10],rdl[9],rdl[8],rdl[7],rdl[6],rdl[5],rdl[4]}),
lsu_sed_dp_prty_macro__width_8 pchk16_lo_r (
.din ({ecc[4],rdl[17],rdl[16],rdl[15],rdl[14],rdl[13],rdl[12],rdl[11]}),
lsu_sed_dp_prty_macro__width_8 pchk32_lo_l (
.din ({rdl[31],rdl[30],rdl[29],rdl[28],rdl[27],rdl[26],1'b0 ,ecc[5]}),
lsu_sed_dp_prty_macro__width_16 pchkf_lo_l (
.din ({rdl[31],rdl[30],rdl[29],rdl[28],rdl[27],rdl[26],rdl[25],rdl[24],
rdl[23],rdl[22],rdl[21],rdl[20],rdl[19],rdl[18],rdl[17],rdl[16]}),
lsu_sed_dp_prty_macro__width_16 pchkf_lo_r (
.din ({rdl[15],rdl[14],rdl[13],rdl[12],rdl[11],rdl[10],rdl[9],rdl[8],
rdl[7],rdl[6],rdl[5],rdl[4],rdl[3],rdl[2],rdl[1],rdl[0]}),
lsu_sed_dp_prty_macro__width_8 pchkf_lo_c (
.din ({ecc[6],ecc[5],ecc[4],ecc[3],ecc[2],ecc[1],ecc[0],1'b0}),
lsu_sed_dp_msff_macro__stack_42l__width_26 dff_prty_bits (
.scan_in(dff_prty_bits_scanin),
.scan_out(dff_prty_bits_scanout),
.din ({c32_hi_l,c32_lo_l,c1_hi_l,c1_lo_l,c2_hi_l,c2_lo_l,c4_hi_l,c4_lo_l,
cf_hi_l,cf_lo_l,c8_hi_l,c8_lo_l,
c16_hi_r,c16_lo_r,c1_hi_r,c1_lo_r,c2_hi_r,c2_lo_r,c4_hi_r,c4_lo_r,
c8_hi_r,c8_lo_r,cf_hi_r,cf_lo_r
.dout ({sed_c32_hi,sed_c32_lo,sed_c1_hi[1],sed_c1_lo[1],sed_c2_hi[1],sed_c2_lo[1],sed_c4_hi[1],sed_c4_lo[1],
sed_cf_hi[1],sed_cf_lo[1],sed_c8_hi[1],sed_c8_lo[1],
sed_cf_hi[2],sed_cf_lo[2],
sed_c16_hi[0],sed_c16_lo[0],sed_c1_hi[0],sed_c1_lo[0],sed_c2_hi[0],sed_c2_lo[0],sed_c4_hi[0],sed_c4_lo[0],
sed_c8_hi[0],sed_c8_lo[0],sed_cf_hi[0],sed_cf_lo[0]
assign sed_c16_hi[1] = sed_c8_hi[1];
assign sed_c16_lo[1] = sed_c8_lo[1];
////////////////////////////////////////////////////////////////////////////////
// stb_ram output flops and correction xors
lsu_sed_dp_msff_macro__minbuff_1__stack_42l__width_42 dff_rd_data_0 (
.scan_in(dff_rd_data_0_scanin),
.scan_out(dff_rd_data_0_scanout),
.din ({stb_ram_rd_cparity,stb_ram_rd_ctl[2],stb_ram_rd_data[63:48],stb_ram_rd_ecc[13:7],1'b0, stb_ram_rd_data[47:32]}),
.dout ({stb_ram_cparity, stb_ram_ctl[2], stb_ram_data[63:48], stb_ram_ecc[13:7], unused[0],stb_ram_data[47:32]}),
lsu_sed_dp_msff_macro__minbuff_1__stack_42l__width_42 dff_rd_data_1 (
.scan_in(dff_rd_data_1_scanin),
.scan_out(dff_rd_data_1_scanout),
.din ({stb_ram_rd_ctl[1:0],stb_ram_rd_data[31:16],stb_ram_rd_ecc[6:0],1'b0, stb_ram_rd_data[15:0]}),
.dout ({stb_ram_ctl[1:0], stb_ram_data[31:16], stb_ram_ecc[6:0], unused[1],stb_ram_data[15:0]}),
lsu_sed_dp_xnor_macro__stack_32c__width_32 ecc_xnor_0 (
.din0 (stb_ram_data[63:32]),
.din1 (sec_corr_bit[63:32]),
.dout (stb_ram_data_corr_[63:32])
lsu_sed_dp_inv_macro__stack_32c__width_32 ecc_inv_0 (
.din (stb_ram_data_corr_[63:32]),
.dout (stb_ram_data_corr[63:32])
lsu_sed_dp_xnor_macro__stack_32c__width_32 ecc_xnor_1 (
.din0 (stb_ram_data[31:0]),
.din1 (sec_corr_bit[31:0]),
.dout (stb_ram_data_corr_[31:0])
lsu_sed_dp_inv_macro__stack_32c__width_32 ecc_inv_1 (
.din (stb_ram_data_corr_[31:0]),
.dout (stb_ram_data_corr[31:0])
////////////////////////////////////////////////////////////////////////////////
// STB diagnostic read and bist muxing
lsu_sed_dp_and_macro__ports_2__stack_32c__width_32 def_value_mx (
.din0 ({4{bist_cmp_data[7:0]}}),
lsu_sed_dp_mux_macro__mux_aope__ports_3__stack_32c__width_32 stb_diag_mux1_0 (
.din0 (stb_ram_data[63:32]),
.din1 ({def_value[31:16],stb_cam_data[7:0],stb_cam_data[44:37]}),
.sel0 (dcc_stb_data_rd_w3),
.sel1 (dcc_stb_addr_sel_w3),
.dout (stb_diag_rd_data[63:32])
lsu_sed_dp_mux_macro__mux_aonpe__ports_5__stack_32c__width_32 stb_diag_mux1_1 (
.din0 (stb_ram_data[31:0]),
.din1 ({def_value[31:14],stb_ram_ecc[13:0]}),
.din2 ({def_value[31:4],stb_ram_cparity,stb_ram_ctl[2:0]}),
.din3 ({stb_cam_data[36:8],def_value[2:0]}),
.din4 ({def_value[31:3],sbc_diag_wptr_w3[2:0]}),
.sel0 (dcc_stb_data_rd_w3),
.sel1 (dcc_stb_ecc_rd_w3),
.sel2 (dcc_stb_ctl_rd_w3),
.sel3 (dcc_stb_addr_sel_w3),
.sel4 (dcc_stb_ptr_rd_w3),
.dout (stb_diag_rd_data[31:0])
lsu_sed_dp_cmp_macro__width_16 bist_cmp_0 (
.din0 ({2{bist_cmp_data[7:0]}}),
.din1 (stb_diag_rd_data[63:48]),
lsu_sed_dp_cmp_macro__width_16 bist_cmp_1 (
.din0 ({2{bist_cmp_data[7:0]}}),
.din1 (stb_diag_rd_data[47:32]),
lsu_sed_dp_cmp_macro__width_16 bist_cmp_2 (
.din0 ({2{bist_cmp_data[7:0]}}),
.din1 (stb_diag_rd_data[31:16]),
lsu_sed_dp_cmp_macro__width_16 bist_cmp_3 (
.din0 ({2{bist_cmp_data[7:0]}}),
.din1 (stb_diag_rd_data[15:0]),
lsu_sed_dp_buff_macro__stack_32c__width_32 ldxa_asi_data_buf_0 (
.din (stb_diag_rd_data[63:32]),
.dout (stb_ldxa_asi_data_w[63:32])
lsu_sed_dp_buff_macro__stack_32c__width_32 ldxa_asi_data_buf_1 (
.din (stb_diag_rd_data[31:0]),
.dout (stb_ldxa_asi_data_w[31:0])
assign dff_prty_bits_scanin = scan_in ;
assign dff_rd_data_0_scanin = dff_prty_bits_scanout ;
assign dff_rd_data_1_scanin = dff_rd_data_0_scanout ;
assign scan_out = dff_rd_data_1_scanout ;
module lsu_sed_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
// parity macro (even parity)
module lsu_sed_dp_prty_macro__width_16 (
// xor macro for ports = 2,3
module lsu_sed_dp_xor_macro__ports_2__width_1 (
// parity macro (even parity)
module lsu_sed_dp_prty_macro__width_8 (
module lsu_sed_dp_buff_macro__width_1 (
module lsu_sed_dp_inv_macro__width_2 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_sed_dp_mux_macro__buffsel_none__dmux_4x__mux_aonpe__ports_2__width_14 (
// any PARAMS parms go into naming of macro
module lsu_sed_dp_msff_macro__stack_42l__width_26 (
.so({so[24:0],scan_out}),
// any PARAMS parms go into naming of macro
module lsu_sed_dp_msff_macro__minbuff_1__stack_42l__width_42 (
.so({so[40:0],scan_out}),
// xnor macro for ports = 2,3
module lsu_sed_dp_xnor_macro__stack_32c__width_32 (
module lsu_sed_dp_inv_macro__stack_32c__width_32 (
// and macro for ports = 2,3,4
module lsu_sed_dp_and_macro__ports_2__stack_32c__width_32 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_sed_dp_mux_macro__mux_aope__ports_3__stack_32c__width_32 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_sed_dp_mux_macro__mux_aonpe__ports_5__stack_32c__width_32 (
cl_dp1_muxbuff5_8x c0_0 (
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module lsu_sed_dp_cmp_macro__width_16 (
module lsu_sed_dp_buff_macro__stack_32c__width_32 (