design/sys/iop/spc/synopsys/script/user_cfg.scr

# ========== Copyright Header Begin ==========================================
#
# OpenSPARC T2 Processor File: user_cfg.scr
# Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
# 4150 Network Circle, Santa Clara, California 95054, U.S.A.
#
# * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
#
# For the avoidance of doubt, and except that if any non-GPL license
# choice is available it will apply instead, Sun elects to use only
# the General Public License version 2 (GPLv2) at this time for any
# software where a choice of GPL license versions is made
# available with the language indicating that GPLv2 or any later version
# may be used, or where a choice of which version of the GPL is applied is
# otherwise unspecified.
#
# Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
# CA 95054 USA or visit www.sun.com if you need additional information or
# have any questions.
#
# ========== Copyright Header End ============================================
source -echo -verbose $dv_root/design/sys/synopsys/script/project_sparc_cfg.scr

set rtl_files {\
libs/cl/cl_rtl_ext.v
libs/cl/cl_a1/cl_a1.behV
libs/cl/cl_u1/cl_u1.behV
libs/cl/cl_dp1/cl_dp1.behV
libs/cl/cl_sc1/cl_sc1.behV
libs/cl/cl_u1lvt/cl_u1lvt.behV
libs/cl/cl_mc1/cl_mc1.v

libs/rtl/n2_efuhdr1_ctl.v

libs/n2sram/mp/n2_irf_mp_128x72_cust_l/n2_irf_mp_128x72_cust/rtl/n2_irf_mp_128x72_cust.v

libs/n2sram/mp/n2_frf_mp_256x78_cust_l/n2_frf_mp_256x78_cust/rtl/n2_frf_mp_256x78_cust.v

libs/tisram/core/n2_icd_sp_16p5kb_cust_l/n2_icd_sp_16p5kb_cust/rtl/n2_icd_sp_16p5kb_cust.v
libs/tisram/core/n2_ict_sp_1920b_cust_l/n2_ict_sp_1920b_cust/rtl/n2_ict_sp_1920b_cust.v
libs/n2sram/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl/n2_tlb_tl_64x59_cust.v

libs/n2sram/dp/n2_dva_dp_32x32_cust_l/n2_dva_dp_32x32_cust/rtl/n2_dva_dp_32x32_cust.v
libs/tisram/core/n2_dca_sp_9kb_cust_l/n2_dca_sp_9kb_cust/rtl/n2_dca_sp_9kb_cust.v
libs/n2sram/cams/n2_stb_cm_64x45_cust_l/n2_stb_cm_64x45_cust/rtl/n2_stb_cm_64x45_cust.v
libs/n2sram/compiler/physical/n2_com_dp_64x84_cust_l/n2_com_dp_64x84_cust/rtl/n2_com_dp_64x84_cust.v
libs/n2sram/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl/n2_tlb_tl_128x59_cust.v
libs/tisram/core/n2_dta_sp_1920b_cust_l/n2_dta_sp_1920b_cust/rtl/n2_dta_sp_1920b_cust.v

libs/n2sram/compiler/physical/n2_com_dp_32x84_cust_l/n2_com_dp_32x84_cust/rtl/n2_com_dp_32x84_cust.v

libs/n2sram/compiler/physical/n2_com_dp_32x152_cust_l/n2_com_dp_32x152_cust/rtl/n2_com_dp_32x152_cust.v
libs/n2sram/compiler/physical/n2_com_dp_32x72_cust_l/n2_com_dp_32x72_cust/rtl/n2_com_dp_32x72_cust.v

design/sys/iop/spc/rtl/spc.v
design/sys/iop/spc/rtl/dmo_dp.v
design/sys/iop/spc/rtl/spc_lb_ctl.v
design/sys/iop/spc/rtl/spc_mb0_ctl.v
design/sys/iop/spc/rtl/spc_mb1_ctl.v
design/sys/iop/spc/rtl/spc_mb2_ctl.v
design/sys/iop/spc/rtl/spc_msf0_dp.v
design/sys/iop/spc/rtl/spc_msf1_dp.v
design/sys/iop/spc/rtl/spc_rep1_dp.v
libs/clk/rtl/clkgen_spc_cmp.v
libs/clk/n2_clk_clstr_hdr_cust_l/n2_clk_clstr_hdr_cust/rtl/n2_clk_clstr_hdr_cust.v
libs/clk/n2_clk_pgrid_cust_l/n2_clk_spc_cmp_cust/rtl/n2_clk_spc_cmp_cust.v

design/sys/iop/spc/dec/rtl/dec.v
design/sys/iop/spc/dec/rtl/dec_dcd_ctl.v
design/sys/iop/spc/dec/rtl/dec_ded_ctl.v
design/sys/iop/spc/dec/rtl/dec_del_ctl.v
design/sys/iop/spc/exu/rtl/exu.v
design/sys/iop/spc/exu/rtl/exu_ecc_ctl.v
design/sys/iop/spc/exu/rtl/exu_ect_ctl.v
design/sys/iop/spc/exu/rtl/exu_edp_dp.v
design/sys/iop/spc/exu/rtl/exu_mdp_dp.v
design/sys/iop/spc/exu/rtl/exu_rml_ctl.v
design/sys/iop/spc/fgu/rtl/fgu.v
design/sys/iop/spc/fgu/rtl/fgu_fac_ctl.v
design/sys/iop/spc/fgu/rtl/fgu_fad_dp.v
design/sys/iop/spc/fgu/rtl/fgu_fdc_ctl.v
design/sys/iop/spc/fgu/rtl/fgu_fdd_dp.v
design/sys/iop/spc/fgu/rtl/fgu_fec_ctl.v
design/sys/iop/spc/fgu/rtl/fgu_fgd_dp.v
design/sys/iop/spc/fgu/rtl/fgu_fic_ctl.v
design/sys/iop/spc/fgu/rtl/fgu_fpc_ctl.v
design/sys/iop/spc/fgu/rtl/fgu_fpe_dp.v
design/sys/iop/spc/fgu/rtl/fgu_fpf_dp.v
design/sys/iop/spc/fgu/rtl/fgu_fpy_dp.v
design/sys/iop/spc/fgu/rtl/fgu_rep_dp.v
design/sys/iop/spc/gkt/rtl/gkt.v
design/sys/iop/spc/gkt/rtl/gkt_ipc_ctl.v
design/sys/iop/spc/gkt/rtl/gkt_ipd_dp.v
design/sys/iop/spc/gkt/rtl/gkt_leg_ctl.v
design/sys/iop/spc/gkt/rtl/gkt_pqm_ctl.v
design/sys/iop/spc/ifu/rtl/ifu_cmu.v
design/sys/iop/spc/ifu/rtl/ifu_cmu_cmt_ctl.v
design/sys/iop/spc/ifu/rtl/ifu_cmu_csm_ctl.v
design/sys/iop/spc/ifu/rtl/ifu_cmu_lsi_ctl.v
design/sys/iop/spc/ifu/rtl/ifu_cmu_lsi_dp.v
design/sys/iop/spc/ifu/rtl/ifu_cmu_msb_ctl.v
design/sys/iop/spc/ifu/rtl/ifu_cmu_msb_dp.v
design/sys/iop/spc/ifu/rtl/ifu_ftu.v
design/sys/iop/spc/ifu/rtl/ifu_ftu_agc_ctl.v
design/sys/iop/spc/ifu/rtl/ifu_ftu_agd_dp.v
design/sys/iop/spc/ifu/rtl/ifu_ftu_asi_ctl.v
design/sys/iop/spc/ifu/rtl/ifu_ftu_byp_dp.v
design/sys/iop/spc/ifu/rtl/ifu_ftu_cms_ctl.v
design/sys/iop/spc/ifu/rtl/ifu_ftu_ctx_dp.v
design/sys/iop/spc/ifu/rtl/ifu_ftu_err_dp.v
design/sys/iop/spc/ifu/rtl/ifu_ftu_ftp_ctl.v
design/sys/iop/spc/ifu/rtl/ifu_ftu_itc_ctl.v
design/sys/iop/spc/ifu/rtl/ifu_ftu_itd_dp.v
design/sys/iop/spc/ifu/rtl/ifu_ftu_red_ctl.v
design/sys/iop/spc/ifu/rtl/ifu_ftu_tfc_ctl.v
design/sys/iop/spc/ifu/rtl/ifu_ftu_tsm_ctl.v
design/sys/iop/spc/ifu/rtl/ifu_ibu.v
design/sys/iop/spc/ifu/rtl/ifu_ibu_ibf_dp.v
design/sys/iop/spc/ifu/rtl/ifu_ibu_ibq_ctl.v
design/sys/iop/spc/lsu/rtl/lsu.v
design/sys/iop/spc/lsu/rtl/lsu_adc_ctl.v
design/sys/iop/spc/lsu/rtl/lsu_arc_ctl.v
design/sys/iop/spc/lsu/rtl/lsu_ard_dp.v
design/sys/iop/spc/lsu/rtl/lsu_asc_ctl.v
design/sys/iop/spc/lsu/rtl/lsu_asd_dp.v
design/sys/iop/spc/lsu/rtl/lsu_cic_ctl.v
design/sys/iop/spc/lsu/rtl/lsu_cid_dp.v
design/sys/iop/spc/lsu/rtl/lsu_dac_ctl.v
design/sys/iop/spc/lsu/rtl/lsu_dcc_ctl.v
design/sys/iop/spc/lsu/rtl/lsu_dcd_dp.v
design/sys/iop/spc/lsu/rtl/lsu_dcp_dp.v
design/sys/iop/spc/lsu/rtl/lsu_dcs_dp.v
design/sys/iop/spc/lsu/rtl/lsu_lmc_ctl.v
design/sys/iop/spc/lsu/rtl/lsu_lmd_dp.v
design/sys/iop/spc/lsu/rtl/lsu_lru8_ctl.v
design/sys/iop/spc/lsu/rtl/lsu_pic_ctl.v
design/sys/iop/spc/lsu/rtl/lsu_pid_dp.v
design/sys/iop/spc/lsu/rtl/lsu_red_ctl.v
design/sys/iop/spc/lsu/rtl/lsu_rep_dp.v
design/sys/iop/spc/lsu/rtl/lsu_sbc_ctl.v
design/sys/iop/spc/lsu/rtl/lsu_sbd_dp.v
design/sys/iop/spc/lsu/rtl/lsu_sbs_ctl.v
design/sys/iop/spc/lsu/rtl/lsu_sec_ctl.v
design/sys/iop/spc/lsu/rtl/lsu_sed_dp.v
design/sys/iop/spc/lsu/rtl/lsu_spd_dp.v
design/sys/iop/spc/lsu/rtl/lsu_tgc_ctl.v
design/sys/iop/spc/lsu/rtl/lsu_tgd_dp.v
design/sys/iop/spc/lsu/rtl/lsu_tlc_ctl.v
design/sys/iop/spc/lsu/rtl/lsu_tld_dp.v
design/sys/iop/spc/mmu/rtl/mmu.v
design/sys/iop/spc/mmu/rtl/mmu_asd_dp.v
design/sys/iop/spc/mmu/rtl/mmu_ase_dp.v
design/sys/iop/spc/mmu/rtl/mmu_asi_ctl.v
design/sys/iop/spc/mmu/rtl/mmu_eem_dp.v
design/sys/iop/spc/mmu/rtl/mmu_htc_ctl.v
design/sys/iop/spc/mmu/rtl/mmu_htd_dp.v
design/sys/iop/spc/mmu/rtl/mmu_mbd_dp.v
design/sys/iop/spc/mmu/rtl/mmu_mec_dp.v
design/sys/iop/spc/mmu/rtl/mmu_mel_dp.v
design/sys/iop/spc/mmu/rtl/mmu_mem_dp.v
design/sys/iop/spc/mmu/rtl/mmu_sed_dp.v
design/sys/iop/spc/mmu/rtl/mmu_seg_dp.v
design/sys/iop/spc/mmu/rtl/mmu_sel_dp.v
design/sys/iop/spc/mmu/rtl/mmu_tmc_ctl.v
design/sys/iop/spc/mmu/rtl/mmu_trc_ctl.v
design/sys/iop/spc/mmu/rtl/mmu_trs_ctl.v
design/sys/iop/spc/mmu/rtl/mmu_tsm_ctl.v
design/sys/iop/spc/pku/rtl/pku.v
design/sys/iop/spc/pku/rtl/pku_pck_ctl.v
design/sys/iop/spc/pku/rtl/pku_pkd_dp.v
design/sys/iop/spc/pku/rtl/pku_swl_ctl.v
design/sys/iop/spc/pmu/rtl/pmu.v
design/sys/iop/spc/pmu/rtl/pmu_pct_ctl.v
design/sys/iop/spc/pmu/rtl/pmu_pdp_dp.v
design/sys/iop/spc/spu/rtl/spu.v
design/sys/iop/spc/tlu/rtl/tlu.v
design/sys/iop/spc/tlu/rtl/tlu_asi_ctl.v
design/sys/iop/spc/tlu/rtl/tlu_cel_dp.v
design/sys/iop/spc/tlu/rtl/tlu_cep_dp.v
design/sys/iop/spc/tlu/rtl/tlu_cer_dp.v
design/sys/iop/spc/tlu/rtl/tlu_cth_dp.v
design/sys/iop/spc/tlu/rtl/tlu_cxi_ctl.v
design/sys/iop/spc/tlu/rtl/tlu_dfd_dp.v
design/sys/iop/spc/tlu/rtl/tlu_ecd_dp.v
design/sys/iop/spc/tlu/rtl/tlu_ecg_dp.v
design/sys/iop/spc/tlu/rtl/tlu_eem_dp.v
design/sys/iop/spc/tlu/rtl/tlu_fls_ctl.v
design/sys/iop/spc/tlu/rtl/tlu_mbd_dp.v
design/sys/iop/spc/tlu/rtl/tlu_npc_dp.v
design/sys/iop/spc/tlu/rtl/tlu_pct_dp.v
design/sys/iop/spc/tlu/rtl/tlu_ras_ctl.v
design/sys/iop/spc/tlu/rtl/tlu_ssd_dp.v
design/sys/iop/spc/tlu/rtl/tlu_sse_dp.v
design/sys/iop/spc/tlu/rtl/tlu_tel_dp.v
design/sys/iop/spc/tlu/rtl/tlu_tic_dp.v
design/sys/iop/spc/tlu/rtl/tlu_trl_ctl.v
design/sys/iop/spc/tlu/rtl/tlu_tsb_dp.v
design/sys/iop/spc/tlu/rtl/tlu_tsd_dp.v
}

set link_library [concat $link_library \
   dw_foundation.sldb \
]


set mix_files {}
set top_module spc

set include_paths {\
}

set black_box_libs {}
set black_box_designs {}
set mem_libs {}

set dont_touch_modules {\
dec \
exu \
fgu \
gkt \
ifu \
ifu_cmu \
ifu_ftu \
ifu_ibu \
lsu \
mmu \
pku \
pmu \
spu \
tlu \
}

set compile_effort   "medium"

set compile_flatten_all 1

set compile_no_new_cells_at_top_level false

set default_clk gclk
set default_clk_freq  1400
set default_setup_skew  0.0
set default_hold_skew  0.0
set default_clk_transition  0.05
set clk_list {                        \
                { gclk           1400.0   0.000   0.000   0.05}        \
}

set ideal_net_list {}
set false_path_list {}
set enforce_input_fanout_one     0
set allow_outport_drive_innodes  1
set skip_scan            0
set add_lockup_latch     false
set chain_count          1
set scanin_port_list     {}
set scanout_port_list    {}
set scanenable_port      global_shift_enable
set has_test_stub        1
set scanenable_pin       test_stub_no_bist/se
set long_chain_so_0_net  long_chain_so_0
set short_chain_so_0_net short_chain_so_0
set so_0_net             so_0
set insert_extra_lockup_latch 0
set extra_lockup_latch_clk_list {}