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// OpenSPARC T2 Processor File: tlu_cxi_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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wire request_lat_scanout;
wire [2:0] cpx_err_thr_id;
wire [1:0] l_ext_int_type;
wire [5:0] l_ext_int_vec;
wire [2:0] l_ext_int_tid;
wire [7:0] step_pending_in;
wire step_pending_lat_scanin;
wire step_pending_lat_scanout;
wire ss_complete_lat_scanin;
wire ss_complete_lat_scanout;
input [7:0] fls_core_running;
input [3:0] lsu_cpx_req; // Same as "rtntype" in CPX chapter
input [1:0] lsu_cpx_err; // Error type for errors
input lsu_cpx_sre; // software_recoverable_error
input [2:0] lsu_cpx_err_thread_id; // Thread ID from CPX control
input [2:0] lsu_cpx_thread_id; // Thread ID from CPX data
input lsu_cpx_valid; // Valid for CPX packet
input [1:0] lsu_cpx_type; // Interrupt type
input [5:0] lsu_cpx_vector; // Trap requests from crossbar
input lsu_cpx_prefetch; // Prefetch response (not load)
input lsu_ext_interrupt; // Write to interrupt vector dispatch
input [1:0] lsu_ext_int_type; // Type for CPX packet
input [5:0] lsu_ext_int_vec; // Interrupt vector
input [2:0] lsu_ext_int_tid;
input [7:0] trl_ss_complete; // Single step is complete
input [7:0] asi_irl_cleared; // Int_Received Reg had bits cleared
input [63:0] cth_irl_cleared; // Copy of IRR after clearing operations
input tlu_cerer_l2c_socc;
input tlu_cerer_l2u_socu;
output [7:0] cxi_xir; // External Interrupt Request
output [7:0] cxi_ivt; // Interrupt Vector Trap Request
output [7:0] cxi_wr_int_dis; // Interrupt Vector Dispatch packet
output [5:0] cxi_int_dis_vec; // from gasket
output cxi_l2_soc_sre; // software_recoverable_error
output [1:0] cxi_l2_soc_err_type; // C=01, UC=10, ND=11
output [2:0] cxi_l2_soc_tid;
output cxi_l2_err; // L2 error reported
output cxi_soc_err; // SOC error reported
output spc_ss_complete; // Single step complete for all threads
////////////////////////////////////////////////////////////////////////////////
assign pce_ov = tcu_pce_ov;
////////////////////////////////////////////////////////////////////////////////
tlu_cxi_ctl_l1clkhdr_ctl_macro clkgen (
tlu_cxi_ctl_msff_ctl_macro__width_23 request_lat (
.scan_in(request_lat_scanin),
.scan_out(request_lat_scanout),
.din ({lsu_cpx_err [1:0],
lsu_cpx_err_thread_id [2:0],
//////////////////////////////////////////////////////////////////////////////
assign valid_req = cpx_valid & (cpx_req[3:0] == 4'b0111);
{cpx_thr_id[2:0] == 3'b111,
cpx_thr_id[2:0] == 3'b110,
cpx_thr_id[2:0] == 3'b101,
cpx_thr_id[2:0] == 3'b100,
cpx_thr_id[2:0] == 3'b011,
cpx_thr_id[2:0] == 3'b010,
cpx_thr_id[2:0] == 3'b001,
cpx_thr_id[2:0] == 3'b000};
// process CPX interrupt type
assign reset_type = (cpx_type[1:0] == 2'b01);
assign xir_excp = valid_req & reset_type & (cpx_vector[5:0] == 6'b000011);
assign cxi_xir[7:0] = {8 {xir_excp}} & id_decode[7:0];
//////////////////////////////////////////////////////////////////////////////
// Interrupt Vector Dispatch decode
tlu_cxi_ctl_msff_ctl_macro__width_12 ivd_lat (
.scan_in(ivd_lat_scanin),
.scan_out(ivd_lat_scanout),
.din ({lsu_ext_interrupt ,
.dout ({l_ext_interrupt ,
{l_ext_int_tid[2:0] == 3'b111,
l_ext_int_tid[2:0] == 3'b110,
l_ext_int_tid[2:0] == 3'b101,
l_ext_int_tid[2:0] == 3'b100,
l_ext_int_tid[2:0] == 3'b011,
l_ext_int_tid[2:0] == 3'b010,
l_ext_int_tid[2:0] == 3'b001,
l_ext_int_tid[2:0] == 3'b000};
// Check if Interrupt Receive Register is zero
(| cth_irl_cleared[63:0]);
// process interrupt type
assign hwint_type = (l_ext_int_type[1:0] == 2'b00);
assign ivt_excp = l_ext_interrupt & hwint_type;
({8 {ivt_excp}} & ivd_decode[7:0]) |
({8 {irr_ne_0}} & asi_irl_cleared[7:0]) ;
assign cxi_wr_int_dis[7:0] = {8 {ivt_excp}} & ivd_decode[7:0];
assign cxi_int_dis_vec[5:0] = l_ext_int_vec[5:0];
//////////////////////////////////////////////////////////////////////////////
// L2 and SOC error decode
tlu_cxi_ctl_msff_ctl_macro__width_3 cerer_lat (
.scan_in(cerer_lat_scanin),
.scan_out(cerer_lat_scanout),
.din ({tlu_cerer_l2c_socc ,
cpx_valid & (cpx_req[3:0] == 4'b1100) &
((cpx_err[1:0] == 2'b01 & cerer_l2c_socc) |
(cpx_err[1:0] == 2'b10 & cerer_l2u_socu) |
(cpx_err[1:0] == 2'b11 & cerer_l2nd ) ) ;
cpx_valid & (cpx_req[3:0] == 4'b1101) &
((cpx_err[1:0] == 2'b01 & cerer_l2c_socc) |
(cpx_err[1:0] == 2'b10 & cerer_l2u_socu) ) ;
assign valid_prefetch_err =
cpx_valid & (cpx_req[3:0] == 4'b0000) & cpx_prefetch &
((cpx_err[1:0] == 2'b01 & cerer_l2c_socc) |
(cpx_err[1:0] == 2'b10 & cerer_l2u_socu) |
(cpx_err[1:0] == 2'b11 & cerer_l2nd ) ) ;
((cpx_sre | (cpx_req[3:0] == 4'b0000 & cpx_prefetch)) &
(cpx_err[1:0] == 2'b01)) |
((cpx_req[3:0] == 4'b1101) &
(cpx_err[1:0] == 2'b10)) ;
assign cxi_l2_soc_err_type[1:0] =
valid_l2_err | valid_prefetch_err;
assign cxi_l2_soc_tid[2:0] =
//////////////////////////////////////////////////////////////////////////////
// Figure out when all threads have stepped
assign step_pending_in[7:0] =
((fls_core_running[7:0] & {8 {fls_ss_request}}) |
step_pending[7:0]) & ~trl_ss_complete[7:0];
tlu_cxi_ctl_msff_ctl_macro__width_8 step_pending_lat (
.scan_in(step_pending_lat_scanin),
.scan_out(step_pending_lat_scanout),
.din (step_pending_in [7:0] ),
.dout (step_pending [7:0] ),
(| step_pending[7:0]) & ~(| step_pending_in[7:0]);
tlu_cxi_ctl_msff_ctl_macro__width_1 ss_complete_lat (
.scan_in(ss_complete_lat_scanin),
.scan_out(ss_complete_lat_scanout),
//////////////////////////////////////////////////////////////////////////////
tlu_cxi_ctl_spare_ctl_macro__num_1 spares (
.scan_out(spares_scanout),
supply0 vss; // <- port for ground
supply1 vdd; // <- port for power
assign request_lat_scanin = scan_in ;
assign ivd_lat_scanin = request_lat_scanout ;
assign cerer_lat_scanin = ivd_lat_scanout ;
assign step_pending_lat_scanin = cerer_lat_scanout ;
assign ss_complete_lat_scanin = step_pending_lat_scanout ;
assign spares_scanin = ss_complete_lat_scanout ;
assign scan_out = spares_scanout ;
// any PARAMS parms go into naming of macro
module tlu_cxi_ctl_l1clkhdr_ctl_macro (
// any PARAMS parms go into naming of macro
module tlu_cxi_ctl_msff_ctl_macro__width_23 (
assign fdin[22:0] = din[22:0];
.so({so[21:0],scan_out}),
// any PARAMS parms go into naming of macro
module tlu_cxi_ctl_msff_ctl_macro__width_12 (
assign fdin[11:0] = din[11:0];
.so({so[10:0],scan_out}),
// any PARAMS parms go into naming of macro
module tlu_cxi_ctl_msff_ctl_macro__width_3 (
assign fdin[2:0] = din[2:0];
// any PARAMS parms go into naming of macro
module tlu_cxi_ctl_msff_ctl_macro__width_8 (
assign fdin[7:0] = din[7:0];
// any PARAMS parms go into naming of macro
module tlu_cxi_ctl_msff_ctl_macro__width_1 (
assign fdin[0:0] = din[0:0];
// Description: Spare gate macro for control blocks
// Param num controls the number of times the macro is added
// flops=0 can be used to use only combination spare logic
module tlu_cxi_ctl_spare_ctl_macro__num_1 (
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
cl_u1_buf_32x spare0_buf_32x (.in(1'b1),
.out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
.out(spare0_nand3_8x_unused));
cl_u1_inv_8x spare0_inv_8x (.in(1'b1),
.out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
.out(spare0_aoi22_4x_unused));
cl_u1_buf_8x spare0_buf_8x (.in(1'b1),
.out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
.out(spare0_oai22_4x_unused));
cl_u1_inv_16x spare0_inv_16x (.in(1'b1),
.out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
.out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
.out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
.out(spare0_nand2_8x_unused));
cl_u1_buf_16x spare0_buf_16x (.in(1'b1),
.out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
.out(spare0_nor2_16x_unused));
cl_u1_inv_32x spare0_inv_32x (.in(1'b1),
.out(spare0_inv_32x_unused));