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// OpenSPARC T2 Processor File: tlu_ecg_dp.v
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input [67:0] data_in; // Used for generation and checking
output [7:0] ecc_out; // Used for generation and checking
//////////////////////////////////////////////////////////////////////////////
// All odd positions (LSB of position set)
assign check0_bus[36:0] =
{d[67], d[65], d[63], d[61], d[59], d[57],
d[56], d[54], d[52], d[50], d[48], d[46], d[44], d[42],
d[40], d[38], d[36], d[34], d[32], d[30], d[28], d[26],
d[25], d[23], d[21], d[19], d[17], d[15], d[13], d[11],
tlu_ecg_dp_prty_macro__width_4 check0_4_pty (
.din (check0_bus [35:32] ),
tlu_ecg_dp_prty_macro__width_8 check0_3_pty (
.din (check0_bus [31:24] ),
tlu_ecg_dp_prty_macro__width_8 check0_2_pty (
.din (check0_bus [23:16] ),
tlu_ecg_dp_prty_macro__width_8 check0_1_pty (
.din (check0_bus [15:8] ),
tlu_ecg_dp_prty_macro__width_8 check0_0_pty (
.din (check0_bus [7:0] ),
tlu_ecg_dp_prty_macro__width_8 check0_pty (
// All positions with secondmost LSB set
assign check1_bus[36:0] =
{d[67:66], d[63:62], d[59:58],
d[56:55], d[52:51], d[48:47], d[44:43],
d[40:39], d[36:35], d[32:31], d[28:27],
d[25:24], d[21:20], d[17:16], d[13:12],
tlu_ecg_dp_prty_macro__width_4 check1_4_pty (
.din (check1_bus [35:32] ),
tlu_ecg_dp_prty_macro__width_8 check1_3_pty (
.din (check1_bus [31:24] ),
tlu_ecg_dp_prty_macro__width_8 check1_2_pty (
.din (check1_bus [23:16] ),
tlu_ecg_dp_prty_macro__width_8 check1_1_pty (
.din (check1_bus [15:8] ),
tlu_ecg_dp_prty_macro__width_8 check1_0_pty (
.din (check1_bus [7:0] ),
tlu_ecg_dp_prty_macro__width_8 check1_pty (
// All positions with thirdmost LSB set
assign check2_bus[34:0] =
d[56:53], d[48:45], d[40:37], d[32:29],
tlu_ecg_dp_prty_macro__width_8 check2_3_pty (
.din (check2_bus [31:24] ),
tlu_ecg_dp_prty_macro__width_8 check2_2_pty (
.din (check2_bus [23:16] ),
tlu_ecg_dp_prty_macro__width_8 check2_1_pty (
.din (check2_bus [15:8] ),
tlu_ecg_dp_prty_macro__width_8 check2_0_pty (
.din (check2_bus [7:0] ),
tlu_ecg_dp_prty_macro__width_8 check2_pty (
// All positions with fourthmost LSB set
assign check3_bus[34:0] =
tlu_ecg_dp_prty_macro__width_8 check3_3_pty (
.din (check3_bus [31:24] ),
tlu_ecg_dp_prty_macro__width_8 check3_2_pty (
.din (check3_bus [23:16] ),
tlu_ecg_dp_prty_macro__width_8 check3_1_pty (
.din (check3_bus [15:8] ),
tlu_ecg_dp_prty_macro__width_8 check3_0_pty (
.din (check3_bus [7:0] ),
tlu_ecg_dp_prty_macro__width_8 check3_pty (
// All positions with fifthmost LSB set
assign check4_bus[30:0] =
tlu_ecg_dp_prty_macro__width_32 check4_pty (
// All positions with sixthmost LSB set
assign check5_bus[30:0] =
tlu_ecg_dp_prty_macro__width_32 check5_pty (
// All positions with seventhmost LSB set
assign check6_bus[10:0] =
tlu_ecg_dp_prty_macro__width_16 check6_pty (
// Parity of the whole word (including check bits)
//assign check7_bus[74:00] =
// {d[67:00], c0, c1, c2, c3, c4, c5, c6};
// But in generation this simplifies to
// (all d bits with even parity binary positions)
assign check7_bus[36:0] =
// 72 71 68 66 65 63 60 58 57
d[64], d[63], d[60], d[58], d[57], d[56], d[53], d[51], d[50],
// 54 53 51 48 46 45 43 40 39
d[47], d[46], d[44], d[41], d[39], d[38], d[36], d[33], d[32],
// 36 34 33 30 29 27 24 23 20
d[29], d[27], d[26], d[24], d[23], d[21], d[18], d[17], d[14],
// 18 17 15 12 10 9 6 5 3
d[12], d[11], d[10], d[7], d[5], d[4], d[2], d[1], d[0]};
tlu_ecg_dp_prty_macro__width_4 check7_4_pty (
.din (check7_bus [35:32] ),
tlu_ecg_dp_prty_macro__width_8 check7_3_pty (
.din (check7_bus [31:24] ),
tlu_ecg_dp_prty_macro__width_8 check7_2_pty (
.din (check7_bus [23:16] ),
tlu_ecg_dp_prty_macro__width_8 check7_1_pty (
.din (check7_bus [15:8] ),
tlu_ecg_dp_prty_macro__width_8 check7_0_pty (
.din (check7_bus [7:0] ),
tlu_ecg_dp_prty_macro__width_8 check7_pty (
{c7, c6, c5, c4, c3, c2, c1, c0};
supply0 vss; // <- port for ground
supply1 vdd; // <- port for power
// parity macro (even parity)
module tlu_ecg_dp_prty_macro__width_4 (
// parity macro (even parity)
module tlu_ecg_dp_prty_macro__width_8 (
// parity macro (even parity)
module tlu_ecg_dp_prty_macro__width_32 (
// parity macro (even parity)
module tlu_ecg_dp_prty_macro__width_16 (