Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / spc / tlu / rtl / tlu_npc_dp.v
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// OpenSPARC T2 Processor File: tlu_npc_dp.v
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module tlu_npc_dp (
pct0_npc_w,
pct1_npc_w,
fls1_lsu_inst_w,
tlu_npc_w);
input [47:2] pct0_npc_w;
input [47:2] pct1_npc_w;
input fls1_lsu_inst_w;
output [47:2] tlu_npc_w;
//////////////////////////////////////////////////////////////////////
tlu_npc_dp_mux_macro__mux_aope__ports_2__stack_48c__width_46 npc_w_mux (
.din1 (pct0_npc_w [47:2] ),
.din0 (pct1_npc_w [47:2] ),
.sel0 (fls1_lsu_inst_w ),
.dout (tlu_npc_w [47:2] )
);
endmodule
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module tlu_npc_dp_mux_macro__mux_aope__ports_2__stack_48c__width_46 (
din0,
din1,
sel0,
dout);
wire psel0;
wire psel1;
input [45:0] din0;
input [45:0] din1;
input sel0;
output [45:0] dout;
cl_dp1_penc2_8x c0_0 (
.sel0(sel0),
.psel0(psel0),
.psel1(psel1)
);
mux2s #(46) d0_0 (
.sel0(psel0),
.sel1(psel1),
.in0(din0[45:0]),
.in1(din1[45:0]),
.dout(dout[45:0])
);
endmodule