// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: tlu_pct_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// choice is available it will apply instead, Sun elects to use only
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// ========== Copyright Header End ============================================
wire target_b_lat_scanin;
wire target_b_lat_scanout;
wire [47:2] npc_plus_4_noncrit_b;
wire [47:2] npc_noncrit_b;
wire npc_3_w_lat_scanout;
wire [47:2] npc_plus_8_b;
wire npc_2_w_lat_scanout;
wire npc_1_w_lat_scanout;
wire npc_0_w_lat_scanout;
wire [47:2] npc_plus_4_b;
wire npc_33_02_plus_4_cout_b;
wire [49:48] npc_plus_4_b_unused;
wire npc_49_34_plus_4_cout_b_unused;
wire npc_34_03_plus_8_cout_b;
wire [50:48] npc_plus_8_b_unused;
wire npc_50_35_plus_8_cout_b_unused;
wire [47:2] tsa_pc_unmasked_w;
wire [47:2] tsa_npc_unmasked_w;
wire [4:0] wmr_vec_mask_;
wire trap_pc_lat_scanout;
wire [31:5] piped_pc_pre_buf_w;
wire [12:11] piped_pc_pre_buf_w_unused;
wire [12:11] piped_pc_w_unused;
wire [47:32] masked_pc_w;
wire [3:0] tid_dec_buf_d;
wire [47:2] pre_npc_noncrit_d;
wire [63:22] npc_inc_unused;
wire npc_inc_cout_d_unused;
wire [47:2] pc_noncrit_d;
wire [47:32] masked_pc_d;
wire iaw_lat_wmr_scanout;
input spc_aclk_wmr; // Warm reset (non)scan
// RSTVADDR (POR address) control
input tcu_wmr_vec_mask; // PINDEF:BOT
input [1:0] dec_inst_cnt; // Count of instructions in E, M, B
input [3:0] dec_raw_pick_p; // Decoded TID at P
input [47:2] exu_address_m; // Target for taken branches
input [47:0] mmu_itte_tag_data;
input [47:0] asi_wr_data;
input [3:0] fls_tid_dec_b;
input [3:0] fls_tid_dec_w;
input [3:0] fls_pc_sel_npc; // Sequential flow
input [3:0] fls_pc_sel_npc_plus_4; // Branch taken or(not taken with annul)
input [3:0] fls_npc_sel_npc_plus_4; // Sequential flow
input [3:0] fls_npc_sel_npc_plus_8; // Branch not taken with annul
input [3:0] fls_npc_sel_target; // Branch taken
input fls_npc_b_sel_npc; // NPC is invalid (but going valid)
input fls_pc_is_npc; // PC reg actually holds NPC, not PC
input fls_pstate_am_d_; // For instruction watchpoint
input fls_pstate_am_b_; // For dsfar
input fls_pstate_am_w_; // For itlb_tag_access
input [4:2] fls_npc_if_cnt_eq_1_d;
input [4:2] fls_npc_if_cnt_eq_2_d;
input [4:2] fls_npc_if_cnt_eq_3_d;
input [3:0] fls_pct_pc_en; // Power managment for PC flops
input [3:0] fls_pct_npc_en; // Power managment for NPC flops
input [3:0] trl_pc_sel_trap_pc; // Trap, retry, or done taken; update PC
input [3:0] trl_npc_sel_trap_npc; // Trap taken; update NPC
input [3:0] trl_npc_sel_tnpc; // Retry or done taken; update NPC
input [8:0] trl_trap_type; // Trap type
input [3:0] trl_pc_thread_sel; // Which thread is trapping
input trl_pc_sel_pc; // Retry the excepting instruction
input trl_pc_sel_npc; // Advance to the next instruction
input trl_pc_sel_trap; // Select the trap PC
input trl_pc_sel_reset; // Select the reset PC
input trl_pc_done; // Select the NPC from the stack
input trl_pc_retry; // Select the PC from the stack
input trl_pc_tte; // Select the TTE for ITLB write
input trl_pct_trap_pc_en; // Power management
input [47:14] tsd_tba; // Trap Base Address
input [47:2] tsd_asi_data_;
input [3:0] tsd_pstate_am;
output wmr_scan_out; // Warm reset (non)scan
output [48:2] pct_asi_data;
output [3:2] pct_npc_0_w;
output [3:2] pct_npc_1_w;
output [3:2] pct_npc_2_w;
output [3:2] pct_npc_3_w;
output [47:2] pct_tsa_pc;
output pct_tsa_pc_oor_va;
output [47:2] pct_tsa_npc;
output pct_tsa_npc_oor_va;
output pct_tsa_npc_nonseq;
output [3:0] pct_npc_is_nonseq;
output [1:0] pct_iaw_exc_e;
output [47:2] pct_shadow_pc_d;
output [47:2] pct_target_b;
output [16:0] pct_trl_wr_data;
output [47:0] tlu_trap_pc;
////////////////////////////////////////////////////////////////////////////////
assign test = tcu_dectest;
tlu_pct_dp_buff_macro__width_4 clk_control_buf (
////////////////////////////////////////////////////////////////////////////////
// Pass target from M to B
tlu_pct_dp_msff_macro__stack_48c__width_48 target_b_lat (
.scan_in(target_b_lat_scanin),
.scan_out(target_b_lat_scanout),
.din ({tcu_wmr_vec_mask ,
tlu_pct_dp_and_macro__ports_2__stack_48c__width_46 target_b_buf (
.din0 (target_b [47:2] ),
.din1 ({{16 {fls_pstate_am_b_}} ,
.dout (pct_target_b [47:2] )
////////////////////////////////////////////////////////////////////////////////
// Save each thread's PC and NPC
// Have to use trap_pc because it merges any_trap_pc and reset_trap_pc
// Also already has TPC and TNPC merged in...
// PC update to trap vector value should happen concurrently with TSA update
tlu_pct_dp_buff_macro__stack_48c__width_1 flush_b_buf (
tlu_pct_dp_msff_macro__mux_aope__ports_5__stack_48c__width_47 pc_3_w_lat (
.scan_in(pc_3_w_lat_scanin),
.scan_out(pc_3_w_lat_scanout),
npc_plus_4_noncrit_b [47:2]}),
.sel0 (trl_pc_sel_trap_pc [3 ] ),
.sel2 (fls_pc_sel_npc_plus_4 [3 ] ),
.sel3 (fls_pc_sel_npc [3 ] ),
.en (fls_pct_pc_en [3 ] ),
tlu_pct_dp_msff_macro__mux_aope__ports_5__stack_48c__width_47 pc_2_w_lat (
.scan_in(pc_2_w_lat_scanin),
.scan_out(pc_2_w_lat_scanout),
npc_plus_4_noncrit_b [47:2]}),
.sel0 (trl_pc_sel_trap_pc [2 ] ),
.sel2 (fls_pc_sel_npc_plus_4 [2 ] ),
.sel3 (fls_pc_sel_npc [2 ] ),
.en (fls_pct_pc_en [2 ] ),
tlu_pct_dp_msff_macro__mux_aope__ports_5__stack_48c__width_47 pc_1_w_lat (
.scan_in(pc_1_w_lat_scanin),
.scan_out(pc_1_w_lat_scanout),
npc_plus_4_noncrit_b [47:2]}),
.sel0 (trl_pc_sel_trap_pc [1 ] ),
.sel2 (fls_pc_sel_npc_plus_4 [1 ] ),
.sel3 (fls_pc_sel_npc [1 ] ),
.en (fls_pct_pc_en [1 ] ),
tlu_pct_dp_msff_macro__mux_aope__ports_5__stack_48c__width_47 pc_0_w_lat (
.scan_in(pc_0_w_lat_scanin),
.scan_out(pc_0_w_lat_scanout),
npc_plus_4_noncrit_b [47:2]}),
.sel0 (trl_pc_sel_trap_pc [0 ] ),
.sel2 (fls_pc_sel_npc_plus_4 [0 ] ),
.sel3 (fls_pc_sel_npc [0 ] ),
.en (fls_pct_pc_en [0 ] ),
// Hold tsd_tnpc for one cycle to allow for ECC check of TSA
tlu_pct_dp_msff_macro__minbuff_1__stack_48c__width_48 tnpc_lat (
.scan_in(tnpc_lat_scanin),
.scan_out(tnpc_lat_scanout),
tlu_pct_dp_msff_macro__mux_aope__ports_7__stack_48c__width_48 npc_3_w_lat (
.scan_in(npc_3_w_lat_scanin),
.scan_out(npc_3_w_lat_scanout),
npc_plus_4_noncrit_b [47:2]}),
.sel0 (trl_npc_sel_trap_npc [3 ] ),
.sel1 (trl_npc_sel_tnpc [3 ] ),
.sel3 (fls_npc_sel_target [3 ] ),
.sel4 (fls_npc_sel_npc_plus_8 [3 ] ),
.sel5 (fls_npc_sel_npc_plus_4 [3 ] ),
.en (fls_pct_npc_en [3 ] ),
tlu_pct_dp_buff_macro__stack_48c__width_2 npc_3_w_buf (
.din (npc_3_crit_w [3:2] ),
tlu_pct_dp_msff_macro__mux_aope__ports_7__stack_48c__width_48 npc_2_w_lat (
.scan_in(npc_2_w_lat_scanin),
.scan_out(npc_2_w_lat_scanout),
npc_plus_4_noncrit_b [47:2]}),
.sel0 (trl_npc_sel_trap_npc [2 ] ),
.sel1 (trl_npc_sel_tnpc [2 ] ),
.sel3 (fls_npc_sel_target [2 ] ),
.sel4 (fls_npc_sel_npc_plus_8 [2 ] ),
.sel5 (fls_npc_sel_npc_plus_4 [2 ] ),
.en (fls_pct_npc_en [2 ] ),
tlu_pct_dp_buff_macro__stack_48c__width_2 npc_2_w_buf (
.din (npc_2_crit_w [3:2] ),
tlu_pct_dp_msff_macro__mux_aope__ports_7__stack_48c__width_48 npc_1_w_lat (
.scan_in(npc_1_w_lat_scanin),
.scan_out(npc_1_w_lat_scanout),
npc_plus_4_noncrit_b [47:2]}),
.sel0 (trl_npc_sel_trap_npc [1 ] ),
.sel1 (trl_npc_sel_tnpc [1 ] ),
.sel3 (fls_npc_sel_target [1 ] ),
.sel4 (fls_npc_sel_npc_plus_8 [1 ] ),
.sel5 (fls_npc_sel_npc_plus_4 [1 ] ),
.en (fls_pct_npc_en [1 ] ),
tlu_pct_dp_buff_macro__stack_48c__width_2 npc_1_w_buf (
.din (npc_1_crit_w [3:2] ),
tlu_pct_dp_msff_macro__mux_aope__ports_7__stack_48c__width_48 npc_0_w_lat (
.scan_in(npc_0_w_lat_scanin),
.scan_out(npc_0_w_lat_scanout),
npc_plus_4_noncrit_b [47:2]}),
.sel0 (trl_npc_sel_trap_npc [0 ] ),
.sel1 (trl_npc_sel_tnpc [0 ] ),
.sel3 (fls_npc_sel_target [0 ] ),
.sel4 (fls_npc_sel_npc_plus_8 [0 ] ),
.sel5 (fls_npc_sel_npc_plus_4 [0 ] ),
.en (fls_pct_npc_en [0 ] ),
tlu_pct_dp_buff_macro__stack_48c__width_2 npc_0_w_buf (
.din (npc_0_crit_w [3:2] ),
assign pct_npc_is_nonseq[3:0] =
{npc_3_nonseq, npc_2_nonseq, npc_1_nonseq, npc_0_nonseq};
////////////////////////////////////////////////////////////////////////////////
tlu_pct_dp_mux_macro__dmux_8x__mux_aonpe__ports_4__stack_48c__width_47 npc_incr_mux (
.sel0 (fls_tid_dec_b [0 ] ),
.sel1 (fls_tid_dec_b [1 ] ),
.sel2 (fls_tid_dec_b [2 ] ),
.sel3 (fls_tid_dec_b [3 ] ),
tlu_pct_dp_buff_macro__stack_48c__width_46 npc_buf (
.dout (npc_noncrit_b [47:2] )
tlu_pct_dp_increment_macro__width_32 npc_33_02_plus_4_b_inc (
.dout (npc_plus_4_b [33:2] ),
.cout (npc_33_02_plus_4_cout_b )
tlu_pct_dp_increment_macro__width_16 npc_plus_4_u_b_inc (
.cin (npc_33_02_plus_4_cout_b ),
.dout ({npc_plus_4_b_unused [49:48],
.cout (npc_49_34_plus_4_cout_b_unused )
tlu_pct_dp_buff_macro__stack_48c__width_46 npc_plus_4_noncrit_b_buf (
.din (npc_plus_4_b [47:2] ),
.dout (npc_plus_4_noncrit_b [47:2] )
tlu_pct_dp_increment_macro__width_32 npc_34_03_plus_8_b_inc (
.dout (npc_plus_8_b [34:3] ),
.cout (npc_34_03_plus_8_cout_b )
assign npc_plus_8_b[2] = npc_noncrit_b[2];
tlu_pct_dp_increment_macro__width_16 npc_47_35_plus_8_b_inc (
.cin (npc_34_03_plus_8_cout_b ),
.dout ({npc_plus_8_b_unused [50:48],
.cout (npc_50_35_plus_8_cout_b_unused )
// Generate NPC for instruction in W for load sync case for fetch
// Only has to be correct for loads that are not flushed
tlu_pct_dp_msff_macro__mux_pgpe__ports_2__stack_48c__width_46 npc_w_lat (
.scan_in(npc_b_mux_scanin),
.scan_out(npc_b_mux_scanout),
.din0 (npc_noncrit_b [47:2] ),
.din1 (npc_plus_4_b [47:2] ),
.sel0 (fls_npc_b_sel_npc ),
.dout (pct_npc_w [47:2] ),
////////////////////////////////////////////////////////////////////////////////
tlu_pct_dp_mux_macro__mux_aonpe__ports_4__stack_48c__width_47 pc_mux (
.sel0 (trl_pc_thread_sel [0 ] ),
.sel1 (trl_pc_thread_sel [1 ] ),
.sel2 (trl_pc_thread_sel [2 ] ),
.sel3 (trl_pc_thread_sel [3 ] ),
.dout ({tsa_pc_oor_va_w ,
tsa_pc_unmasked_w [47:2]})
tlu_pct_dp_and_macro__left_30__ports_2__stack_48c__width_16 tsa_pc_w_and (
.din0 (tsa_pc_unmasked_w [47:32] ),
.din1 ({16 {trl_pc_pstate_am_}} ),
.dout (tsa_pc_w [47:32] )
assign pct_tsa_pc[47:2] =
tsa_pc_unmasked_w [31:2]};
assign pct_tsa_pc_oor_va =
tlu_pct_dp_mux_macro__mux_aonpe__ports_4__stack_48c__width_48 npc_mux (
.sel0 (trl_pc_thread_sel [0 ] ),
.sel1 (trl_pc_thread_sel [1 ] ),
.sel2 (trl_pc_thread_sel [2 ] ),
.sel3 (trl_pc_thread_sel [3 ] ),
tsa_npc_unmasked_w [47:2]})
tlu_pct_dp_and_macro__left_30__ports_2__stack_48c__width_16 tsa_npc_w_and (
.din0 (tsa_npc_unmasked_w [47:32] ),
.din1 ({16 {trl_pc_pstate_am_}} ),
.dout (tsa_npc_w [47:32] )
assign pct_tsa_npc[47:2] =
tsa_npc_unmasked_w [31:2]};
assign pct_tsa_npc_oor_va =
assign pct_tsa_npc_nonseq =
assign any_trap_pc[47:14] =
assign any_trap_pc[13:5] =
assign any_trap_pc[4:2] =
// Select RSTVADDR == 48'hfffff0000000 or == 0
// Create a tree to prevent overloading of flop
tlu_pct_dp_inv_macro__stack_48c__width_5 reset_pc_inv (
.din ({5 {wmr_vec_mask}} ),
.dout (wmr_vec_mask_ [4:0] )
{{ 4 {wmr_vec_mask_[4]}},
// Selects are checked with 0in inside trl
tlu_pct_dp_msff_macro__mux_aope__ports_8__stack_48c__width_48 trap_pc_lat (
.scan_in(trap_pc_lat_scanin),
.scan_out(trap_pc_lat_scanout),
.din0 ({tsa_pc_unmasked_w [47:2],
.din1 ({tsa_npc_unmasked_w [47:2],
.din2 ({any_trap_pc [47:2],
.din6 (mmu_itte_tag_data [47:0] ),
.sel2 (trl_pc_sel_trap ),
.sel3 (trl_pc_sel_reset ),
.en (trl_pct_trap_pc_en ),
assign tlu_trap_pc[47:0] =
////////////////////////////////////////////////////////////////////////////////
// Pass PC in W for tag_access reg
tlu_pct_dp_mux_macro__left_3__mux_aonpe__ports_4__stack_48c__width_43 piped_pc_w_mux (
.sel0 (fls_tid_dec_w [0 ] ),
.sel1 (fls_tid_dec_w [1 ] ),
.sel2 (fls_tid_dec_w [2 ] ),
.sel3 (fls_tid_dec_w [3 ] ),
.dout ({piped_pc_w [47:32],
piped_pc_pre_buf_w [31:5]})
tlu_pct_dp_buff_macro__left_3__rep_1__stack_48c__width_27 piped_pc_w_buf (
.din (piped_pc_pre_buf_w [31:5] ),
.dout (piped_pc_w [31:5] )
assign piped_pc_pre_buf_w_unused[12:11] =
piped_pc_pre_buf_w[12:11];
assign piped_pc_w_unused[12:11] =
tlu_pct_dp_and_macro__left_30__ports_2__stack_48c__width_16 masked_pc_w_and (
.din0 (piped_pc_w [47:32] ),
.din1 ({16 {fls_pstate_am_w_}} ),
.dout (masked_pc_w [47:32] )
{masked_pc_w[47:32], piped_pc_w[31:13]};
////////////////////////////////////////////////////////////////////////////////
// Mux PC for shadow scan
////////////////////////////////////////////////////////////////////////////////
// Generate PC for instruction in D
assign pct_npc_3_w[3:2] =
assign pct_npc_2_w[3:2] =
assign pct_npc_1_w[3:2] =
assign pct_npc_0_w[3:2] =
tlu_pct_dp_mux_macro__dmux_8x__mux_aonpe__ports_4__stack_48c__width_47 pre_pc_d_mux (
.sel0 (tid_dec_buf_d [0] ),
.sel1 (tid_dec_buf_d [1] ),
.sel2 (tid_dec_buf_d [2] ),
.sel3 (tid_dec_buf_d [3] ),
.dout ({pre_pc_oor_va_d ,
// Muxing down PSTATE.am for PC reads. However, if reading
// instruction VA watchpoint, then masking must NOT occur
tlu_pct_dp_nand_macro__ports_2__width_4 pstate_am_b_nand (
.din0 (asi_rd_pc [3:0] ),
.din1 (tsd_pstate_am [3:0] ),
.dout (pstate_am_ [3:0] )
tlu_pct_dp_nand_macro__ports_4__width_1 rd_pc_pstate_am_in_nand (
.din0 (pstate_am_ [0 ] ),
.din1 (pstate_am_ [1 ] ),
.din2 (pstate_am_ [2 ] ),
.din3 (pstate_am_ [3 ] ),
.dout (rd_pc_pstate_am_in )
tlu_pct_dp_msff_macro__left_20__stack_48c__width_10 tid_d_lat (
.scan_in(tid_d_lat_scanin),
.scan_out(tid_d_lat_scanout),
.din ({rd_pc_pstate_am_in ,
.dout ({prd_pc_pstate_am ,
tlu_pct_dp_inv_macro__width_1 rd_iaw_b_inv (
tlu_pct_dp_nand_macro__ports_2__width_1 rd_pc_pstate_am_b_nand (
.din1 (prd_pc_pstate_am ),
.dout (rd_pc_pstate_am_ )
tlu_pct_dp_buff_macro__stack_48c__width_4 tid_d_buf (
.dout (tid_dec_buf_d [3:0] )
tlu_pct_dp_mux_macro__dmux_8x__mux_aonpe__ports_4__stack_48c__width_47 pre_npc_d_mux (
.dout ({pre_npc_oor_va_d ,
tlu_pct_dp_buff_macro__stack_48c__width_46 pre_npc_noncrit_d_buf (
.din (pre_npc_d [47:2] ),
.dout (pre_npc_noncrit_d [47:2] )
// The increment can be before the mux because you have to use the
// NPC if the count is nonzero
// Bits are separated to account for alignment with 48c stack and
// that the lower two bits are not used
tlu_pct_dp_increment_macro__width_64 pc_d_47_04_inc (
.dout ({npc_inc_unused [63:52],
.cout (npc_inc_cout_d_unused )
// Must take PC if PC actually holds NPC
// If a branch in the delay slot of another branch is at decode
// (signified by dec_inst_cnt[01:00] being nonzero), then the PC is no longer
tlu_pct_dp_or_macro__stack_48c__width_1 inst_cnt_nz_or (
.din0 (dec_inst_cnt [1 ] ),
.din1 (dec_inst_cnt [0 ] ),
tlu_pct_dp_inv_macro__width_2 inst_cnt_inv_inv (
.din (dec_inst_cnt [1:0] ),
tlu_pct_dp_nand_macro__ports_3__width_3 npc_inc_0_d_nand (
.din1 ({3 {inst_cnt_[1]}} ),
.din2 ({3 {inst_cnt_[0]}} ),
.dout (npc_inc_0_d [4:2] )
tlu_pct_dp_nand_macro__ports_3__width_3 npc_inc_1_d_nand (
.din0 (fls_npc_if_cnt_eq_1_d [4:2] ),
.din1 ({3 {inst_cnt_[1]}} ),
.din2 ({3 {dec_inst_cnt[0]}} ),
.dout (npc_inc_1_d [4:2] )
tlu_pct_dp_nand_macro__ports_3__width_3 npc_inc_2_d_nand (
.din0 (fls_npc_if_cnt_eq_2_d [4:2] ),
.din1 ({3 {dec_inst_cnt[1]}} ),
.din2 ({3 {inst_cnt_[0]}} ),
.dout (npc_inc_2_d [4:2] )
tlu_pct_dp_nand_macro__ports_3__width_3 npc_inc_3_d_nand (
.din0 (fls_npc_if_cnt_eq_3_d [4:2] ),
.din1 ({3 {dec_inst_cnt[1]}} ),
.din2 ({3 {dec_inst_cnt[0]}} ),
.dout (npc_inc_3_d [4:2] )
tlu_pct_dp_nand_macro__ports_4__width_3 npc_inc_d_nand (
.din0 (npc_inc_0_d [4:2] ),
.din1 (npc_inc_1_d [4:2] ),
.din2 (npc_inc_2_d [4:2] ),
.din3 (npc_inc_3_d [4:2] ),
tlu_pct_dp_buff_macro__dbuff_48x__width_1 tst_mux_rep3 (
.dout (tcu_muxtest_rep3 )
tlu_pct_dp_mux_macro__mux_pgpe__ports_4__stack_48c__width_47 pc_d_mux (
.din0 ({pre_npc_oor_va_d ,
.din1 ({pre_npc_oor_va_d ,
pre_npc_noncrit_d [47:4],
.din2 ({pre_pc_oor_va_d ,
.din3 ({pre_npc_oor_va_d ,
pre_npc_noncrit_d [47:2]}),
.muxtst (tcu_muxtest_rep3 ),
tlu_pct_dp_buff_macro__rep_1__stack_48c__width_46 pc_noncrit_d_buf (
.dout (pc_noncrit_d [47:2] )
assign pct_shadow_pc_d[47:2] =
////////////////////////////////////////////////////////////////////////////////
// Compare instruction watchpoint in E
tlu_pct_dp_and_macro__left_30__ports_2__stack_48c__width_17 am_and (
.din1 ({17 {fls_pstate_am_d_}} ),
.dout ({masked_pc_oor_va_d ,
tlu_pct_dp_msff_macro__stack_48c__width_47 pc_e_lat (
.scan_in(pc_e_lat_scanin),
.scan_out(pc_e_lat_scanout),
.din ({masked_pc_oor_va_d ,
tlu_pct_dp_msff_macro__stack_48c__width_47 iaw_lat ( // FS:wmr_protect
.scan_in(iaw_lat_wmr_scanin),
.scan_out(iaw_lat_wmr_scanout),
tlu_pct_dp_buff_macro__rep_1__stack_48c__width_17 wr_data_buf (
.din ({asi_wr_data [1:0],
.dout ({pct_trl_wr_data [1:0],
tlu_pct_dp_cmp_macro__width_16 iaw_47_34_cmp (
.dout (pct_iaw_exc_e [1 ] )
tlu_pct_dp_cmp_macro__width_32 iaw_33_02_cmp (
.dout (pct_iaw_exc_e [0 ] )
////////////////////////////////////////////////////////////////////////////////
tlu_pct_dp_mux_macro__mux_aonpe__ports_5__stack_48c__width_47 asi_pc_mux (
.din0 ({1'b0, pc_0_w [47:2]}),
.din1 ({1'b0, pc_1_w [47:2]}),
.din2 ({1'b0, pc_2_w [47:2]}),
.din3 ({1'b0, pc_3_w [47:2]}),
.din4 ({iaw_en, iaw_va [47:2]}),
tlu_pct_dp_nand_macro__ports_2__stack_48c__width_47 asi_data_0_b_nand (
.din0 ({{17 {rd_pc_pstate_am_}} ,
.din1 (asi_data [48:2] ),
.dout (asi_data_0_ [48:2] )
tlu_pct_dp_nand_macro__ports_2__stack_48c__width_47 asi_data_nand (
.din0 ({1'b1, tsd_asi_data_ [47:2]}),
.din1 (asi_data_0_ [48:2] ),
.dout (pct_asi_data [48:2] )
assign target_b_lat_scanin = scan_in ;
assign pc_3_w_lat_scanin = target_b_lat_scanout ;
assign pc_2_w_lat_scanin = pc_3_w_lat_scanout ;
assign pc_1_w_lat_scanin = pc_2_w_lat_scanout ;
assign pc_0_w_lat_scanin = pc_1_w_lat_scanout ;
assign tnpc_lat_scanin = pc_0_w_lat_scanout ;
assign npc_3_w_lat_scanin = tnpc_lat_scanout ;
assign npc_2_w_lat_scanin = npc_3_w_lat_scanout ;
assign npc_1_w_lat_scanin = npc_2_w_lat_scanout ;
assign npc_0_w_lat_scanin = npc_1_w_lat_scanout ;
assign npc_b_mux_scanin = npc_0_w_lat_scanout ;
assign trap_pc_lat_scanin = npc_b_mux_scanout ;
assign tid_d_lat_scanin = trap_pc_lat_scanout ;
assign pc_e_lat_scanin = tid_d_lat_scanout ;
assign scan_out = pc_e_lat_scanout ;
assign iaw_lat_wmr_scanin = wmr_scan_in ;
assign wmr_scan_out = iaw_lat_wmr_scanout ;
module tlu_pct_dp_buff_macro__width_4 (
// any PARAMS parms go into naming of macro
module tlu_pct_dp_msff_macro__stack_48c__width_48 (
.so({so[46:0],scan_out}),
// and macro for ports = 2,3,4
module tlu_pct_dp_and_macro__ports_2__stack_48c__width_46 (
module tlu_pct_dp_buff_macro__stack_48c__width_1 (
// any PARAMS parms go into naming of macro
module tlu_pct_dp_msff_macro__mux_aope__ports_5__stack_48c__width_47 (
.so({so[45:0],scan_out}),
// any PARAMS parms go into naming of macro
module tlu_pct_dp_msff_macro__minbuff_1__stack_48c__width_48 (
.so({so[46:0],scan_out}),
// any PARAMS parms go into naming of macro
module tlu_pct_dp_msff_macro__mux_aope__ports_7__stack_48c__width_48 (
.so({so[46:0],scan_out}),
module tlu_pct_dp_buff_macro__stack_48c__width_2 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module tlu_pct_dp_mux_macro__dmux_8x__mux_aonpe__ports_4__stack_48c__width_47 (
cl_dp1_muxbuff4_8x c0_0 (
module tlu_pct_dp_buff_macro__stack_48c__width_46 (
module tlu_pct_dp_increment_macro__width_32 (
module tlu_pct_dp_increment_macro__width_16 (
// any PARAMS parms go into naming of macro
module tlu_pct_dp_msff_macro__mux_pgpe__ports_2__stack_48c__width_46 (
.so({so[44:0],scan_out}),
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module tlu_pct_dp_mux_macro__mux_aonpe__ports_4__stack_48c__width_47 (
cl_dp1_muxbuff4_8x c0_0 (
// and macro for ports = 2,3,4
module tlu_pct_dp_and_macro__left_30__ports_2__stack_48c__width_16 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module tlu_pct_dp_mux_macro__mux_aonpe__ports_4__stack_48c__width_48 (
cl_dp1_muxbuff4_8x c0_0 (
module tlu_pct_dp_inv_macro__stack_48c__width_5 (
// any PARAMS parms go into naming of macro
module tlu_pct_dp_msff_macro__mux_aope__ports_8__stack_48c__width_48 (
.so({so[46:0],scan_out}),
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module tlu_pct_dp_mux_macro__left_3__mux_aonpe__ports_4__stack_48c__width_43 (
cl_dp1_muxbuff4_8x c0_0 (
module tlu_pct_dp_buff_macro__left_3__rep_1__stack_48c__width_27 (
// nand macro for ports = 2,3,4
module tlu_pct_dp_nand_macro__ports_2__width_4 (
// nand macro for ports = 2,3,4
module tlu_pct_dp_nand_macro__ports_4__width_1 (
// any PARAMS parms go into naming of macro
module tlu_pct_dp_msff_macro__left_20__stack_48c__width_10 (
module tlu_pct_dp_inv_macro__width_1 (
// nand macro for ports = 2,3,4
module tlu_pct_dp_nand_macro__ports_2__width_1 (
module tlu_pct_dp_buff_macro__stack_48c__width_4 (
module tlu_pct_dp_increment_macro__width_64 (
// or macro for ports = 2,3
module tlu_pct_dp_or_macro__stack_48c__width_1 (
module tlu_pct_dp_inv_macro__width_2 (
// nand macro for ports = 2,3,4
module tlu_pct_dp_nand_macro__ports_3__width_3 (
// nand macro for ports = 2,3,4
module tlu_pct_dp_nand_macro__ports_4__width_3 (
module tlu_pct_dp_buff_macro__dbuff_48x__width_1 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module tlu_pct_dp_mux_macro__mux_pgpe__ports_4__stack_48c__width_47 (
module tlu_pct_dp_buff_macro__rep_1__stack_48c__width_46 (
// and macro for ports = 2,3,4
module tlu_pct_dp_and_macro__left_30__ports_2__stack_48c__width_17 (
// any PARAMS parms go into naming of macro
module tlu_pct_dp_msff_macro__stack_48c__width_47 (
.so({so[45:0],scan_out}),
module tlu_pct_dp_buff_macro__rep_1__stack_48c__width_17 (
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module tlu_pct_dp_cmp_macro__width_16 (
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module tlu_pct_dp_cmp_macro__width_32 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module tlu_pct_dp_mux_macro__mux_aonpe__ports_5__stack_48c__width_47 (
cl_dp1_muxbuff5_8x c0_0 (
// nand macro for ports = 2,3,4
module tlu_pct_dp_nand_macro__ports_2__stack_48c__width_47 (