// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: cl_a1.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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// it under the terms of the GNU General Public License as published by
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// ========== Copyright Header End ============================================
module cl_a1_msffmin_fp_16x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffmin_fp_8x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffmin_fp_4x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffmin_fp_32x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffmin_fp_1x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffmin_fp_30ps_16x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffmin_fp_30ps_8x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffmin_fp_30ps_4x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffmin_fp_30ps_32x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffmin_fp_30ps_1x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffmin_fp_syrst_1x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_a1_msffmin_fp_syrst_4x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_a1_msffmin_fp_syrst_8x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_a1_msffmin_fp_syrst_16x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_a1_msffmin_fp_syrst_32x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_a1_msffmin_30ps_16x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffmin_30ps_8x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffmin_30ps_4x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffmin_30ps_32x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffmin_30ps_1x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_clken_msffmin_4x ( q, so, d, l1clk, si, siclk, soclk, clken);
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d & clken ) | (q & !clken); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d & clken ) | (q & !clken);
module cl_a1_msffmin_syrst_1x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_a1_msffmin_syrst_4x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_a1_msffmin_syrst_8x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_a1_msffmin_syrst_16x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_a1_msffmin_syrst_32x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_a1_bsac_cell_4x(q, so, d, l1clk, si, siclk, soclk, updateclk,
ac_mode, ac_test_signal);
input updateclk, ac_mode;
wire l1clk, siclk, soclk, updateclk;
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
if ( l1clk && siclk) l1 <= si; // Load master with
if (!l1clk && siclk) l1 <= 1'bx; // Conflict between
if ( l1clk && !soclk) so <= l1; // Load slave with
if ( l1clk && siclk && !soclk) so <= si; // Flush
always@(ac_mode or qm or ac_test_signal)
else q=qm ^ ac_test_signal;
module cl_a1_blatch_4x ( latout, so, d, l1clk, si, siclk, soclk);
always @(posedge l1clk or posedge siclk ) begin
m <= 1'b0; //pseudo flush reset
s <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si) begin
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && siclk) m <= si; // Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan
if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data
else if (l1clk && siclk && !soclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if(siclk==0 && l1clk==0) m = d;
else if(siclk && !l1clk) m = 1'bx;
if(siclk && l1clk) m = si;
if(l1clk && !soclk) s = m;
module cl_a1_alatch_4x ( q, so, d, l1clk, si, siclk, soclk, se );
wire l1clk, siclk, soclk;
always @(l1clk or siclk or soclk or d or si or se)
if (siclk) l1 <= si; // Load master with scan or flush
if(se && !soclk && l1clk && siclk) q <= si;
else if ( se && !soclk && l1clk) q <= l1;
else if ( !soclk && l1clk) q <= d;
module cl_a1_clken_msff_4x ( q, so, d, l1clk, si, siclk, soclk, clken);
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
q <= (d & clken ) | (q & !clken);
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d & clken ) | (q & !clken); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d & clken ) | (q & !clken);
module cl_a1_msff_arst_4x ( q, so, d, l1clk, si, siclk, soclk, reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or soclk or d or si or reset)
else if (!l1clk && !siclk) l1 <= d;
else if ( l1clk && siclk) l1 <= si;
else if (!l1clk && siclk) l1 <= 1'bx;
else if ( l1clk && !siclk && !soclk) q <= l1;
else if ( l1clk && siclk && !soclk) q <= si;
assign siclk_unused = siclk;
assign soclk_unused = soclk;
always @(posedge l1clk or posedge reset)
else if (!siclk && !soclk ) q <= d;
module cl_a1_aomux2_12x (
assign out = ((sel0 & in0) |
module cl_a1_aomux2_16x (
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
module cl_a1_aomux3_12x (
assign out = ((sel0 & in0) |
module cl_a1_aomux3_16x (
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
module cl_a1_aomux4_12x (
assign out = ((sel0 & in0) |
module cl_a1_aomux4_16x (
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
module cl_a1_aomux4_niu_8x (
assign out = ((sel0 & in0) |
module cl_a1_aomux5_12x (
assign out = ((sel0 & in0) |
module cl_a1_aomux5_16x (
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
module cl_a1_aomux6_12x (
assign out = ((sel0 & in0) |
module cl_a1_aomux6_16x (
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
module cl_a1_aomux6_by2_1x (
assign out = ((sel0 & in0) |
module cl_a1_aomux6_by2_2x (
assign out = ((sel0 & in0) |
module cl_a1_aomux7_12x (
assign out = ((sel0 & in0) |
module cl_a1_aomux7_16x (
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
module cl_a1_aomux7_by2_1x (
assign out = ((sel0 & in0) |
module cl_a1_aomux7_by2_2x (
assign out = ((sel0 & in0) |
module cl_a1_aomux8_12x (
assign out = ((sel0 & in0) |
module cl_a1_aomux8_16x (
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
assign out = ((sel0 & in0) |
module cl_a1_aomux8_by2_1x (
assign out = ((sel0 & in0) |
module cl_a1_aomux8_by2_2x (
assign out = ((sel0 & in0) |
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
wire l1en = (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se;
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
wire l1en = (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se;
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
wire l1en = (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se;
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
wire l1en = (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se;
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
wire l1en = (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se;
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
wire l1en = (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se;
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
wire l1en = (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se;
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
wire l1en = (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se;
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_a1_msffmin_16x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffmin_8x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffmin_4x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffmin_32x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffmin_1x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msff_lp_4x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msff_16x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msff_1x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msff_32x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msff_4x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msff_8x ( q, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msff_syrst_1x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_a1_msff_syrst_4x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_a1_msff_syrst_8x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_a1_msff_syrst_16x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_a1_msff_syrst_32x ( q, so, d, l1clk, si, siclk, soclk,reset );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or d ) // vcs optimized code
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && !siclk) q <= l1; // Load slave with master data
else if ( l1clk && siclk) begin // Conflict between data and scan
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= (d&reset);
module cl_a1_msffi_16x ( q_l, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffi_1x ( q_l, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffi_32x ( q_l, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffi_4x ( q_l, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffi_8x ( q_l, so, d, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(posedge l1clk or posedge siclk ) begin
q <= 1'b0; //pseudo flush reset
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
assign siclk_unused = siclk;
assign soclk_unused = soclk;
if (!siclk && !soclk) q <= d;
module cl_a1_msffjtag_4x ( q, so, d, l1clk, si, siclk, soclk, reset, updateclk );
wire l1clk, siclk, soclk, updateclk;
always @(l1clk or siclk or soclk or d or si or reset)
if (!l1clk && !siclk) l1 <= d; // Load master with data
else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush
else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan
if ( l1clk && !siclk && !soclk && !reset) so <= l1; // Load slave with master data
if ( l1clk && siclk && !soclk && !reset) so <= si; // Flush
always@(updateclk or reset or l1)
else if(updateclk) q <=l1;
module cl_a1_clksyncff_4x(l1clk, d, si, siclk, soclk, q, so);
input l1clk, d, si, siclk, soclk;
cl_a1_msff_4x xx0 ( .l1clk(l1clk), .d(d), .si(si), .siclk(siclk), .soclk(soclk), .q(q1o), .so(slo));
cl_a1_msff_4x xx1 ( .l1clk(l1clk), .d(q1o), .si(slo), .siclk(siclk), .soclk(soclk), .q(q), .so(so));
module cl_a1_bs_cell2_4x(q, so, d, l1clk, si, siclk, soclk, updateclk, mode,
input updateclk, mode, muxd;
wire l1clk, siclk, soclk, updateclk;
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) l1 <= d;
if ( l1clk && siclk) l1 <= si;
if (!l1clk && siclk) l1 <= 1'bx;
if ( l1clk && !soclk) so <= l1;
if ( l1clk && siclk && !soclk) so <= si; // Flush
always@(mode or muxd or qm or highz_n)
if(mode==0) q=(qm && highz_n);
module cl_a1_clk_buf_16x (
module cl_a1_clk_buf_20x (
module cl_a1_clk_buf_24x (
module cl_a1_clk_buf_32x (
module cl_a1_clk_buf_48x (
module cl_a1_clk_buf_64x (
module cl_a1_clk_buf_8x (
module cl_a1_clk_inv_16x (
module cl_a1_clk_inv_20x (
//assign clkout = ~clkin;
module cl_a1_clk_inv_24x (
module cl_a1_clk_inv_32x (
module cl_a1_clk_inv_48x (
module cl_a1_clk_inv_64x (
module cl_a1_clk_inv_8x (
//assign clkout = ~clkin;
module cl_a1_clk_mux2_16x (
always @ ( sel0 or in0 or in1)
module cl_a1_clk_mux2_24x (
always @ ( sel0 or in0 or in1)
module cl_a1_clk_mux2_32x (
always @ ( sel0 or in0 or in1)
module cl_a1_clk_mux2_8x (
always @ ( sel0 or in0 or in1)
// --------------------------------------------------
// File: cl_a1_aoi12_12x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Thursday Nov 29,2001 at 11:51:25 AM PST
// --------------------------------------------------
assign out = ~(( in10 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_a1_aoi12_16x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Thursday Nov 29,2001 at 11:51:25 AM PST
// --------------------------------------------------
assign out = ~(( in10 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_a1_aoi12_1x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Thursday Dec 6,2001 at 02:09:00 PM PST
// --------------------------------------------------
assign out = ~(( in10 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_a1_aoi12_2x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Thursday Nov 29,2001 at 11:51:25 AM PST
// --------------------------------------------------
assign out = ~(( in10 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_a1_aoi12_4x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Thursday Nov 29,2001 at 11:51:25 AM PST
// --------------------------------------------------
assign out = ~(( in10 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_a1_aoi12_8x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Thursday Nov 29,2001 at 11:51:25 AM PST
// --------------------------------------------------
assign out = ~(( in10 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_a1_aoi21_12x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:15 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 ));
// --------------------------------------------------
// File: cl_a1_aoi21_16x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:15 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 ));
// --------------------------------------------------
// File: cl_a1_aoi21_1x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:15 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 ));
// --------------------------------------------------
// File: cl_a1_aoi21_2x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:15 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 ));
// --------------------------------------------------
// File: cl_a1_aoi21_4x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:15 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 ));
// --------------------------------------------------
// File: cl_a1_aoi21_8x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:15 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 ));
// --------------------------------------------------
// File: cl_a1_aoi22_12x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:16 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_a1_aoi22_1x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:32 PM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_a1_aoi22_2x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:16 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_a1_aoi22_4x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:16 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_a1_aoi22_8x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:16 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_a1_aoi33_1x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Thursday Dec 6,2001 at 02:09:02 PM PST
// --------------------------------------------------
assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 ));
// --------------------------------------------------
// File: cl_a1_aoi33_2x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:18 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 ));
// --------------------------------------------------
// File: cl_a1_aoi33_4x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:18 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 ));
// --------------------------------------------------
// File: cl_a1_aoi33_8x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:18 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 ));
module cl_a1_rep_dcp2x_32x (
module cl_a1_rep_dcp2x_16x (
module cl_a1_rep_dcp2x_24x (
module cl_a1_rep_dcp2x_40x (
module cl_a1_rep_dcp2x_48x (
module cl_a1_rep_dcp_32x (
module cl_a1_rep_dcp_16x (
module cl_a1_rep_dcp_24x (
module cl_a1_rep_dcp_40x (
module cl_a1_rep_dcp_48x (
module cl_a1_rep_dcp50k_48x (
module cl_a1_rep_dcp50k_32x (
module cl_a1_rep_dcp50k_40x (
module cl_a1_bufmin_16x (
module cl_a1_bufmin_32x (
assign carry = (in0 & in1) | (in0 & in2) | (in1 & in2);
assign sum = (in0 ^ in1 ^ in2);
assign carry = (in0 & in1) | (in0 & in2) | (in1 & in2);
assign sum = (in0 ^ in1 ^ in2);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1 & in2);
assign out = ~(in0 & in1 & in2);
assign out = ~(in0 & in1 & in2);
assign out = ~(in0 & in1 & in2);
assign out = ~(in0 & in1 & in2);
assign out = ~(in0 & in1 & in2);
assign out = ~(in0 & in1 & in2);
assign out = ~(in0 & in1 & in2);
assign out = ~(in0 & in1 & in2);
assign out = ~(in0 & in1 & in2 & in3);
assign out = ~(in0 & in1 & in2 & in3);
assign out = ~(in0 & in1 & in2 & in3);
assign out = ~(in0 & in1 & in2 & in3);
assign out = ~(in0 & in1 & in2 & in3);
assign out = ~(in0 & in1 & in2 & in3);
assign out = ~(in0 & in1 & in2 & in3);
assign out = ~(in0 | in1);
assign out = ~(in0 | in1);
assign out = ~(in0 | in1);
assign out = ~(in0 | in1);
assign out = ~(in0 | in1);
assign out = ~(in0 | in1);
assign out = ~(in0 | in1);
assign out = ~(in0 | in1 | in2);
assign out = ~(in0 | in1 | in2);
assign out = ~(in0 | in1 | in2);
// --------------------------------------------------
// File: cl_a1_oai12_12x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:34 PM PDT
// --------------------------------------------------
assign out = ~(( in10 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_a1_oai12_16x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:34 PM PDT
// --------------------------------------------------
assign out = ~(( in10 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_a1_oai12_1x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:34 PM PDT
// --------------------------------------------------
assign out = ~(( in10 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_a1_oai12_2x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:34 PM PDT
// --------------------------------------------------
assign out = ~(( in10 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_a1_oai12_4x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:34 PM PDT
// --------------------------------------------------
assign out = ~(( in10 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_a1_oai12_8x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:34 PM PDT
// --------------------------------------------------
assign out = ~(( in10 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_a1_oai21_12x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:35 PM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 ));
// --------------------------------------------------
// File: cl_a1_oai21_16x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:35 PM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 ));
// --------------------------------------------------
// File: cl_a1_oai21_1x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Friday Mar 15,2002 at 02:53:58 PM PST
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 ));
// --------------------------------------------------
// File: cl_a1_oai21_2x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:23 AM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 ));
// --------------------------------------------------
// File: cl_a1_oai21_4x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:23 AM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 ));
// --------------------------------------------------
// File: cl_a1_oai21_8x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:23 AM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 ));
// --------------------------------------------------
// File: cl_a1_oai22_12x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:35 PM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_a1_oai22_16x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:35 PM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_a1_oai22_1x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:35 PM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_a1_oai22_2x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:24 AM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_a1_oai22_4x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:24 AM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_a1_oai22_8x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:24 AM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 | in01 ));
assign out = ~(in0 ^ in1);
assign out = ~(in0 ^ in1);
assign out = ~(in0 ^ in1);
assign out = ~(in0 ^ in1);
assign out = ~(in0 ^ in1);
assign out = ~(in0 ^ in1);
assign out = ~(in0 ^ in1 ^ in2);
assign out = ~(in0 ^ in1 ^ in2);
assign out = ~(in0 ^ in1 ^ in2);
assign out = ~(in0 ^ in1 ^ in2);
assign out = ~(in0 ^ in1 ^ in2);
assign out = ~(in0 ^ in1 ^ in2);
assign out = in0 ^ in1 ^ in2;
assign out = in0 ^ in1 ^ in2;
assign out = in0 ^ in1 ^ in2;
assign out = in0 ^ in1 ^ in2;
assign out = in0 ^ in1 ^ in2;
assign out = in0 ^ in1 ^ in2;
module cl_a1_muxprotect_2x (
assign e0 = scan_en | d0;
assign e1= ~scan_en & d1;
assign e2= ~scan_en & d2;
assign e3= ~scan_en & d3;
assign {cout, out[63:0]} = ({1'b0, in0[63:0]} + {1'b0, in1[63:0]} + {{64{1'b0}}, cin});