// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: n2_clk_clstr_hdr1_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// ========== Copyright Header End ============================================
module n2_clk_clstr_hdr1_cust (
// *******************************
// *******************************
input ccu_cmp_slow_sync_en;
input ccu_slow_cmp_sync_en;
// *******************************
// *******************************
wire ccu_cmp_slow_sync_en;
wire ccu_slow_cmp_sync_en;
wire tcu_wr_inhibit; // to be made input
wire tcu_atpg_mode; // to be made input
wire array_wr_inhibit; // to be made output
// additional internal nets
// wire div_r_n; // vlint
// wire div_f_n; // vlint
// wire clk_stop_muxed; // vlint
// wire clk_stop_q; // vlint
// **********************************************************
// buffered & gated stuff
// **********************************************************
cl_u1_buf_1x aclk_buf ( .in( tcu_aclk ), .out ( aclk ) );
cl_u1_buf_1x bclk_buf ( .in( tcu_bclk ), .out ( bclk ) );
cl_u1_buf_1x pce_ov_buf ( .in( tcu_pce_ov ), .out ( pce_ov ) );
cl_u1_buf_1x wmr_protect_buf ( .in( rst_wmr_protect ), .out ( wmr_protect ) );
// assign aclk_gated = aclk & tcu_atpg_mode;
// assign bclk_gated = bclk & tcu_atpg_mode;
// assign scan_en_gated = scan_en & tcu_atpg_mode;
// implemented right here
cl_u1_nand2_1x aclk_gated_nand ( .in0 (aclk), .in1 (tcu_atpg_mode), .out (aclk_gated_n) );
cl_u1_nand2_1x bclk_gated_nand ( .in0 (bclk), .in1 (tcu_atpg_mode), .out (bclk_gated_n) );
cl_u1_nand2_1x scan_en_gated_nand ( .in0 (scan_en), .in1 (tcu_atpg_mode), .out (scan_en_gated_n) );
cl_u1_inv_1x aclk_gated_inv ( .in (aclk_gated_n), .out (aclk_gated) );
cl_u1_inv_1x bclk_gated_inv ( .in (bclk_gated_n), .out (bclk_gated) );
cl_u1_inv_1x scan_en_gated_inv ( .in (scan_en_gated_n), .out (scan_en_gated) );
// assign scan_out = tcu_atpg_mode ? scan_out_pre_mux : scan_in ;
// implemented below, and as instance "scan_chain_mux"
cl_u1_inv_1x tcu_atpg_mode_inv ( .in (tcu_atpg_mode) , .out (tcu_atpg_mode_n) );
// assign aclk_wmr = ~rst_wmr_protect & tcu_aclk;
cl_u1_inv_1x wmr_protect_inv ( .in (rst_wmr_protect) , .out (rst_wmr_protect_n) );
cl_u1_nand2_1x aclk_wmr_gate (
.in1 (rst_wmr_protect_n),
cl_u1_inv_1x aclk_wmr_inv ( .in (aclk_wmr_n) , .out (aclk_wmr) );
// cl_u1_inv_1x gclk_inv ( .in (gclk) , .out (gclk_n) ); // vlint
// **********************************************************
// **********************************************************
n2_clk_clstr_hdr1_l1hdr gclk_header (
.stop(1'b0) // ECO1.2 - not allowed to stop local clocks
n2_clk_clstr_hdr1_l1hdr l1_header (
.stop(1'b0) // ECO1.3 - false info; no action needed
// **********************************************************
// make observe flops part of scan chain (observe only)
// **********************************************************
n2_clk_clstr_hdr1_obs_flops observe_flops (
.tcu_clk_stop (tcu_clk_stop),
.ccu_div_ph (ccu_div_ph),
.array_wr_inhibit (array_wr_inhibit),
cl_sc1_aomux2_1x scan_chain_mux (
.sel1 ( tcu_atpg_mode_n ),
.in0 ( scan_out_pre_mux ),
// **********************************************************
// synchronize the control signals
// **********************************************************
n2_clk_clstr_hdr1_sync control_sig_sync (
.ccu_slow_cmp_sync_en ( ccu_slow_cmp_sync_en),
.ccu_cmp_slow_sync_en ( ccu_cmp_slow_sync_en),
.ccu_dr_sync_en ( ccu_dr_sync_en),
.ccu_io2x_sync_en ( ccu_io2x_sync_en),
.slow_cmp_sync_en ( slow_cmp_sync_en ),
.cmp_slow_sync_en ( cmp_slow_sync_en ),
.dr_sync_en ( dr_sync_en),
.io2x_sync_en ( io2x_sync_en),
.scan_out ( scan_out_pre_mux )
// **********************************************************
// **********************************************************
wire ccu_div_ph_flop_unused;
cl_sc1_msff_1x ccu_div_ph_flop (
.so (ccu_div_ph_flop_unused)
// div_r = sel1 (ie, ~div_en | tcu_div_bypass ) | div_ph
// div_f = sel0 (ie, div_en & ~tcu_div_bypass )
// sel0 = ~div_bypass & div_en // div_ph select
// sel1 = div_bypass | ~div_en // gclk select
cl_u1_inv_1x div_bypass_inv ( .in (tcu_div_bypass), .out (tcu_div_bypass_n) );
cl_u1_inv_1x cluster_div_inv ( .in (cluster_div_en), .out (cluster_div_en_n) );
// generate sel0 - div_ph sel
cl_u1_nand2_1x sel0_n_gen (
cl_u1_inv_1x sel0_gen ( .in (sel0_n), .out (sel0) );
// generate sel1 - gclk sel
cl_u1_nor2_1x sel2_n_gen (
cl_u1_inv_1x sel1_gen ( .in (sel1_n), .out (sel1) );
//cl_u1_nor2_1x div_r_gate (
cl_sc1_blatch_4x blatch_divr (
.latout(div_ph_blatch), .d(ccu_div_ph_ff), .l1clk (gclk),
.so (blatch_divr_unused), .si (1'b0), .siclk(1'b0), .soclk(1'b0) );
//cl_u1_nor2_1x div_r_gate (
cl_u1_buf_1x div_r_buf ( .in (div_ph_blatch), .out (div_r ) );
// creating the div_r_to_syncronizer to mimic generation of
cl_u1_nor2_1x div_r_sync_gen_nor (
cl_u1_inv_1x div_r_sync_gen_inv ( .in (div_r_sync_n), .out (div_r_sync) );
cl_sc1_aomux2_1x alatch_in (
cl_u1_nor2_1x nor_gclk_reset ( .in0 (sel1), .in1 (gclk), .out (gclk_reset_n));
cl_u1_inv_1x inv_gclk_reset ( .in (gclk_reset_n), .out (gclk_reset));
cl_sc1_alatch_4x alatch (
.q(div_out), .d(div_mux), .l1clk (gclk_reset),
.so (alatch_unused), .si (1'b0), .siclk(1'b0), .soclk(1'b0), .se(1'b0) );
cl_sc1_aomux2_1x final_mux (
// **********************************************************
// clkstop for l2clk (via control of cclk)
// **********************************************************
// 1. sync up clock stop (these are non-scanned)
n2_clk_clstr_hdr1_clk_stop_syncff clk_stop_syncff (
.synced ( clk_stop_synced ),
wire clk_stop_synced_stg1;
wire clk_stop_synced_stg2;
wire clk_stop_del_stg1_unused;
wire clk_stop_del_stg2_unused;
// 2. now delay sync'd up clock stop (these are non-scanned)
cl_sc1_msff_1x clk_stop_del_stg1 (
.d (clk_stop_synced), .q (clk_stop_synced_stg1), .l1clk (div_clk),
.siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg1_unused)
cl_sc1_msff_1x clk_stop_del_stg2 (
.d (clk_stop_synced_stg1), .q (clk_stop_synced_stg2), .l1clk (div_clk),
.siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg2_unused)
wire clk_stop_synced_stg2_gated;
wire clk_stop_synced_stg2_n;
cl_u1_inv_1x clk_stop_stg2_inv ( .in (clk_stop_synced_stg2), .out (clk_stop_synced_stg2_n) );
// ECO1.5 - pushed the gate after the latch in the clk-stop instance "clk_stopper"
// cl_u1_nor2_1x clk_stop_stg2_nor ( .in0 (clk_stop_synced_stg2_n), .in1 (tcu_atpg_mode), .out (clk_stop_synced_stg2_gated) );
// 3. use blatch & and-gate for controlling clock
n2_clk_clstr_hdr1_clkgate clk_stopper (
.atpg_mode(tcu_atpg_mode),
.clken(clk_stop_synced_stg2_n)
// 4. finally gate-off with async reset
// assign cclk = pre_cclk & cluster_arst_l;
cl_u1_nand2_1x cclk_nand ( .in0 (pre_cclk), .in1 (cluster_arst_l), .out (cclk_n) );
cl_u1_inv_1x cclk_inv ( .in (cclk_n), .out (cclk) ); // cclk_tmp
// assign cclk = cclk_tmp | scan_en;
// **********************************************************
// array write inhibit operation
// **********************************************************
wire clk_stop_synced_stg3;
wire clk_stop_synced_stg4;
wire clk_stop_synced_stg5;
wire array_wr_inhibit1_n;
wire array_wr_inhibit2_n;
wire clk_stop_del_stg3_unused;
wire clk_stop_del_stg4_unused;
wire clk_stop_del_stg5_unused;
cl_sc1_msff_1x clk_stop_del_stg3 (
.d (clk_stop_synced_stg2), .q (clk_stop_synced_stg3), .l1clk (div_clk),
.siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg3_unused)
cl_sc1_msff_1x clk_stop_del_stg4 (
.d (clk_stop_synced_stg3), .q (clk_stop_synced_stg4), .l1clk (div_clk),
.siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg4_unused)
cl_sc1_msff_1x clk_stop_del_stg5 (
.d (clk_stop_synced_stg4), .q (clk_stop_synced_stg5), .l1clk (div_clk),
.siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg5_unused)
// assign array_wr_inhibit1 = clk_stop_synced & clk_stop_synced_stg5;
cl_u1_nand3_1x clk_stop_and_delayed ( // ECO1.4 - changed cl_u1_nand2_1x
.in1 (clk_stop_synced_stg5),
.out (array_wr_inhibit1_n)
cl_u1_inv_1x array_wr_inhibit1_inv ( .in(array_wr_inhibit1_n), .out(array_wr_inhibit1) );
// assign array_wr_inhibit2 = (~clk_stop_synced) & wr_inhibit_q2;
cl_u1_inv_1x clk_stop_synced_inv ( .in(clk_stop_synced), .out(clk_stop_synced_n) );
// ECO1.1 - removed nand gate from path of tcu_wr_inhibit
// and replaced with buffer
// cl_u1_nand2_1x clk_stop_synced_and_wr_inhibit_q2 (
// .in0 (clk_stop_synced_n),
// .in1 (tcu_wr_inhibit), // (wr_inhibit_q2),
// .out (array_wr_inhibit2_n)
// cl_u1_inv_1x array_wr_inhibit2_inv ( .in(array_wr_inhibit2_n), .out(array_wr_inhibit2) );
cl_u1_buf_1x array_wr_inhibit2_buf ( .in(tcu_wr_inhibit), .out(array_wr_inhibit2) );
// assign array_wr_inhibit = array_wr_inhibit1 | array_wr_inhibit2 | (~cluster_arst_l);
cl_u1_inv_1x cluster_arst_inv (.in (cluster_arst_l), .out (cluster_arst));
cl_u1_nor3_1x array_wr_inhibit_nor (
.in0 (array_wr_inhibit1),
.in1 (array_wr_inhibit2),
.out (array_wr_inhibit_n)
cl_u1_inv_1x array_wr_inhibit_inv (.in (array_wr_inhibit_n), .out (array_wr_inhibit));
endmodule // n2_clk_clstr_hdr1_cust
// **********************************************************
// (fictitous) observe flop module for ATPG purposes
// **********************************************************
module n2_clk_clstr_hdr1_obs_flops (
endmodule // n2_clk_clstr_hdr1_obs_flops
// **********************************************************
// (fictitous) synchronizer module for ATPG purposes
// **********************************************************
module n2_clk_clstr_hdr1_sync (
input ccu_slow_cmp_sync_en ;
input ccu_cmp_slow_sync_en ;
// wire div_r_n; // vlint
wire ccu_slow_cmp_sync_en ;
wire ccu_cmp_slow_sync_en ;
n2_clk_clstr_hdr1_sync_ff slow_cmp_sync_en_syncff (
.din ( ccu_slow_cmp_sync_en ),
.synced ( slow_cmp_sync_en ),
n2_clk_clstr_hdr1_sync_ff cmp_slow_sync_en_syncff (
.din ( ccu_cmp_slow_sync_en ),
.synced ( cmp_slow_sync_en ),
n2_clk_clstr_hdr1_sync_ff por_syncff (
n2_clk_clstr_hdr1_sync_ff wmr_syncff (
n2_clk_clstr_hdr1_sync_ff dr_sync_en_syncff (
n2_clk_clstr_hdr1_sync_ff io2x_sync_en_syncff (
.din ( ccu_io2x_sync_en ),
.synced ( io2x_sync_en ),
endmodule // n2_clk_clstr_hdr1_sync
// **********************************************************
// (fictitous) 1-bit synchronizer for ATPG purposes
// **********************************************************
module n2_clk_clstr_hdr1_sync_ff (
cl_u1_inv_1x sel_inv ( .in ( sel ), .out ( sel_n ) );
cl_sc1_aomux2_1x sync_mux1 (
cl_sc1_msff_1x din_stg1 (
cl_sc1_msff_1x din_stg2 (
endmodule // n2_clk_clstr_hdr1_sync_ff
// **********************************************************
// (fictitous) module for clock stop sync.
// **********************************************************
module n2_clk_clstr_hdr1_clk_stop_syncff (
cl_u1_inv_1x sel_inv ( .in(sel), .out(sel_n) );
cl_sc1_aomux2_1x sync_mux1 (
.sel0 ( sel_n ), .sel1 ( sel ),
.in0 ( din_q1 ), .in1 ( din ),
cl_sc1_msff_1x din_stg1 (
.d ( din_muxed ), .l1clk ( clkin ), .q ( din_q1 ),
.si ( 1'b0 ), .siclk ( 1'b0 ), .soclk ( 1'b0 ),
cl_sc1_blatch_4x blatch (
.latout(din_q1_lat), .d(din_q1), .l1clk (clkin),
.so (so_unused[1]), .si (1'b0), .siclk(1'b0), .soclk(1'b0) );
cl_sc1_msff_1x din_stg2 (
.d ( din_q1_lat ), .l1clk ( sync_clk ), .q ( synced ),
.siclk ( 1'b0 ), .soclk ( 1'b0 ), .si ( 1'b0 ), .so (so_unused[2] ) );
endmodule // n2_clk_clstr_hdr1_clk_stop_sync_ff
module n2_clk_clstr_hdr1_clkgate (
input clken; // clken, active high
input l2clk; // level 2 clock, from clock grid
wire atpg_mode, clken, l2clk, l1clk;
cl_sc1_blatch_4x blatch (
.latout(clken_lat), .d(clken), .l1clk (l2clk),
.so (so_unused), .si (1'b0), .siclk(1'b0), .soclk(1'b0) );
cl_u1_nor2_1x clken_nor ( .in0(clken_lat), .in1(atpg_mode), .out(clken_gated_n) );
cl_u1_inv_1x clken_gated_inv ( .in(clken_gated_n), .out(clken_gated) );
cl_u1_nand2_1x clk_nand ( .in0(clken_gated), .in1(l2clk), .out(l1clk_n) );
cl_u1_inv_1x clk_inv ( .in(l1clk_n), .out(l1clk) );
endmodule // n2_clk_clstr_hdr1_clkgate
module n2_clk_clstr_hdr1_l1hdr (
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
always @ (l2clk or stop or pce or pce_ov ) begin // vlint fix - latch model
l1en = (~stop & ( pce | pce_ov )); // vlint fix - replaced w/blocking
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
endmodule // n2_clk_clstr_hdr1_l1hdr