verif/diag/8core.diaglist

///////////////////////////////////////////////////////////////////////////////
//
//  Description:  DIAGS for Tester -
//                      DTM diags that run on all 8 cores.
//
//
///////////////////////////////////////////////////////////////////////////////

<8core_diags name=8core_diags>
<sys(8core_diags)>

<runargs -vcs_run_args=+EIGHT_CORE_DTM2_TESTER>

//  Description:  DIAGS for Tester -
//                      Diags which are eight cores and
//                      uses default memory config
//
//

// Always run with TSO_CHECKER enabled
<runargs -sas_run_args=-DTSO_CHECKER>

//---MPGen diags {{{
<runargs -vcs_run_args=+finish_mask=all -midas_args=-DCMP_THREAD_START=ALL -midas_args=-allow_tsb_conflicts>

<8core_mpgen_dynamic_caches>
mpgen_dynamic_caches_2  mpgen_dynamic_caches_2.s
mpgen_dynamic_caches_4  mpgen_dynamic_caches_4.s
mpgen_dynamic_caches_5  mpgen_dynamic_caches_5.s
</8core_mpgen_dynamic_caches>

<8core_mpgen_dynamic_pwr_mgmt>
mpgen_dynamic_pwr_mgmt   mpgen_dynamic_pwr_mgmt.s
mpgen_dynamic_pwr_mgmt_2 mpgen_dynamic_pwr_mgmt_2.s
mpgen_dynamic_pwr_mgmt_3 mpgen_dynamic_pwr_mgmt_3.s
mpgen_dynamic_pwr_mgmt_4 mpgen_dynamic_pwr_mgmt_4.s
</8core_mpgen_dynamic_pwr_mgmt>

<8core_mpgen_tso_all_banks>
mpgen_tso_all_banks_2   mpgen_tso_all_banks_2.s
mpgen_tso_all_banks_3   mpgen_tso_all_banks_3.s
mpgen_tso_all_banks_4   mpgen_tso_all_banks_4.s
mpgen_tso_all_banks_5   mpgen_tso_all_banks_5.s
</8core_mpgen_tso_all_banks>

<8core_mpgen_tso_atomic_all_banks>
mpgen_tso_atomic_all_banks_2  mpgen_tso_atomic_all_banks_2.s
mpgen_tso_atomic_all_banks_3  mpgen_tso_atomic_all_banks_3.s
mpgen_tso_atomic_all_banks_4  mpgen_tso_atomic_all_banks_4.s
mpgen_tso_atomic_all_banks_5  mpgen_tso_atomic_all_banks_5.s
</8core_mpgen_tso_atomic_all_banks>

<8core_mpgen_tso_atomic_asi_one_bank>
mpgen_tso_atomic_asi_one_bank_3  mpgen_tso_atomic_asi_one_bank_3.s
mpgen_tso_atomic_asi_one_bank_4  mpgen_tso_atomic_asi_one_bank_4.s
mpgen_tso_atomic_asi_one_bank_5  mpgen_tso_atomic_asi_one_bank_5.s
</8core_mpgen_tso_atomic_asi_one_bank>

<8core_mpgen_tso_atomic_one_bank>
mpgen_tso_atomic_one_bank       mpgen_tso_atomic_one_bank.s
mpgen_tso_atomic_one_bank_2     mpgen_tso_atomic_one_bank_2.s
mpgen_tso_atomic_one_bank_3     mpgen_tso_atomic_one_bank_3.s
mpgen_tso_atomic_one_bank_4     mpgen_tso_atomic_one_bank_4.s
mpgen_tso_atomic_one_bank_5     mpgen_tso_atomic_one_bank_5.s
</8core_mpgen_tso_atomic_one_bank>

<8core_mpgen_tso_ba_all_banks>
mpgen_tso_ba_all_banks    mpgen_tso_ba_all_banks.s
mpgen_tso_ba_all_banks_2  mpgen_tso_ba_all_banks_2.s
mpgen_tso_ba_all_banks_3  mpgen_tso_ba_all_banks_3.s
mpgen_tso_ba_all_banks_4  mpgen_tso_ba_all_banks_4.s
mpgen_tso_ba_all_banks_5  mpgen_tso_ba_all_banks_5.s
</8core_mpgen_tso_ba_all_banks>

<8core_mpgen_tso_ba_one_bank>
mpgen_tso_ba_one_bank_3  mpgen_tso_ba_one_bank_3.s
mpgen_tso_ba_one_bank_4  mpgen_tso_ba_one_bank_4.s
mpgen_tso_ba_one_bank_5  mpgen_tso_ba_one_bank_5.s
</8core_mpgen_tso_ba_one_bank>

<8core_mpgen_tso_one_bank>
mpgen_tso_one_bank      mpgen_tso_one_bank.s
mpgen_tso_one_bank_3    mpgen_tso_one_bank_3.s
mpgen_tso_one_bank_4    mpgen_tso_one_bank_4.s
mpgen_tso_one_bank_5    mpgen_tso_one_bank_5.s
</8core_mpgen_tso_one_bank>


</runargs>
//---MPGen diags }}}

</runargs>

<8core_ncu>

<runargs -midas_args=-DCMP_THREAD_START=0x1  -finish_mask=1 -midas_args=-DTHREAD_COUNT=1 -midas_args=-DPART_0_BASE=0x200000000 -nosas -nofast_boot >
interrupt_int_vec_dis                   interrupt_INT_VEC_DIS.s
interrupt_pci_spurious_err              interrupt_pci_spurious_err.s
interrupt_queue_cpu_mondo_mode          interrupt_QUEUE_CPU_MONDO_mode.s
interrupt_queue_cpu_mondo_trap          interrupt_QUEUE_CPU_MONDO_trap.s
interrupt_queue_dev_mondo_mode          interrupt_QUEUE_DEV_MONDO_mode.s
interrupt_queue_dev_mondo_trap          interrupt_QUEUE_DEV_MONDO_trap.s
interrupt_swvr_intr_r                   interrupt_SWVR_INTR_R.s
</runargs>

<runargs -midas_args=-DCMP_THREAD_START=0x3  -finish_mask=3 -midas_args=-DSYNC_THREADS=0x3 -midas_args=-DPART_0_BASE=0x200000000 -nosas -nofast_boot >
<8core_ncu_subset>
interrupt_swvr_intr_r_mode      interrupt_SWVR_INTR_R_mode.s
interrupt_swvr_intr_rec_mode   interrupt_SWVR_INTR_REC_mode.s
interrupt_swvr_intr_w_mode      interrupt_SWVR_INTR_W_mode.s
</8core_ncu_subset>
</runargs>

<runargs -midas_args=-DCMP_THREAD_START=0x1      -midas_args=-DPART_0_BASE=0x200000000 -nosas -nofast_boot >
n2_cmp_upk_pk_upk               n2_cmp_upk_pk_upk.s             -finish_mask=3
</runargs>

<runargs -midas_args=-DCMP_THREAD_START=0x1  -midas_args=-DPART_0_BASE=0x200000000 -nosas -nofast_boot >
ncu_1core_wakup    ncu_1core_wakup.s   -finish_mask=0x2b
</runargs>

</8core_ncu>

</runargs> // EIGHT_CORE_DTM2_TESTER

</sys(8core_diags)>
</8core_diags>