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* OpenSPARC T2 Processor File: n2_err_L2_LVF_uecc_WrmRst.s
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#define MAIN_PAGE_HV_ALSO
#define L2_ENTRY_PA 0x517590000
#define TEST_DATA 0x555555555555555
#define L2_ES_W1C_VALUE 0xc03ffff800000000
! Boot code does not provide TLB translation for IO address space
! Check if Warm Reset is done, or first time entering diag
setx warm_reset_done, %g1, %g2
brnz %g3, Warm_Reset_Complt
! First time thru, Store a non-zero value there
setx L2_ES_W1C_VALUE, %l0, %g4
! Now access L2 control and status registers
ldxa [%g0] ASI_LSU_CONTROL, %l0
! Remove the lower 2 bits (I-Cache and D-Cache enables)
stxa %l0, [%g0] ASI_LSU_CONTROL
! Write 1 to clear L2 Error status registers
set_L2_Directly_Mapped_Mode:
setx 0x22000000, %l0, %g1
! Generate L2 VD Diag read address
! Addressing: [39:32] See PRM, [22] 1 for V/D, [17:8] set, [7:6] bank, [2:0] = 0
setx 0x3ffc0, %l0, %l2 ! Mask for extracting [17:6]
sllx %l0, 32, %l0 ! Bits [39:32]
sllx %l0, 22, %l0 ! Bit [22]
setx 0x22000000, %l0, %g1
setx 0x22000000, %l1, %g2
ldxa [%g0] ASI_LSU_CONTROL, %l0
stxa %l0, [%g0] ASI_LSU_CONTROL
! Compute expected value of L2 error status register
sllx %l1, L2ES_VEU, %l3 ! VEC bit
setx 0xfc00000000, %l5,%g2
ldx [%l3], %l4 ! Error address is the physical address of the cache line (PA[5:0] 0)
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