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* OpenSPARC T2 Processor File: n2_err_dram_DAC_st_trap.s
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#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
#define DRAM_ERR_INJ_REG 0x8400000290
#define DRAM_ERR_STAT_REG 0x8400000280
#define L2_ERR_STAT_REG 0xAB00000000
#define L2_ERR_ADDR_REG 0xAC00000000
#define ERROR_ADDR 0x20200000
#define TEST_DATA0 0x1000100081c3e008
#define TEST_DATA1 0x2000200081c3e008
#define TEST_DATA2 0x3000300081c3e008
#define L2_ES_W1C_VALUE 0xc03ffff800000000
#define DRAM_ES_W1C_VALUE 0xfe00000000000000
!.global My_Recoverable_Sw_error_trap
.global My_Corrected_ECC_error_trap
ldxa [%g0] ASI_LSU_CONTROL, %l0
! Remove the lower 2 bits (I-Cache and D-Cache enables)
stxa %l0, [%g0] ASI_LSU_CONTROL
! Clear DRAM Error status register (Bit[63:57] write-1-clear)
setx DRAM_ES_W1C_VALUE, %l0, %g4
setx DRAM_ERR_STAT_REG, %l3, %g5
set_DRAM_error_inject_ch0:
mov 0x2, %l1 ! ECC Mask (1-bit error)
sllx %l2, DRAM_EI_SSHOT, %l3
Or %l1, %l3, %l1 ! Set single shot ;
sllx %l2, DRAM_EI_ENB, %l3
or %l1, %l3, %l1 ! Enable error injection for the next write
setx DRAM_ERR_INJ_REG, %l3, %g6
! Write 1 to clear L2 Error status registers
setx TEST_DATA1, %l0, %g5
set_L2_Directly_Mapped_Mode:
setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way
! Storing to same L2 way0 but different tag,this will write to mcu
setx 0x2100aa00, %l0, %g3 ! bits [21:18] select way
setx DRAM_ERR_STAT_REG, %l3, %g5
sllx %l1, DRAM_ES_DAC, %l0
set 0x0002, %l3 ! 16-bit Syndrome - for SECC, it's the mask nibble-reversed
or %l0, %l3, %l0 ! %l0 has expected value
setx L2_ERR_STAT_REG, %l3, %g5
setx 0xfffffffff0000000, %l3, %l0
andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits
! Error address is the physical address of the cache line
setx 0x2200aa00, %l0, %l1 ! bits [21:18] select way
setx 0xffffffffc0, %l0,%o2
! Check if a Hardware Corrected Error Trap happened
mov TT_Corrected_ECC, %l0
My_Corrected_ECC_error_trap:
!My_Recoverable_Sw_error_trap:
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