* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: ncu_xir_allth.s
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* ========== Copyright Header End ============================================
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
#define My_External_Reset setx 0x200005000,%g7,%g1;add %g1,%o1,%g1;set 0x1,%g2;stb %g2,[%g1];done;
! Check that asi_xir_steering is correct
setx 0xffffffffffffffff,%g7,%g1
stxa %g1,[ASI_CMP_CORE_RUNNING_RW]%asi
! Wait for threads to finish boot
setx 0x8900000808,%g7,%g1
/******************************************************
*******************************************************/
setx 0x0000000000000fff,%g7,%l1
/******************************************************
*******************************************************/
SECTION my_xir_trap_handler DATA_VA=0x200005000
Name = my_xir_trap_handler,