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* OpenSPARC T2 Processor File: interrupt_QUEUE_CPU_MONDO_trap.s
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* ========== Copyright Header End ============================================
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
#define H_T0_Cpu_Mondo_Trap_0x7c
#define My_T0_Cpu_Mondo_Trap_0x7c \
call my_Cpu_Mondo_trap; \
#define H_HT0_DAE_invalid_asi_0x14 my_H_T0_DAE_invalid_asi_0x14
/************************************************************************
************************************************************************/
! Switch to Hypervisor mode.
! Enable interrupts in the Pstate reg.
! Initialize the queue head and tail pointers to same location.
setx queue_start, %g1, %g2
stxa %g2, [%g0 + ASI_CPU_MONDO_QUEUE_HEAD]%asi
stxa %g2, [%g0 + ASI_CPU_MONDO_QUEUE_TAIL]%asi
! Switch to supervisor mode.
! Change the queue head != queue tail to generate trap
stxa %g2, [%g0 + ASI_CPU_MONDO_QUEUE_HEAD]%asi
setx 400, %g1, %g7 ! g7 = timeout count
setx cpu_mondo_trap_count, %g1, %g3
! Change queue head == queue tail, no trap expected
setx queue_start, %g1, %g2
stxa %g2, [%g0 + ASI_CPU_MONDO_QUEUE_HEAD]%asi
! Try to write queue tail register, expect a
stxa %g2, [%g0 + ASI_CPU_MONDO_QUEUE_TAIL]%asi
! Switch to Hypervisor mode.
! Change queue tail != queue head, no trap expected.
stxa %g2, [%g0 + ASI_CPU_MONDO_QUEUE_TAIL]%asi
setx 100, %g1, %g7 ! Loop count
! Go back to privileged mode, trap should occur now.
setx 400, %g1, %g7 ! Loop count
brz %g7, check_trap_counts
! Check for expected number of traps.
setx cpu_mondo_trap_count, %g1, %g3
setx dae_invalid_trap_count, %g1, %g3
/**********************************************************************
**********************************************************************/
.global my_Cpu_Mondo_trap
.global my_H_T0_DAE_invalid_asi_0x14
setx cpu_mondo_trap_count, %g6, %g7
ldxa [%g0 + ASI_CPU_MONDO_QUEUE_TAIL]%asi, %g2
stxa %g2, [%g0 + ASI_CPU_MONDO_QUEUE_HEAD]%asi
my_H_T0_DAE_invalid_asi_0x14:
setx dae_invalid_trap_count, %g6, %g7
/************************************************************************
************************************************************************/