* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: memop_mt_l2_miss_buff.s
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* ========== Copyright Header End ============================================
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
/************************************************************************
************************************************************************/
! Initialize the global registers.
setx user_data_start, %g1, %g3
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
! Sync up all the treads.
SYNC_THREAD_MAIN( test_failed, %g1, %g2, %g3 )
! Do 8 loads that use the same L2 cache line.
setx 0x40000, %g1, %g2 ! Set up the load addresses
add %l7, %g2, %l6 ! All alias to same L2$ line
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
! All Treads, except 0, Start Here
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
! Sync up all the treads.
SYNC_THREAD_OTHER( %l6,%g1,%g2 )
setx 0x40000, %g1, %g2 ! Set up the load addresses
add %l7, %g2, %l6 ! All alias to same L2$ line
/**********************************************************************
*********************************************************************/
/************************************************************************
************************************************************************/
SECTION .DATA DATA_VA=0x70000000