* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: tso_n1_evict_fanout_dc2_8c.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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* it under the terms of the GNU General Public License as published by
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* ========== Copyright Header End ============================================
#define MAIN_BASE_DATA_ADDR 0x160000
#define MAIN_BASE_TEXT_ADDR 0x150000
#define MAIN_BASE_DATA_ADDR_RA 0x100160000
#define MAIN_BASE_TEXT_ADDR_RA 0x100150000
#define DATA2_BASE_DATA_ADDR 0x960000
#define DATA2_BASE_DATA_ADDR_RA 0x100960000
#define USER_PAGE_CUSTOM_MAP
#define data_base_reg1 %o1
#define data_base_reg2 %o2
SECTION .MAIN TEXT_VA=0x150000, DATA_VA=0x160000
RA=MAIN_BASE_TEXT_ADDR_RA,
PA=ra2pa(MAIN_BASE_TEXT_ADDR_RA,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_NFO=0,
TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
RA=MAIN_BASE_DATA_ADDR_RA,
PA=ra2pa(MAIN_BASE_DATA_ADDR_RA,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_NFO=0,
TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1
set ITERATIONS, counter_reg
add my_id_reg, 0x00, my_id_reg ! ID address
add my_id_reg, 0x04, my_id_reg
add my_id_reg, 0x08, my_id_reg
add my_id_reg, 0x0c, my_id_reg
add my_id_reg, 0x10, my_id_reg
add my_id_reg, 0x14, my_id_reg
add my_id_reg, 0x18, my_id_reg
add my_id_reg, 0x1c, my_id_reg
add my_id_reg, 0x20, my_id_reg
add my_id_reg, 0x24, my_id_reg
add my_id_reg, 0x28, my_id_reg
add my_id_reg, 0x2c, my_id_reg
add my_id_reg, 0x30, my_id_reg
add my_id_reg, 0x34, my_id_reg
add my_id_reg, 0x38, my_id_reg
add my_id_reg, 0x3c, my_id_reg
add my_id_reg, 0x40, my_id_reg
add my_id_reg, 0x44, my_id_reg
add my_id_reg, 0x48, my_id_reg
add my_id_reg, 0x4c, my_id_reg
add my_id_reg, 0x50, my_id_reg
add my_id_reg, 0x54, my_id_reg
add my_id_reg, 0x58, my_id_reg
add my_id_reg, 0x5c, my_id_reg
add my_id_reg, 0x60, my_id_reg
add my_id_reg, 0x64, my_id_reg
add my_id_reg, 0x68, my_id_reg
add my_id_reg, 0x6c, my_id_reg
add my_id_reg, 0x70, my_id_reg
add my_id_reg, 0x74, my_id_reg
add my_id_reg, 0x78, my_id_reg
add my_id_reg, 0x7c, my_id_reg
setx protected_area, %l0, data_base_reg1 ! the data area
setx protected_area2,%l0, data_base_reg2 ! the data area2
ld [data_base_reg1], test_reg ! read the data area
ld [data_base_reg1 + 0x10], test_reg ! read the data area
ld [data_base_reg1 + 0x20], test_reg ! read the data area
ld [data_base_reg1 + 0x30], test_reg ! read the data area
ld [data_base_reg1 + 0x20], test_reg ! read the data area
ld [data_base_reg1 + 0x30], test_reg ! read the data area
ld [data_base_reg1 + 0x30], test_reg ! read the data area
brz counter_reg, good_end
ld [data_base_reg2], test_reg ! read the data area2
setx barrier_data, tmp1, tmp2
prefetch [tmp2], #n_reads
brz tmp3, bout2 ! somebody already reset the barrier
sub tmp3, THREAD_COUNT, tmp3 ! subtract THREAD_COUNT
brnz tmp3, bloop2 ! wait if 0 we are out. Otherwise loop more.
prefetch [tmp2], #n_reads
st %g0, [tmp2 + 4] ! clear the barrier counter
!==========================
SECTION .DATA2 DATA_VA=0x960000
RA=DATA2_BASE_DATA_ADDR_RA,
PA=ra2pa(DATA2_BASE_DATA_ADDR_RA,0),
part_0_ctx_nonzero_tsb_config_0,
TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_NFO=0,
TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=1, TTE_CV=1, TTE_E=0, TTE_P=0, TTE_W=1