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* OpenSPARC T2 Processor File: tso_n1_indirection1.s
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* ========== Copyright Header End ============================================
#define global_cnt_reg %i4
setx addrA, tmp0, addrA_reg
setx addrB, tmp0, addrB_reg
setx addrC, tmp0, addrC_reg
setx result0, tmp0, result0_reg
setx result1, tmp0, result1_reg
setx ready0, tmp0, ready0_reg
setx ready1, tmp0, ready1_reg
setx finish_area, tmp0, finish_reg
set ITERATIONS, global_cnt_reg
!=====================================================
st tmp2, [addrB_reg] ! store non-zero to B
brz global_cnt_reg, good_end
!=========================================================
loop10: ! wait for B to be non-zero
st test_reg, [addrC_reg] ! store non-zero to C
brz global_cnt_reg, good_end
!=========================================================
ld [addrC_reg], test_reg ! load C until set
ld [addrA_reg], tmp1 ! check A
st %g0, [addrC_reg] ! clear
brz global_cnt_reg, good_end
!=x========================================================================
! all threads synchronize at this point.
setx barrier_data, tmp1, tmp2
sll global_cnt_reg, 0x3, tmp1
bloop1: ! get lock of barrier count
prefetch [tmp2], #n_reads
ld [tmp2 + 4], tmp3 ! increment
bloop2: ! check the barrier count
ld [tmp2 + 4], tmp3 ! if 0 ->
brz tmp3, bout2 ! somebody already reset it
sub tmp3, THREAD_COUNT, tmp3 ! subtract THREAD_COUNT
brnz tmp3, bloop2 ! if 0 -> we are out.
prefetch [tmp2], #n_reads
st %g0, [tmp2 + 4] ! clear the barrier counter
!==================================================