* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: tso_n2_ncrdwr3_user.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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* ========== Copyright Header End ============================================
#define MAIN_PAGE_HV_ALSO
#define PART0_NZ_RANOTPA_2 0
#define ENABLE_PCIE_LINK_TRAINING
wr %g0, 0x4, %fprs /* make sure fef is 1 */
setx 0x00d01ee000, %g1, %g3 ! will translate to MEM32 address space
setx user_data_start, %l0, %o0 ! user_data_start
! Now some NC writes and reads mixed with cacheable writes and reads
!================================
!================================
!================================
stda %f0, [%o0]ASI_BLK_PL
stda %f0, [%o0]ASI_BLK_PL
stda %f0, [%o0]ASI_BLK_PL
!================================
stxa %l0, [%o1]ASI_BLK_INIT_ST_QUAD_LDD_P
stxa %l1, [%o1]ASI_BLK_INIT_ST_QUAD_LDD_P
!================================
stxa %l0, [%o1]ASI_BLK_INIT_ST_QUAD_LDD_P_LITTLE
stxa %l1, [%o1]ASI_BLK_INIT_ST_QUAD_LDD_P_LITTLE
!================================
stxa %l0, [%o1]ASI_BLK_INIT_ST_QUAD_LDD_P
stxa %l1, [%o1]ASI_BLK_INIT_ST_QUAD_LDD_P
/******************************************************************/
SECTION .NCDATA DATA_VA=0x00d01ee000
part_0_ctx_nonzero_tsb_config_2,
TTE_G=0, TTE_Context=PCONTEXT, TTE_V=1, TTE_Size=0, TTE_SIZE_PTR=0, TTE_NFO=0,
TTE_IE=0, TTE_Soft2=0, TTE_Diag=0, TTE_Soft=0,
TTE_L=0, TTE_CP=0, TTE_CV=0, TTE_E=1, TTE_P=0, TTE_W=1