* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: tso_n2_ncrdwr5.s
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* ========== Copyright Header End ============================================
#define MAIN_PAGE_HV_ALSO
#define ASI_SWVR_INTR_RECEIVE 0x72
#define ASI_SWVR_UDB_INTR_W 0x73
#define ASI_SWVR_UDB_INTR_R 0x74
#define ENABLE_PCIE_LINK_TRAINING
#define H_T0_Trap_Instruction_0
#define My_T0_Trap_Instruction_0 \
!!!#define H_HT0_Data_Access_Exception_0x30 data_access_exception_custom_trap
#define H_HT0_DAE_nc_page_0x16
#define SUN_H_HT0_DAE_nc_page_0x16 \
wr %g0, 0x4, %fprs /* make sure fef is 1 */
setx 0xdeadbeefdeadbeef, %g1, %g2
setx 0xc100beef00, %g1, %g3 ! MEM32 address space
setx 0xdeadbeefdeadbeef, %g1, %g2
setx 0xc900beef00, %g1, %g3 ! MEM64 address space
! Now some NC writes and reads
prefetch [%g3], #n_writes
/***********************************************************************
***********************************************************************/
SECTION .MY_HYP_SEC TEXT_VA = 0x1100150000, DATA_VA = 0x1100160000
.global data_access_exception_custom_trap
data_access_exception_custom_trap: