* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: traps_34_35_36.s
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* ========== Copyright Header End ============================================
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
#define MY_GENERIC_TRAP \
! these should go to Hpriv table ???
#define H_HT0_Mem_Address_Not_Aligned_0x34
#define My_HT0_Mem_Address_Not_Aligned_0x34 MY_GENERIC_TRAP
#define H_HT0_Lddf_Mem_Address_Not_Aligned_0x35
#define My_HT0_Lddf_Mem_Address_Not_Aligned_0x35 MY_GENERIC_TRAP
#define H_HT0_Stdf_Mem_Address_Not_Aligned_0x36
#define My_HT0_Stdf_Mem_Address_Not_Aligned_0x36 MY_GENERIC_TRAP
/************************************************************************
************************************************************************/
! ta T_CHANGE_PRIV ! run in priv mode
! rdth_id ! get thread ID in %o1
! setx user_data_start, %g1, %g3
setx HV_TRAP_BASE_PA, %i1, %i7
srlx %i7, 13, %i4 ! HV_TRAP_BASE
setx TRAP_BASE_VA, %i1, %i7
srlx %i7, 13, %i5 ! TRAP_BASE
setx user_data_start, %g1, %i2
srlx %i2, 0x3, %i2 ! insure DW alignment
sllx %i2, 0x3, %i2 ! insure DW alignment
! %l5 = Mem_Address_Not_Aligned_0x34
srlx %l4, 13, %g3 ! table address
cmp %g3, %i4 ! correct table?
! %l5 = Lddf_Mem_Address_Not_Aligned_0x35
srlx %l4, 13, %g3 ! table address
cmp %g3, %i4 ! correct table?
! %l5 = Stdf_Mem_Address_Not_Aligned_0x36
srlx %l4, 13, %g3 ! table address
cmp %g3, %i4 ! correct table?
! check final trap count, overkill...
/************************************************************************
************************************************************************/
.xword 0xDEADBEEFDEADBEEF
.xword 0x1111111122222222
.xword 0x3333333344444444