* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: PCIeDMARw.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
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* ========== Copyright Header End ============================================
#define ENABLE_PCIE_LINK_TRAINING
#define MAIN_PAGE_HV_ALSO
#define MEM32_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
#define DMA_DATA_ADDR 0x0000000123456000
#define DMA_DATA_BYP_SADDR 0xfffc000123456000
#define DMA_DATA_BYP_EADDR 0xfffc000123456800
#define DMA_DATA_BYP_ADDR1 0xfffc000123457000
#define DMA_DATA_BYP_ADDR2 0xfffc000123457100
#define DMA_DATA_BYP_ADDR3 0xfffc000123457200
#define DMA_DATA_BYP_ADDR4 0xfffc000123457300
#define DMA_DATA_BYP_ADDR5 0xfffc000123457400
#define DMA_DATA_BYP_ADDR6 0xfffc000123457500
#define DMA_DATA_BYP_ADDR7 0xfffc000123457600
#define DMA_DATA_BYP_ADDR8 0xfffc000123457700
#define DMA_DATA_BYP_ADDR9 0xfffc000123457800
/************************************************************************
************************************************************************/
! see if this user event works in a loop (multi-shot)
nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt1)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_SADDR, DMA_DATA_BYP_EADDR, "64'h40", 1, *, * )
nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt2)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR2, "64'h40", 1 )
UsrEvnt3: !! this DMA Read will have 2 completions, since it is longer than 128 bytes (default MPS)
nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt3)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_SADDR, DMA_DATA_BYP_EADDR, "64'h100", 1, *, * )
nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt4)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR2, DMA_DATA_BYP_ADDR3, "64'h80", 1 )
nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt5)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR3, DMA_DATA_BYP_ADDR4, "64'h20", 1 )
nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt6)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR4, DMA_DATA_BYP_ADDR5, "64'h10", 1 )
nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt7)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR5, DMA_DATA_BYP_ADDR6, "64'h8", 1 )
nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt8)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR6, DMA_DATA_BYP_ADDR7, "64'h4", 1 )
nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt9)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR7, DMA_DATA_BYP_ADDR8, "64'h2", 1 )
nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt10)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR8, DMA_DATA_BYP_ADDR9, "64'h1", 1 )
nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt11)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR8, DMA_DATA_BYP_ADDR9, "64'h0", 1 )
nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt12)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_ADDR9, DMA_DATA_BYP_ADDR9, "64'h0", 1 )
! select a MEM32 address in PCI address range and transmit the command to NCU
setx MEM32_RD_ADDR, %g1, %g2
stx %g1, [%g2] ! MEM32 PIO Write
stx %g2, [%g2+8] ! MEM32 PIO Write
stx %g3, [%g2+16] ! MEM32 PIO Write
ldx [%g2], %l0 ! MEM32 PIO READ
ldx [%g2+8], %l1 ! MEM32 PIO READ
ldx [%g2+16], %l2 ! MEM32 PIO READ
/************************************************************************
************************************************************************/
SECTION .DATA DATA_VA=DMA_DATA_ADDR
init_mem(0x0101010201030104, 256, 8, +, 0, +, 0x0004000400040004)
/************************************************************************/