* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: mmu_mt_psize_1.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* ========== Copyright Header End ============================================
#define HV_RED_TEXT_PA 0x10000
#define HV_RED_DATA_PA 0x20000
#define HPTRAP_TEXT_PA 0x80000
#define HPTRAPS_EXT_TEXT_PA 0x90000
#define HPTRAPS_EXT_DATA_PA 0x98000
#define HP_GOOD_TRAP 0xa0
#define EXIT_GOOD ta P_GOOD_TRAP; nop
#define EXIT_BAD ta P_BAD_TRAP; nop
#define THR0_PCONTEXT_0 0x00000
#define THR0_PCONTEXT_1 0x01100
#define THR0_SCONTEXT_0 0x01200
#define THR0_SCONTEXT_1 0x01300
#define THR1_PCONTEXT_0 0x00001
#define THR1_PCONTEXT_1 0x01101
#define THR1_SCONTEXT_0 0x01201
#define THR1_SCONTEXT_1 0x01301
#define THR2_PCONTEXT_0 0x00002
#define THR2_PCONTEXT_1 0x01102
#define THR2_SCONTEXT_0 0x01202
#define THR2_SCONTEXT_1 0x01302
#define THR3_PCONTEXT_0 0x00003
#define THR3_PCONTEXT_1 0x01103
#define THR3_SCONTEXT_0 0x01203
#define THR3_SCONTEXT_1 0x01303
#define THR4_PCONTEXT_0 0x00004
#define THR4_PCONTEXT_1 0x01104
#define THR4_SCONTEXT_0 0x01204
#define THR4_SCONTEXT_1 0x01304
#define THR5_PCONTEXT_0 0x00005
#define THR5_PCONTEXT_1 0x01105
#define THR5_SCONTEXT_0 0x01205
#define THR5_SCONTEXT_1 0x01305
#define THR6_PCONTEXT_0 0x00006
#define THR6_PCONTEXT_1 0x01106
#define THR6_SCONTEXT_0 0x01206
#define THR6_SCONTEXT_1 0x01306
#define THR7_PCONTEXT_0 0x00007
#define THR7_PCONTEXT_1 0x01107
#define THR7_SCONTEXT_0 0x01207
#define THR7_SCONTEXT_1 0x01307
#define THR0_PTRAP_TEXT_VA 0x0100000000
#define THR0_PTRAP_TEXT_RA 0x0000300000
#define THR0_PTRAP_TEXT_PA 0x4000300000
#define THR1_PTRAP_TEXT_VA 0x0101000000
#define THR1_PTRAP_TEXT_RA 0x0000310000
#define THR1_PTRAP_TEXT_PA 0x4400310000
#define THR2_PTRAP_TEXT_VA 0x0102000000
#define THR2_PTRAP_TEXT_RA 0x0000320000
#define THR2_PTRAP_TEXT_PA 0x4800320000
#define THR3_PTRAP_TEXT_VA 0x0103000000
#define THR3_PTRAP_TEXT_RA 0x0000330000
#define THR3_PTRAP_TEXT_PA 0x4C00330000
#define THR4_PTRAP_TEXT_VA 0x0104000000
#define THR4_PTRAP_TEXT_RA 0x0000340000
#define THR4_PTRAP_TEXT_PA 0x5000340000
#define THR5_PTRAP_TEXT_VA 0x0105000000
#define THR5_PTRAP_TEXT_RA 0x0000350000
#define THR5_PTRAP_TEXT_PA 0x5400350000
#define THR6_PTRAP_TEXT_VA 0x0106000000
#define THR6_PTRAP_TEXT_RA 0x0000360000
#define THR6_PTRAP_TEXT_PA 0x5800360000
#define THR7_PTRAP_TEXT_VA 0x0107000000
#define THR7_PTRAP_TEXT_RA 0x0000370000
#define THR7_PTRAP_TEXT_PA 0x5C00370000
#define THR0_PRIV_TEXT_VA 0x000200000000
#define THR0_PRIV_TEXT_RA 0x0300000000
#define THR0_PRIV_TEXT_PA 0x4300000000
#define THR1_PRIV_TEXT_VA 0x000201000000
#define THR1_PRIV_TEXT_RA 0x0301000000
#define THR1_PRIV_TEXT_PA 0x4701000000
#define THR2_PRIV_TEXT_VA 0x000202000000
#define THR2_PRIV_TEXT_RA 0x0302000000
#define THR2_PRIV_TEXT_PA 0x4B02000000
#define THR3_PRIV_TEXT_VA 0x000203000000
#define THR3_PRIV_TEXT_RA 0x0303000000
#define THR3_PRIV_TEXT_PA 0x4F03000000
#define THR4_PRIV_TEXT_VA 0x000204000000
#define THR4_PRIV_TEXT_RA 0x0304000000
#define THR4_PRIV_TEXT_PA 0x5304000000
#define THR5_PRIV_TEXT_VA 0x000205000000
#define THR5_PRIV_TEXT_RA 0x0305000000
#define THR5_PRIV_TEXT_PA 0x5705000000
#define THR6_PRIV_TEXT_VA 0x000206000000
#define THR6_PRIV_TEXT_RA 0x0306000000
#define THR6_PRIV_TEXT_PA 0x5B06000000
#define THR7_PRIV_TEXT_VA 0x000207000000
#define THR7_PRIV_TEXT_RA 0x0307000000
#define THR7_PRIV_TEXT_PA 0x5F07000000
#define THR0_USER_TEXT_4V_VA000 0x1000000000
#define THR0_USER_TEXT_4V_RA000 0x0200000000
#define THR0_USER_TEXT_4V_PA000 0x4200000000
#define THR0_USER_DATA_4V_VA008 0x1010000000
#define THR0_USER_DATA_4V_RA008 0x0210000000
#define THR0_USER_DATA_4V_PA008 0x4210000000
#define THR0_USER_DATA_4V_PA008_8K 0x42103FE000
#define THR0_END_PAGE008 0x10103FFFFC
#define THR0_USER_DATA_4V_VA010 0x1010400000
#define THR0_USER_DATA_4V_RA010 0x0210400000
#define THR0_USER_DATA_4V_PA010 0x4210400000
#define THR0_USER_TEXT_4V_VA001 0x1020000000
#define THR0_USER_TEXT_4V_RA001 0x0220000000
#define THR0_USER_TEXT_4V_PA001 0x4220000000
#define THR0_USER_DATA_4V_VA009 0x1030000000
#define THR0_USER_DATA_4V_RA009 0x0230000000
#define THR0_USER_DATA_4V_PA009 0x4230000000
#define THR0_USER_DATA_4V_PA009_8K 0x423FFFE000
#define THR0_END_PAGE009 0x103FFFFFFC
#define THR0_USER_DATA_4V_VA011 0x1040000000
#define THR0_USER_DATA_4V_RA011 0x0240000000
#define THR0_USER_DATA_4V_PA011 0x4240000000
#define THR1_USER_TEXT_4V_VA000 0x1050000000
#define THR1_USER_TEXT_4V_RA000 0x0250000000
#define THR1_USER_TEXT_4V_PA000 0x4650000000
#define THR1_USER_DATA_4V_VA008 0x1060000000
#define THR1_USER_DATA_4V_RA008 0x0260000000
#define THR1_USER_DATA_4V_PA008 0x4660000000
#define THR1_USER_DATA_4V_PA008_8K 0x46603FE000
#define THR1_END_PAGE008 0x10603FFFFC
#define THR1_USER_DATA_4V_VA010 0x1060400000
#define THR1_USER_DATA_4V_RA010 0x0260400000
#define THR1_USER_DATA_4V_PA010 0x4660400000
#define THR1_USER_TEXT_4V_VA001 0x1070000000
#define THR1_USER_TEXT_4V_RA001 0x0270000000
#define THR1_USER_TEXT_4V_PA001 0x4670000000
#define THR1_USER_DATA_4V_VA009 0x1080000000
#define THR1_USER_DATA_4V_RA009 0x0280000000
#define THR1_USER_DATA_4V_PA009 0x4680000000
#define THR1_USER_DATA_4V_PA009_8K 0x468FFFE000
#define THR1_END_PAGE009 0x108FFFFFFC
#define THR1_USER_DATA_4V_VA011 0x1090000000
#define THR1_USER_DATA_4V_RA011 0x0290000000
#define THR1_USER_DATA_4V_PA011 0x4690000000
#define THR2_USER_TEXT_4V_VA000 0x10A0000000
#define THR2_USER_TEXT_4V_RA000 0x02A0000000
#define THR2_USER_TEXT_4V_PA000 0x4AA0000000
#define THR2_USER_DATA_4V_VA008 0x10B0000000
#define THR2_USER_DATA_4V_RA008 0x02B0000000
#define THR2_USER_DATA_4V_PA008 0x4AB0000000
#define THR2_USER_DATA_4V_PA008_8K 0x4AB03FE000
#define THR2_END_PAGE008 0x10B03FFFFC
#define THR2_USER_DATA_4V_VA010 0x10B0400000
#define THR2_USER_DATA_4V_RA010 0x02B0400000
#define THR2_USER_DATA_4V_PA010 0x4AB0400000
#define THR2_USER_TEXT_4V_VA001 0x10C0000000
#define THR2_USER_TEXT_4V_RA001 0x02C0000000
#define THR2_USER_TEXT_4V_PA001 0x4AC0000000
#define THR2_USER_DATA_4V_VA009 0x10D0000000
#define THR2_USER_DATA_4V_RA009 0x02D0000000
#define THR2_USER_DATA_4V_PA009 0x4AD0000000
#define THR2_USER_DATA_4V_PA009_8K 0x4ADFFFE000
#define THR2_END_PAGE009 0x10DFFFFFFC
#define THR2_USER_DATA_4V_VA011 0x10E0000000
#define THR2_USER_DATA_4V_RA011 0x02E0000000
#define THR2_USER_DATA_4V_PA011 0x4AE0000000
#define THR3_USER_TEXT_4V_VA000 0x10F0000000
#define THR3_USER_TEXT_4V_RA000 0x02F0000000
#define THR3_USER_TEXT_4V_PA000 0x4EF0000000
#define THR3_USER_DATA_4V_VA008 0x1100000000
#define THR3_USER_DATA_4V_RA008 0x0300000000
#define THR3_USER_DATA_4V_PA008 0x4F00000000
#define THR3_USER_DATA_4V_PA008_8K 0x4F003FE000
#define THR3_END_PAGE008 0x11003FFFFC
#define THR3_USER_DATA_4V_VA010 0x1100400000
#define THR3_USER_DATA_4V_RA010 0x0300400000
#define THR3_USER_DATA_4V_PA010 0x4F00400000
#define THR3_USER_TEXT_4V_VA001 0x1110000000
#define THR3_USER_TEXT_4V_RA001 0x0310000000
#define THR3_USER_TEXT_4V_PA001 0x4F10000000
#define THR3_USER_DATA_4V_VA009 0x1120000000
#define THR3_USER_DATA_4V_RA009 0x0320000000
#define THR3_USER_DATA_4V_PA009 0x4F20000000
#define THR3_USER_DATA_4V_PA009_8K 0x4F2FFFE000
#define THR3_END_PAGE009 0x112FFFFFFC
#define THR3_USER_DATA_4V_VA011 0x1130000000
#define THR3_USER_DATA_4V_RA011 0x0330000000
#define THR3_USER_DATA_4V_PA011 0x4F30000000
#define THR4_USER_TEXT_4V_VA000 0x1140000000
#define THR4_USER_TEXT_4V_RA000 0x0340000000
#define THR4_USER_TEXT_4V_PA000 0x5340000000
#define THR4_USER_DATA_4V_VA008 0x1150000000
#define THR4_USER_DATA_4V_RA008 0x0350000000
#define THR4_USER_DATA_4V_PA008 0x5350000000
#define THR4_USER_DATA_4V_PA008_8K 0x53503FE000
#define THR4_END_PAGE008 0x11503FFFFC
#define THR4_USER_DATA_4V_VA010 0x1150400000
#define THR4_USER_DATA_4V_RA010 0x0350400000
#define THR4_USER_DATA_4V_PA010 0x5350400000
#define THR4_USER_TEXT_4V_VA001 0x1160000000
#define THR4_USER_TEXT_4V_RA001 0x0360000000
#define THR4_USER_TEXT_4V_PA001 0x5360000000
#define THR4_USER_DATA_4V_VA009 0x1170000000
#define THR4_USER_DATA_4V_RA009 0x0370000000
#define THR4_USER_DATA_4V_PA009 0x5370000000
#define THR4_USER_DATA_4V_PA009_8K 0x537FFFE000
#define THR4_END_PAGE009 0x117FFFFFFC
#define THR4_USER_DATA_4V_VA011 0x1180000000
#define THR4_USER_DATA_4V_RA011 0x0380000000
#define THR4_USER_DATA_4V_PA011 0x5380000000
#define THR5_USER_TEXT_4V_VA000 0x1190000000
#define THR5_USER_TEXT_4V_RA000 0x0390000000
#define THR5_USER_TEXT_4V_PA000 0x5790000000
#define THR5_USER_DATA_4V_VA008 0x11A0000000
#define THR5_USER_DATA_4V_RA008 0x03A0000000
#define THR5_USER_DATA_4V_PA008 0x57A0000000
#define THR5_USER_DATA_4V_PA008_8K 0x57A03FE000
#define THR5_END_PAGE008 0x11A03FFFFC
#define THR5_USER_DATA_4V_VA010 0x11A0400000
#define THR5_USER_DATA_4V_RA010 0x03A0400000
#define THR5_USER_DATA_4V_PA010 0x57A0400000
#define THR5_USER_TEXT_4V_VA001 0x11B0000000
#define THR5_USER_TEXT_4V_RA001 0x03B0000000
#define THR5_USER_TEXT_4V_PA001 0x57B0000000
#define THR5_USER_DATA_4V_VA009 0x11C0000000
#define THR5_USER_DATA_4V_RA009 0x03C0000000
#define THR5_USER_DATA_4V_PA009 0x57C0000000
#define THR5_USER_DATA_4V_PA009_8K 0x57CFFFE000
#define THR5_END_PAGE009 0x11CFFFFFFC
#define THR5_USER_DATA_4V_VA011 0x11D0000000
#define THR5_USER_DATA_4V_RA011 0x03D0000000
#define THR5_USER_DATA_4V_PA011 0x57D0000000
#define THR6_USER_TEXT_4V_VA000 0x11E0000000
#define THR6_USER_TEXT_4V_RA000 0x03E0000000
#define THR6_USER_TEXT_4V_PA000 0x5BE0000000
#define THR6_USER_DATA_4V_VA008 0x11F0000000
#define THR6_USER_DATA_4V_RA008 0x03F0000000
#define THR6_USER_DATA_4V_PA008 0x5BF0000000
#define THR6_USER_DATA_4V_PA008_8K 0x5BF03FE000
#define THR6_END_PAGE008 0x11F03FFFFC
#define THR6_USER_DATA_4V_VA010 0x11F0400000
#define THR6_USER_DATA_4V_RA010 0x03F0400000
#define THR6_USER_DATA_4V_PA010 0x5BF0400000
#define THR6_USER_TEXT_4V_VA001 0x1200000000
#define THR6_USER_TEXT_4V_RA001 0x0400000000
#define THR6_USER_TEXT_4V_PA001 0x5C00000000
#define THR6_USER_DATA_4V_VA009 0x1210000000
#define THR6_USER_DATA_4V_RA009 0x0410000000
#define THR6_USER_DATA_4V_PA009 0x5C10000000
#define THR6_USER_DATA_4V_PA009_8K 0x5C1FFFE000
#define THR6_END_PAGE009 0x121FFFFFFC
#define THR6_USER_DATA_4V_VA011 0x1220000000
#define THR6_USER_DATA_4V_RA011 0x0420000000
#define THR6_USER_DATA_4V_PA011 0x5C20000000
#define THR7_USER_TEXT_4V_VA000 0x1230000000
#define THR7_USER_TEXT_4V_RA000 0x0430000000
#define THR7_USER_TEXT_4V_PA000 0x6030000000
#define THR7_USER_DATA_4V_VA008 0x1240000000
#define THR7_USER_DATA_4V_RA008 0x0440000000
#define THR7_USER_DATA_4V_PA008 0x6040000000
#define THR7_USER_DATA_4V_PA008_8K 0x60403FE000
#define THR7_END_PAGE008 0x12403FFFFC
#define THR7_USER_DATA_4V_VA010 0x1240400000
#define THR7_USER_DATA_4V_RA010 0x0440400000
#define THR7_USER_DATA_4V_PA010 0x6040400000
#define THR7_USER_TEXT_4V_VA001 0x1250000000
#define THR7_USER_TEXT_4V_RA001 0x0450000000
#define THR7_USER_TEXT_4V_PA001 0x6050000000
#define THR7_USER_DATA_4V_VA009 0x1260000000
#define THR7_USER_DATA_4V_RA009 0x0460000000
#define THR7_USER_DATA_4V_PA009 0x6060000000
#define THR7_USER_DATA_4V_PA009_8K 0x606FFFE000
#define THR7_END_PAGE009 0x126FFFFFFC
#define THR7_USER_DATA_4V_VA011 0x1270000000
#define THR7_USER_DATA_4V_RA011 0x0470000000
#define THR7_USER_DATA_4V_PA011 0x6070000000
#define THR0_PHY_OFF_0 0x4000001000
#define THR0_PHY_OFF_1 0x4100001000
#define THR0_PHY_OFF_2 0x4200001000
#define THR0_PHY_OFF_3 0x4300001000
#define THR1_PHY_OFF_0 0x4400001000
#define THR1_PHY_OFF_1 0x4500001000
#define THR1_PHY_OFF_2 0x4600001000
#define THR1_PHY_OFF_3 0x4700001000
#define THR2_PHY_OFF_0 0x4800001000
#define THR2_PHY_OFF_1 0x4900001000
#define THR2_PHY_OFF_2 0x4a00001000
#define THR2_PHY_OFF_3 0x4b00001000
#define THR3_PHY_OFF_0 0x4c00001000
#define THR3_PHY_OFF_1 0x4d00001000
#define THR3_PHY_OFF_2 0x4e00001000
#define THR3_PHY_OFF_3 0x4f00001000
#define THR4_PHY_OFF_0 0x5000001000
#define THR4_PHY_OFF_1 0x5100001000
#define THR4_PHY_OFF_2 0x5200001000
#define THR4_PHY_OFF_3 0x5300001000
#define THR5_PHY_OFF_0 0x5400001000
#define THR5_PHY_OFF_1 0x5500001000
#define THR5_PHY_OFF_2 0x5600001000
#define THR5_PHY_OFF_3 0x5700001000
#define THR6_PHY_OFF_0 0x5800001000
#define THR6_PHY_OFF_1 0x5900001000
#define THR6_PHY_OFF_2 0x5a00001000
#define THR6_PHY_OFF_3 0x5b00001000
#define THR7_PHY_OFF_0 0x5c00001000
#define THR7_PHY_OFF_1 0x5d00001000
#define THR7_PHY_OFF_2 0x5e00001000
#define THR7_PHY_OFF_3 0x5f00001000
#define THR0_REAL_RANGE_0 0x8004000000000000
#define THR0_REAL_RANGE_1 0x8008000000000000
#define THR0_REAL_RANGE_2 0x8010000000000000
#define THR0_REAL_RANGE_3 0x8020000000000000
#define THR1_REAL_RANGE_0 0x8004000000000000
#define THR1_REAL_RANGE_1 0x8008000000000000
#define THR1_REAL_RANGE_2 0x8010000000000000
#define THR1_REAL_RANGE_3 0x8020000000000000
#define THR2_REAL_RANGE_0 0x8004000000000000
#define THR2_REAL_RANGE_1 0x8008000000000000
#define THR2_REAL_RANGE_2 0x8010000000000000
#define THR2_REAL_RANGE_3 0x8020000000000000
#define THR3_REAL_RANGE_0 0x8004000000000000
#define THR3_REAL_RANGE_1 0x8008000000000000
#define THR3_REAL_RANGE_2 0x8010000000000000
#define THR3_REAL_RANGE_3 0x8020000000000000
#define THR4_REAL_RANGE_0 0x8004000000000000
#define THR4_REAL_RANGE_1 0x8008000000000000
#define THR4_REAL_RANGE_2 0x8010000000000000
#define THR4_REAL_RANGE_3 0x8020000000000000
#define THR5_REAL_RANGE_0 0x8004000000000000
#define THR5_REAL_RANGE_1 0x8008000000000000
#define THR5_REAL_RANGE_2 0x8010000000000000
#define THR5_REAL_RANGE_3 0x8020000000000000
#define THR6_REAL_RANGE_0 0x8004000000000000
#define THR6_REAL_RANGE_1 0x8008000000000000
#define THR6_REAL_RANGE_2 0x8010000000000000
#define THR6_REAL_RANGE_3 0x8020000000000000
#define THR7_REAL_RANGE_0 0x8004000000000000
#define THR7_REAL_RANGE_1 0x8008000000000000
#define THR7_REAL_RANGE_2 0x8010000000000000
#define THR7_REAL_RANGE_3 0x8020000000000000
#define THR0_Z_CTX_TSB_CONFIG_0 0x8000000100000104
#define THR0_Z_CTX_TSB_CONFIG_1 0x8000000101000113
#define THR0_Z_CTX_TSB_CONFIG_2 0x8000000102000132
#define THR0_Z_CTX_TSB_CONFIG_3 0x8000000103000151
#define THR0_NZ_CTX_TSB_CONFIG_0 0x8000000104000104
#define THR0_NZ_CTX_TSB_CONFIG_1 0x8000000105000103
#define THR0_NZ_CTX_TSB_CONFIG_2 0x8000000106000102
#define THR0_NZ_CTX_TSB_CONFIG_3 0x8000000107000101
#define THR1_Z_CTX_TSB_CONFIG_0 0x8000000108000104
#define THR1_Z_CTX_TSB_CONFIG_1 0x8000000109000113
#define THR1_Z_CTX_TSB_CONFIG_2 0x800000010a000102
#define THR1_Z_CTX_TSB_CONFIG_3 0x800000010b000101
#define THR1_NZ_CTX_TSB_CONFIG_0 0x800000010c000104
#define THR1_NZ_CTX_TSB_CONFIG_1 0x800000010d000113
#define THR1_NZ_CTX_TSB_CONFIG_2 0x800000010e000132
#define THR1_NZ_CTX_TSB_CONFIG_3 0x800000010f000151
#define THR2_Z_CTX_TSB_CONFIG_0 0x8000000110000114
#define THR2_Z_CTX_TSB_CONFIG_1 0x8000000111000113
#define THR2_Z_CTX_TSB_CONFIG_2 0x8000000112000132
#define THR2_Z_CTX_TSB_CONFIG_3 0x8000000113000151
#define THR2_NZ_CTX_TSB_CONFIG_0 0x8000000114000104
#define THR2_NZ_CTX_TSB_CONFIG_1 0x8000000115000113
#define THR2_NZ_CTX_TSB_CONFIG_2 0x8000000116000132
#define THR2_NZ_CTX_TSB_CONFIG_3 0x8000000117000151
#define THR3_Z_CTX_TSB_CONFIG_0 0x8000000118000114
#define THR3_Z_CTX_TSB_CONFIG_1 0x8000000119000113
#define THR3_Z_CTX_TSB_CONFIG_2 0x800000011a000132
#define THR3_Z_CTX_TSB_CONFIG_3 0x800000011b000151
#define THR3_NZ_CTX_TSB_CONFIG_0 0x800000011c000104
#define THR3_NZ_CTX_TSB_CONFIG_1 0x800000011d000113
#define THR3_NZ_CTX_TSB_CONFIG_2 0x800000011e000132
#define THR3_NZ_CTX_TSB_CONFIG_3 0x800000011f000151
#define THR4_Z_CTX_TSB_CONFIG_0 0x8000000120000114
#define THR4_Z_CTX_TSB_CONFIG_1 0x8000000121000113
#define THR4_Z_CTX_TSB_CONFIG_2 0x8000000122000132
#define THR4_Z_CTX_TSB_CONFIG_3 0x8000000123000151
#define THR4_NZ_CTX_TSB_CONFIG_0 0x8000000124000104
#define THR4_NZ_CTX_TSB_CONFIG_1 0x8000000125000113
#define THR4_NZ_CTX_TSB_CONFIG_2 0x8000000126000132
#define THR4_NZ_CTX_TSB_CONFIG_3 0x8000000127000151
#define THR5_Z_CTX_TSB_CONFIG_0 0x8000000128000114
#define THR5_Z_CTX_TSB_CONFIG_1 0x8000000129000113
#define THR5_Z_CTX_TSB_CONFIG_2 0x800000012a000132
#define THR5_Z_CTX_TSB_CONFIG_3 0x800000012b000151
#define THR5_NZ_CTX_TSB_CONFIG_0 0x800000012c000104
#define THR5_NZ_CTX_TSB_CONFIG_1 0x800000012d000113
#define THR5_NZ_CTX_TSB_CONFIG_2 0x800000012e000132
#define THR5_NZ_CTX_TSB_CONFIG_3 0x800000012f000151
#define THR6_Z_CTX_TSB_CONFIG_0 0x8000000130000114
#define THR6_Z_CTX_TSB_CONFIG_1 0x8000000131000113
#define THR6_Z_CTX_TSB_CONFIG_2 0x8000000132000132
#define THR6_Z_CTX_TSB_CONFIG_3 0x8000000133000151
#define THR6_NZ_CTX_TSB_CONFIG_0 0x8000000134000104
#define THR6_NZ_CTX_TSB_CONFIG_1 0x8000000135000113
#define THR6_NZ_CTX_TSB_CONFIG_2 0x8000000136000132
#define THR6_NZ_CTX_TSB_CONFIG_3 0x8000000137000151
#define THR7_Z_CTX_TSB_CONFIG_0 0x8000000138000114
#define THR7_Z_CTX_TSB_CONFIG_1 0x8000000139000113
#define THR7_Z_CTX_TSB_CONFIG_2 0x800000013a000132
#define THR7_Z_CTX_TSB_CONFIG_3 0x800000013b000151
#define THR7_NZ_CTX_TSB_CONFIG_0 0x800000013c000104
#define THR7_NZ_CTX_TSB_CONFIG_1 0x800000013d000113
#define THR7_NZ_CTX_TSB_CONFIG_2 0x800000013e000132
#define THR7_NZ_CTX_TSB_CONFIG_3 0x800000013f000151
MIDAS_TSB thr0_z_ctx_tsb_0 THR0_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr0_z_ctx_tsb_1 THR0_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr0_z_ctx_tsb_2 THR0_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr0_z_ctx_tsb_3 THR0_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr0_nz_ctx_tsb_0 THR0_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr0_nz_ctx_tsb_1 THR0_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr0_nz_ctx_tsb_2 THR0_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr0_nz_ctx_tsb_3 THR0_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr1_z_ctx_tsb_0 THR1_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr1_z_ctx_tsb_1 THR1_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr1_z_ctx_tsb_2 THR1_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr1_z_ctx_tsb_3 THR1_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr1_nz_ctx_tsb_0 THR1_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr1_nz_ctx_tsb_1 THR1_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr1_nz_ctx_tsb_2 THR1_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr1_nz_ctx_tsb_3 THR1_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr2_z_ctx_tsb_0 THR2_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr2_z_ctx_tsb_1 THR2_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr2_z_ctx_tsb_2 THR2_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr2_z_ctx_tsb_3 THR2_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr2_nz_ctx_tsb_0 THR2_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr2_nz_ctx_tsb_1 THR2_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr2_nz_ctx_tsb_2 THR2_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr2_nz_ctx_tsb_3 THR2_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr3_z_ctx_tsb_0 THR3_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr3_z_ctx_tsb_1 THR3_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr3_z_ctx_tsb_2 THR3_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr3_z_ctx_tsb_3 THR3_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr3_nz_ctx_tsb_0 THR3_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr3_nz_ctx_tsb_1 THR3_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr3_nz_ctx_tsb_2 THR3_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr3_nz_ctx_tsb_3 THR3_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr4_z_ctx_tsb_0 THR4_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr4_z_ctx_tsb_1 THR4_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr4_z_ctx_tsb_2 THR4_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr4_z_ctx_tsb_3 THR4_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr4_nz_ctx_tsb_0 THR4_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr4_nz_ctx_tsb_1 THR4_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr4_nz_ctx_tsb_2 THR4_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr4_nz_ctx_tsb_3 THR4_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr5_z_ctx_tsb_0 THR5_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr5_z_ctx_tsb_1 THR5_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr5_z_ctx_tsb_2 THR5_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr5_z_ctx_tsb_3 THR5_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr5_nz_ctx_tsb_0 THR5_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr5_nz_ctx_tsb_1 THR5_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr5_nz_ctx_tsb_2 THR5_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr5_nz_ctx_tsb_3 THR5_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr6_z_ctx_tsb_0 THR6_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr6_z_ctx_tsb_1 THR6_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr6_z_ctx_tsb_2 THR6_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr6_z_ctx_tsb_3 THR6_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr6_nz_ctx_tsb_0 THR6_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr6_nz_ctx_tsb_1 THR6_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr6_nz_ctx_tsb_2 THR6_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr6_nz_ctx_tsb_3 THR6_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr7_z_ctx_tsb_0 THR7_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr7_z_ctx_tsb_1 THR7_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr7_z_ctx_tsb_2 THR7_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr7_z_ctx_tsb_3 THR7_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr7_nz_ctx_tsb_0 THR7_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr7_nz_ctx_tsb_1 THR7_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr7_nz_ctx_tsb_2 THR7_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr7_nz_ctx_tsb_3 THR7_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v
!#*****************************************************************************************
SECTION .RED_SEC TEXT_VA = 0xfffffffff0000000
wrhpr %l1, 0x820, %hpstate
! load partition id to %l7
wr %g0, ASI_CORE_ID, %asi
ldxa [ASI_CORE_ID_VA] %asi, %l7
and %l7, %g1, %l7 ! %l7 has TID
setx thr0_red_handler, %l0, %l2
setx thr1_red_handler, %l0, %l2
setx thr2_red_handler, %l0, %l2
setx thr3_red_handler, %l0, %l2
setx thr4_red_handler, %l0, %l2
setx thr5_red_handler, %l0, %l2
setx thr6_red_handler, %l0, %l2
setx thr7_red_handler, %l0, %l2
!#*****************************************************************************************
SECTION .RED_EXT_SEC TEXT_VA = HV_RED_TEXT_PA, DATA_VA = HV_RED_DATA_PA
mov ASI_PARTITION_ID_VAL, %g1
stxa %g2, [%g1] ASI_PARTITION_ID
! set hyper trap base addr
setx HPTRAP_TEXT_PA, %l0, %l7
thr0_hred_context_config:
setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1
setx THR0_PCONTEXT_0, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi
setx THR0_PCONTEXT_1, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi
setx THR0_SCONTEXT_0, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi
setx THR0_SCONTEXT_1, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi
thr0_hred_physical_offset:
setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1
setx THR0_PHY_OFF_0, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi
setx THR0_PHY_OFF_1, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi
setx THR0_PHY_OFF_2, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi
setx THR0_PHY_OFF_3, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi
setx ASI_MMU_REAL_RANGE, %l1, %g1
setx THR0_REAL_RANGE_0, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi
setx THR0_REAL_RANGE_1, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi
setx THR0_REAL_RANGE_2, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi
setx THR0_REAL_RANGE_3, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi
mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3
thr0_hred_tsb_z_config_0:
setx THR0_Z_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR0_Z_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR0_Z_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR0_Z_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi
setx THR0_NZ_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR0_NZ_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR0_NZ_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR0_NZ_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi
stxa %l7, [%g0] ASI_LSU_CONTROL
thr0_transfer_to_priv_code:
setx thr0_priv_code_begin, %g1, %g2
wrhpr %g0, 0x000, %hpstate
mov ASI_PARTITION_ID_VAL, %g1
stxa %g2, [%g1] ASI_PARTITION_ID
! set hyper trap base addr
setx HPTRAP_TEXT_PA, %l0, %l7
thr1_hred_context_config:
setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1
setx THR1_PCONTEXT_0, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi
setx THR1_PCONTEXT_1, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi
setx THR1_SCONTEXT_0, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi
setx THR1_SCONTEXT_1, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi
thr1_hred_physical_offset:
setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1
setx THR1_PHY_OFF_0, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi
setx THR1_PHY_OFF_1, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi
setx THR1_PHY_OFF_2, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi
setx THR1_PHY_OFF_3, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi
setx ASI_MMU_REAL_RANGE, %l1, %g1
setx THR1_REAL_RANGE_0, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi
setx THR1_REAL_RANGE_1, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi
setx THR1_REAL_RANGE_2, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi
setx THR1_REAL_RANGE_3, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi
mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3
thr1_hred_tsb_z_config_0:
setx THR1_Z_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR1_Z_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR1_Z_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR1_Z_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi
setx THR1_NZ_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR1_NZ_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR1_NZ_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR1_NZ_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi
stxa %l7, [%g0] ASI_LSU_CONTROL
thr1_transfer_to_priv_code:
setx thr1_priv_code_begin, %g1, %g2
wrhpr %g0, 0x000, %hpstate
mov ASI_PARTITION_ID_VAL, %g1
stxa %g2, [%g1] ASI_PARTITION_ID
! set hyper trap base addr
setx HPTRAP_TEXT_PA, %l0, %l7
thr2_hred_context_config:
setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1
setx THR2_PCONTEXT_0, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi
setx THR2_PCONTEXT_1, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi
setx THR2_SCONTEXT_0, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi
setx THR2_SCONTEXT_1, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi
thr2_hred_physical_offset:
setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1
setx THR2_PHY_OFF_0, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi
setx THR2_PHY_OFF_1, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi
setx THR2_PHY_OFF_2, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi
setx THR2_PHY_OFF_3, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi
setx ASI_MMU_REAL_RANGE, %l1, %g1
setx THR2_REAL_RANGE_0, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi
setx THR2_REAL_RANGE_1, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi
setx THR2_REAL_RANGE_2, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi
setx THR2_REAL_RANGE_3, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi
mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3
thr2_hred_tsb_z_config_0:
setx THR2_Z_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR2_Z_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR2_Z_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR2_Z_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi
setx THR2_NZ_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR2_NZ_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR2_NZ_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR2_NZ_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi
stxa %l7, [%g0] ASI_LSU_CONTROL
thr2_transfer_to_priv_code:
setx thr2_priv_code_begin, %g1, %g2
wrhpr %g0, 0x000, %hpstate
mov ASI_PARTITION_ID_VAL, %g1
stxa %g2, [%g1] ASI_PARTITION_ID
! set hyper trap base addr
setx HPTRAP_TEXT_PA, %l0, %l7
thr3_hred_context_config:
setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1
setx THR3_PCONTEXT_0, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi
setx THR3_PCONTEXT_1, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi
setx THR3_SCONTEXT_0, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi
setx THR3_SCONTEXT_1, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi
thr3_hred_physical_offset:
setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1
setx THR3_PHY_OFF_0, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi
setx THR3_PHY_OFF_1, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi
setx THR3_PHY_OFF_2, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi
setx THR3_PHY_OFF_3, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi
setx ASI_MMU_REAL_RANGE, %l1, %g1
setx THR3_REAL_RANGE_0, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi
setx THR3_REAL_RANGE_1, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi
setx THR3_REAL_RANGE_2, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi
setx THR3_REAL_RANGE_3, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi
mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3
thr3_hred_tsb_z_config_0:
setx THR3_Z_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR3_Z_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR3_Z_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR3_Z_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi
setx THR3_NZ_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR3_NZ_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR3_NZ_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR3_NZ_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi
stxa %l7, [%g0] ASI_LSU_CONTROL
thr3_transfer_to_priv_code:
setx thr3_priv_code_begin, %g1, %g2
wrhpr %g0, 0x000, %hpstate
mov ASI_PARTITION_ID_VAL, %g1
stxa %g2, [%g1] ASI_PARTITION_ID
! set hyper trap base addr
setx HPTRAP_TEXT_PA, %l0, %l7
thr4_hred_context_config:
setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1
setx THR4_PCONTEXT_0, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi
setx THR4_PCONTEXT_1, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi
setx THR4_SCONTEXT_0, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi
setx THR4_SCONTEXT_1, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi
thr4_hred_physical_offset:
setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1
setx THR4_PHY_OFF_0, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi
setx THR4_PHY_OFF_1, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi
setx THR4_PHY_OFF_2, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi
setx THR4_PHY_OFF_3, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi
setx ASI_MMU_REAL_RANGE, %l1, %g1
setx THR4_REAL_RANGE_0, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi
setx THR4_REAL_RANGE_1, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi
setx THR4_REAL_RANGE_2, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi
setx THR4_REAL_RANGE_3, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi
mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3
thr4_hred_tsb_z_config_0:
setx THR4_Z_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR4_Z_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR4_Z_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR4_Z_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi
setx THR4_NZ_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR4_NZ_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR4_NZ_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR4_NZ_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi
stxa %l7, [%g0] ASI_LSU_CONTROL
thr4_transfer_to_priv_code:
setx thr4_priv_code_begin, %g1, %g2
wrhpr %g0, 0x000, %hpstate
mov ASI_PARTITION_ID_VAL, %g1
stxa %g2, [%g1] ASI_PARTITION_ID
! set hyper trap base addr
setx HPTRAP_TEXT_PA, %l0, %l7
thr5_hred_context_config:
setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1
setx THR5_PCONTEXT_0, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi
setx THR5_PCONTEXT_1, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi
setx THR5_SCONTEXT_0, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi
setx THR5_SCONTEXT_1, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi
thr5_hred_physical_offset:
setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1
setx THR5_PHY_OFF_0, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi
setx THR5_PHY_OFF_1, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi
setx THR5_PHY_OFF_2, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi
setx THR5_PHY_OFF_3, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi
setx ASI_MMU_REAL_RANGE, %l1, %g1
setx THR5_REAL_RANGE_0, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi
setx THR5_REAL_RANGE_1, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi
setx THR5_REAL_RANGE_2, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi
setx THR5_REAL_RANGE_3, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi
mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3
thr5_hred_tsb_z_config_0:
setx THR5_Z_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR5_Z_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR5_Z_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR5_Z_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi
setx THR5_NZ_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR5_NZ_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR5_NZ_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR5_NZ_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi
stxa %l7, [%g0] ASI_LSU_CONTROL
thr5_transfer_to_priv_code:
setx thr5_priv_code_begin, %g1, %g2
wrhpr %g0, 0x000, %hpstate
mov ASI_PARTITION_ID_VAL, %g1
stxa %g2, [%g1] ASI_PARTITION_ID
! set hyper trap base addr
setx HPTRAP_TEXT_PA, %l0, %l7
thr6_hred_context_config:
setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1
setx THR6_PCONTEXT_0, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi
setx THR6_PCONTEXT_1, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi
setx THR6_SCONTEXT_0, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi
setx THR6_SCONTEXT_1, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi
thr6_hred_physical_offset:
setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1
setx THR6_PHY_OFF_0, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi
setx THR6_PHY_OFF_1, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi
setx THR6_PHY_OFF_2, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi
setx THR6_PHY_OFF_3, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi
setx ASI_MMU_REAL_RANGE, %l1, %g1
setx THR6_REAL_RANGE_0, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi
setx THR6_REAL_RANGE_1, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi
setx THR6_REAL_RANGE_2, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi
setx THR6_REAL_RANGE_3, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi
mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3
thr6_hred_tsb_z_config_0:
setx THR6_Z_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR6_Z_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR6_Z_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR6_Z_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi
setx THR6_NZ_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR6_NZ_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR6_NZ_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR6_NZ_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi
stxa %l7, [%g0] ASI_LSU_CONTROL
thr6_transfer_to_priv_code:
setx thr6_priv_code_begin, %g1, %g2
wrhpr %g0, 0x000, %hpstate
mov ASI_PARTITION_ID_VAL, %g1
stxa %g2, [%g1] ASI_PARTITION_ID
! set hyper trap base addr
setx HPTRAP_TEXT_PA, %l0, %l7
thr7_hred_context_config:
setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1
setx THR7_PCONTEXT_0, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi
setx THR7_PCONTEXT_1, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi
setx THR7_SCONTEXT_0, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi
setx THR7_SCONTEXT_1, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi
thr7_hred_physical_offset:
setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1
setx THR7_PHY_OFF_0, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi
setx THR7_PHY_OFF_1, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi
setx THR7_PHY_OFF_2, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi
setx THR7_PHY_OFF_3, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi
setx ASI_MMU_REAL_RANGE, %l1, %g1
setx THR7_REAL_RANGE_0, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi
setx THR7_REAL_RANGE_1, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi
setx THR7_REAL_RANGE_2, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi
setx THR7_REAL_RANGE_3, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi
mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3
thr7_hred_tsb_z_config_0:
setx THR7_Z_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR7_Z_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR7_Z_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR7_Z_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi
setx THR7_NZ_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR7_NZ_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR7_NZ_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR7_NZ_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi
stxa %l7, [%g0] ASI_LSU_CONTROL
thr7_transfer_to_priv_code:
setx thr7_priv_code_begin, %g1, %g2
wrhpr %g0, 0x000, %hpstate
.xword THR_0_PARTID, THR_1_PARTID, THR_2_PARTID, THR_3_PARTID
.xword THR_4_PARTID, THR_5_PARTID, THR_6_PARTID, THR_7_PARTID
!#*****************************************************************************************
SECTION .HPTRAPS_EXT_SECT TEXT_VA=HPTRAPS_EXT_TEXT_PA, DATA_VA=HPTRAPS_EXT_DATA_PA
.global ext_trap_0x64_begin
.global function_tsb_ptr_calc
setx ASI_IMMU_TAG_ACCESS_VAL, %l0, %l1
ldxa [%l1] ASI_IMMU_TAG_REG, %g2 !# %g2 = VA + CTX
and %g2, %l1, %g3 !# %g3 = context
and %g2, %l1, %g1 !# %g1 = VA
brnz %g3, walk_nonzero_tsb
setx ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0, %l0, %l1
ldxa [%l1] ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g2 !# %g2 = TSB config
call function_tsb_ptr_calc
setx ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1, %l0, %l1
ldxa [%l1] ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g2
call function_tsb_ptr_calc
setx ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2, %l0, %l1
ldxa [%l1] ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g2
call function_tsb_ptr_calc
setx ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3, %l0, %l1
ldxa [%l1] ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g2
call function_tsb_ptr_calc
setx ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0, %l0, %l1
ldxa [%l1] ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g2
call function_tsb_ptr_calc
setx ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1, %l0, %l1
ldxa [%l1] ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g2
call function_tsb_ptr_calc
setx ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2, %l0, %l1
ldxa [%l1] ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g2
call function_tsb_ptr_calc
setx ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3, %l0, %l1
ldxa [%l1] ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g2
call function_tsb_ptr_calc
and %g2, %l0, %l3 !# %l3 = tsb size
setx tsb_base_mask, %l0, %l2
ldx [%l2], %l4 !# %l4 = TSB_base_upper mask
and %g2, %l4, %l4 !# %l4 = TSB_base_upper
srlx %l2, 4, %l1 !# %l1 = page size
setx tsb_va_8k_mask, %l0, %l5
setx tsb_va_64k_mask, %l0, %l5
setx tsb_va_4m_mask, %l0, %l5
setx tsb_va_256m_mask, %l0, %l5
ldx [%l5], %l0 !# %l0 = va mask
srlx %l0, %l6, %l0 !# %l0 = TSB_base_lower
add %l4, %l0, %l0 !# %l0 = TSB pointer
ldx [%l0], %l2 !# %l2 = tte_tag
ldx [%l0+8], %l6 !# %l6 = tte_data
srlx %g1, 22, %l0 !# %l0 = shifted VA
setx ASI_PRIMARY_CONTEXT_0_REG_VAL, %l0, %l1
ldxa [%l1] ASI_PRIMARY_CONTEXT_REG, %l1
sllx %l1, 48, %l1 !# %l1 = shifted context
brz %l0, found_matched_tte
wr %g0, ASI_CORE_ID, %asi
ldxa [ASI_CORE_ID_VA] %asi, %l7
and %l7, 7, %l7 !# %l7 = TID
setx phy_offset_list, %l0, %l2
ldx [%l2], %l2 !# %l2 = Phy Offset
stxa %l6, [%l1] ASI_ITLB_DATA_IN
.xword 0x000000ffffffe000
.xword 0x000000ffffffc000
.xword 0x000000ffffff8000
.xword 0x000000ffffff0000
.xword 0x000000fffffe0000
.xword 0x000000fffffc0000
.xword 0x000000fffff80000
.xword 0x000000fffff00000
.xword 0x000000ffffe00000
.xword 0x000000ffffc00000
.xword 0x000000ffff800000
.xword 0x000000ffff000000
.xword 0x000000fffe000000
.xword 0x000000fffc000000
.xword 0x000000fff8000000
.xword 0x000000fff0000000
.xword 0x00000000003fe000
.xword 0x00000000007fe000
.xword 0x0000000000ffe000
.xword 0x0000000001ffe000
.xword 0x0000000003ffe000
.xword 0x0000000007ffe000
.xword 0x000000000fffe000
.xword 0x000000001fffe000
.xword 0x000000003fffe000
.xword 0x000000007fffe000
.xword 0x00000000ffffe000
.xword 0x00000001ffffe000
.xword 0x00000003ffffe000
.xword 0x00000007ffffe000
.xword 0x0000000fffffe000
.xword 0x0000001fffffe000
.xword 0x0000000001ff0000
.xword 0x0000000003ff0000
.xword 0x0000000007ff0000
.xword 0x000000000fff0000
.xword 0x000000001fff0000
.xword 0x000000003fff0000
.xword 0x000000007fff0000
.xword 0x00000000ffff0000
.xword 0x00000001ffff0000
.xword 0x00000003ffff0000
.xword 0x00000007ffff0000
.xword 0x0000000fffff0000
.xword 0x0000001fffff0000
.xword 0x0000003fffff0000
.xword 0x0000007fffff0000
.xword 0x000000ffffff0000
.xword 0x000000007fc00000
.xword 0x00000000ffc00000
.xword 0x00000001ffc00000
.xword 0x00000003ffc00000
.xword 0x00000007ffc00000
.xword 0x0000000fffc00000
.xword 0x0000001fffc00000
.xword 0x0000003fffc00000
.xword 0x0000007fffc00000
.xword 0x000000ffffc00000
.xword 0x000001ffffc00000
.xword 0x000003ffffc00000
.xword 0x000007ffffc00000
.xword 0x00000fffffc00000
.xword 0x00001fffffc00000
.xword 0x00003fffffc00000
.xword 0x0000001fe0000000
.xword 0x0000003fe0000000
.xword 0x0000007fe0000000
.xword 0x000000ffe0000000
.xword 0x000001ffe0000000
.xword 0x000003ffe0000000
.xword 0x000007ffe0000000
.xword 0x00000fffe0000000
.xword 0x00001fffe0000000
.xword 0x00003fffe0000000
.xword 0x00007fffe0000000
.xword 0x0000ffffe0000000
.xword 0x0001ffffe0000000
.xword 0x0003ffffe0000000
.xword 0x0007ffffe0000000
.xword 0x000fffffe0000000
!#*****************************************************************************************
SECTION .THR0_PRIV_SECT TEXT_VA=THR0_PRIV_TEXT_VA
TTE_Context = THR0_PCONTEXT_0,
.global thr0_priv_code_begin
setx THR0_PTRAP_TEXT_VA, %l0, %l1
setx thr0_user_code_begin_4v000, %l0, %l1
!#*****************************************************************************************
SECTION .THR1_PRIV_SECT TEXT_VA=THR1_PRIV_TEXT_VA
TTE_Context = THR1_PCONTEXT_0,
.global thr1_priv_code_begin
setx THR1_PTRAP_TEXT_VA, %l0, %l1
setx thr1_user_code_begin_4v000, %l0, %l1
!#*****************************************************************************************
SECTION .THR2_PRIV_SECT TEXT_VA=THR2_PRIV_TEXT_VA
TTE_Context = THR2_PCONTEXT_0,
.global thr2_priv_code_begin
setx THR2_PTRAP_TEXT_VA, %l0, %l1
setx thr2_user_code_begin_4v000, %l0, %l1
!#*****************************************************************************************
SECTION .THR3_PRIV_SECT TEXT_VA=THR3_PRIV_TEXT_VA
TTE_Context = THR3_PCONTEXT_0,
.global thr3_priv_code_begin
setx THR3_PTRAP_TEXT_VA, %l0, %l1
setx thr3_user_code_begin_4v000, %l0, %l1
!#*****************************************************************************************
SECTION .THR4_PRIV_SECT TEXT_VA=THR4_PRIV_TEXT_VA
TTE_Context = THR4_PCONTEXT_0,
.global thr4_priv_code_begin
setx THR4_PTRAP_TEXT_VA, %l0, %l1
setx thr4_user_code_begin_4v000, %l0, %l1
!#*****************************************************************************************
SECTION .THR5_PRIV_SECT TEXT_VA=THR5_PRIV_TEXT_VA
TTE_Context = THR5_PCONTEXT_0,
.global thr5_priv_code_begin
setx THR5_PTRAP_TEXT_VA, %l0, %l1
setx thr5_user_code_begin_4v000, %l0, %l1
!#*****************************************************************************************
SECTION .THR6_PRIV_SECT TEXT_VA=THR6_PRIV_TEXT_VA
TTE_Context = THR6_PCONTEXT_0,
.global thr6_priv_code_begin
setx THR6_PTRAP_TEXT_VA, %l0, %l1
setx thr6_user_code_begin_4v000, %l0, %l1
!#*****************************************************************************************
SECTION .THR7_PRIV_SECT TEXT_VA=THR7_PRIV_TEXT_VA
TTE_Context = THR7_PCONTEXT_0,
.global thr7_priv_code_begin
setx THR7_PTRAP_TEXT_VA, %l0, %l1
setx thr7_user_code_begin_4v000, %l0, %l1
!#*****************************************************************************************
SECTION .THR0_TRAPS TEXT_VA=THR0_PTRAP_TEXT_VA
!#*****************************************************************************************
SECTION .THR1_TRAPS TEXT_VA=THR1_PTRAP_TEXT_VA
!#*****************************************************************************************
SECTION .THR2_TRAPS TEXT_VA=THR2_PTRAP_TEXT_VA
!#*****************************************************************************************
SECTION .THR3_TRAPS TEXT_VA=THR3_PTRAP_TEXT_VA
!#*****************************************************************************************
SECTION .THR4_TRAPS TEXT_VA=THR4_PTRAP_TEXT_VA
!#*****************************************************************************************
SECTION .THR5_TRAPS TEXT_VA=THR5_PTRAP_TEXT_VA
!#*****************************************************************************************
SECTION .THR6_TRAPS TEXT_VA=THR6_PTRAP_TEXT_VA
!#*****************************************************************************************
SECTION .THR7_TRAPS TEXT_VA=THR7_PTRAP_TEXT_VA
!#*****************************************************************************************
SECTION .HTRAPS TEXT_VA=HPTRAP_TEXT_PA
setx ext_trap_0x64_begin, %l0, %l1
!#*****************************************************************************************
SECTION .Thr0_User_Text_4v000 TEXT_VA=THR0_USER_TEXT_4V_VA000
Name = .Thr0_User_Text_4v000,
VA = THR0_USER_TEXT_4V_VA000,
RA = THR0_USER_TEXT_4V_RA000,
PA = THR0_USER_TEXT_4V_PA000,
TTE_Context = THR0_PCONTEXT_0,
end_label = Thr0_User_text_4v000_end,
.global thr0_user_code_begin_4v000
thr0_user_code_begin_4v000:
setx THR0_END_PAGE008, %l0, %l4
setx thr0_user_code_begin_4v001, %l0, %l5
Thr0_User_text_4v000_end:
SECTION .Thr0_User_Data_4v008 DATA_VA=THR0_USER_DATA_4V_VA008
Name = .Thr0_User_Data_4v008,
VA = THR0_USER_DATA_4V_VA008,
RA = THR0_USER_DATA_4V_RA008,
PA = THR0_USER_DATA_4V_PA008,
TTE_Context = THR0_PCONTEXT_0,
Name = .Thr0_User_Data_4v008,
PA = THR0_USER_DATA_4V_PA008_8K,
.global thr0_user_data_end_4v008
thr0_user_data_end_4v008:
SECTION .Thr0_User_Data_4v010 DATA_VA=THR0_USER_DATA_4V_VA010
Name = .Thr0_User_Data_4v010,
VA = THR0_USER_DATA_4V_VA010,
RA = THR0_USER_DATA_4V_RA010,
PA = THR0_USER_DATA_4V_PA010,
TTE_Context = THR0_PCONTEXT_0,
.global thr0_user_data_begin_4v010
.global thr0_user_data_end_4v010
thr0_user_data_begin_4v010:
!#*****************************************************************************************
SECTION .Thr0_User_Text_4v001 TEXT_VA=THR0_USER_TEXT_4V_VA001
Name = .Thr0_User_Text_4v001,
VA = THR0_USER_TEXT_4V_VA001,
RA = THR0_USER_TEXT_4V_RA001,
PA = THR0_USER_TEXT_4V_PA001,
TTE_Context = THR0_PCONTEXT_0,
.global thr0_user_code_begin_4v001
thr0_user_code_begin_4v001:
setx THR0_END_PAGE009, %l0, %l5
SECTION .Thr0_User_Data_4v009 DATA_VA=THR0_USER_DATA_4V_VA009
Name = .Thr0_User_Data_4v009,
VA = THR0_USER_DATA_4V_VA009,
RA = THR0_USER_DATA_4V_RA009,
PA = THR0_USER_DATA_4V_PA009,
TTE_Context = THR0_PCONTEXT_0,
Name = .Thr0_User_Data_4v009,
PA = THR0_USER_DATA_4V_PA009_8K,
.global thr0_user_data_end_4v009
thr0_user_data_end_4v009:
SECTION .Thr0_User_Data_4v011 DATA_VA=THR0_USER_DATA_4V_VA011
Name = .Thr0_User_Data_4v011,
VA = THR0_USER_DATA_4V_VA011,
RA = THR0_USER_DATA_4V_RA011,
PA = THR0_USER_DATA_4V_PA011,
TTE_Context = THR0_PCONTEXT_0,
.global thr0_user_data_begin_4v011
thr0_user_data_begin_4v011:
!#*****************************************************************************************
SECTION .Thr1_User_Text_4v000 TEXT_VA=THR1_USER_TEXT_4V_VA000
Name = .Thr1_User_Text_4v000,
VA = THR1_USER_TEXT_4V_VA000,
RA = THR1_USER_TEXT_4V_RA000,
PA = THR1_USER_TEXT_4V_PA000,
TTE_Context = THR1_PCONTEXT_0,
.global thr1_user_code_begin_4v000
thr1_user_code_begin_4v000:
setx THR1_END_PAGE008, %l0, %l4
setx thr1_user_code_begin_4v001, %l0, %l5
SECTION .Thr1_User_Data_4v008 DATA_VA=THR1_USER_DATA_4V_VA008
Name = .Thr1_User_Data_4v008,
VA = THR1_USER_DATA_4V_VA008,
RA = THR1_USER_DATA_4V_RA008,
PA = THR1_USER_DATA_4V_PA008,
TTE_Context = THR1_PCONTEXT_0,
.global thr1_user_data_begin_4v008
thr1_user_data_begin_4v008:
Name = .Thr1_User_Data_4v008,
PA = THR1_USER_DATA_4V_PA008_8K,
.global thr1_user_data_end_4v008
thr1_user_data_end_4v008:
SECTION .Thr1_User_Data_4v010 DATA_VA=THR1_USER_DATA_4V_VA010
Name = .Thr1_User_Data_4v010,
VA = THR1_USER_DATA_4V_VA010,
RA = THR1_USER_DATA_4V_RA010,
PA = THR1_USER_DATA_4V_PA010,
TTE_Context = THR1_PCONTEXT_0,
.global thr1_user_data_begin_4v010
.global thr1_user_data_end_4v010
thr1_user_data_begin_4v010:
!#*****************************************************************************************
SECTION .Thr1_User_Text_4v001 TEXT_VA=THR1_USER_TEXT_4V_VA001
Name = .Thr1_User_Text_4v001,
VA = THR1_USER_TEXT_4V_VA001,
RA = THR1_USER_TEXT_4V_RA001,
PA = THR1_USER_TEXT_4V_PA001,
TTE_Context = THR1_PCONTEXT_0,
.global thr1_user_code_begin_4v001
thr1_user_code_begin_4v001:
setx THR1_END_PAGE009, %l0, %l5
SECTION .Thr1_User_Data_4v009 DATA_VA=THR1_USER_DATA_4V_VA009
Name = .Thr1_User_Data_4v009,
VA = THR1_USER_DATA_4V_VA009,
RA = THR1_USER_DATA_4V_RA009,
PA = THR1_USER_DATA_4V_PA009,
TTE_Context = THR1_PCONTEXT_0,
.global thr1_user_data_begin_4v009
thr1_user_data_begin_4v009:
Name = .Thr1_User_Data_4v009,
PA = THR1_USER_DATA_4V_PA009_8K,
.global thr1_user_data_end_4v009
thr1_user_data_end_4v009:
SECTION .Thr1_User_Data_4v011 DATA_VA=THR1_USER_DATA_4V_VA011
Name = .Thr1_User_Data_4v011,
VA = THR1_USER_DATA_4V_VA011,
RA = THR1_USER_DATA_4V_RA011,
PA = THR1_USER_DATA_4V_PA011,
TTE_Context = THR1_PCONTEXT_0,
.global thr1_user_data_begin_4v011
thr1_user_data_begin_4v011:
!#*****************************************************************************************
SECTION .Thr2_User_Text_4v000 TEXT_VA=THR2_USER_TEXT_4V_VA000
Name = .Thr2_User_Text_4v000,
VA = THR2_USER_TEXT_4V_VA000,
RA = THR2_USER_TEXT_4V_RA000,
PA = THR2_USER_TEXT_4V_PA000,
TTE_Context = THR2_PCONTEXT_0,
.global thr2_user_code_begin_4v000
thr2_user_code_begin_4v000:
setx THR2_END_PAGE008, %l0, %l4
setx thr2_user_code_begin_4v001, %l0, %l5
SECTION .Thr2_User_Data_4v008 DATA_VA=THR2_USER_DATA_4V_VA008
Name = .Thr2_User_Data_4v008,
VA = THR2_USER_DATA_4V_VA008,
RA = THR2_USER_DATA_4V_RA008,
PA = THR2_USER_DATA_4V_PA008,
TTE_Context = THR2_PCONTEXT_0,
.global thr2_user_data_begin_4v008
thr2_user_data_begin_4v008:
Name = .Thr2_User_Data_4v008,
PA = THR2_USER_DATA_4V_PA008_8K,
.global thr2_user_data_end_4v008
thr2_user_data_end_4v008:
SECTION .Thr2_User_Data_4v010 DATA_VA=THR2_USER_DATA_4V_VA010
Name = .Thr2_User_Data_4v010,
VA = THR2_USER_DATA_4V_VA010,
RA = THR2_USER_DATA_4V_RA010,
PA = THR2_USER_DATA_4V_PA010,
TTE_Context = THR2_PCONTEXT_0,
.global thr2_user_data_begin_4v010
.global thr2_user_data_end_4v010
thr2_user_data_begin_4v010:
!#*****************************************************************************************
SECTION .Thr2_User_Text_4v001 TEXT_VA=THR2_USER_TEXT_4V_VA001
Name = .Thr2_User_Text_4v001,
VA = THR2_USER_TEXT_4V_VA001,
RA = THR2_USER_TEXT_4V_RA001,
PA = THR2_USER_TEXT_4V_PA001,
TTE_Context = THR2_PCONTEXT_0,
.global thr2_user_code_begin_4v001
thr2_user_code_begin_4v001:
setx THR2_END_PAGE009, %l0, %l5
SECTION .Thr2_User_Data_4v009 DATA_VA=THR2_USER_DATA_4V_VA009
Name = .Thr2_User_Data_4v009,
VA = THR2_USER_DATA_4V_VA009,
RA = THR2_USER_DATA_4V_RA009,
PA = THR2_USER_DATA_4V_PA009,
TTE_Context = THR2_PCONTEXT_0,
.global thr2_user_data_begin_4v009
thr2_user_data_begin_4v009:
Name = .Thr2_User_Data_4v009,
PA = THR2_USER_DATA_4V_PA009_8K,
.global thr2_user_data_end_4v009
thr2_user_data_end_4v009:
SECTION .Thr2_User_Data_4v011 DATA_VA=THR2_USER_DATA_4V_VA011
Name = .Thr2_User_Data_4v011,
VA = THR2_USER_DATA_4V_VA011,
RA = THR2_USER_DATA_4V_RA011,
PA = THR2_USER_DATA_4V_PA011,
TTE_Context = THR2_PCONTEXT_0,
.global thr2_user_data_begin_4v011
thr2_user_data_begin_4v011:
!#*****************************************************************************************
SECTION .Thr3_User_Text_4v000 TEXT_VA=THR3_USER_TEXT_4V_VA000
Name = .Thr3_User_Text_4v000,
VA = THR3_USER_TEXT_4V_VA000,
RA = THR3_USER_TEXT_4V_RA000,
PA = THR3_USER_TEXT_4V_PA000,
TTE_Context = THR3_PCONTEXT_0,
.global thr3_user_code_begin_4v000
thr3_user_code_begin_4v000:
setx THR3_END_PAGE008, %l0, %l4
setx thr3_user_code_begin_4v001, %l0, %l5
SECTION .Thr3_User_Data_4v008 DATA_VA=THR3_USER_DATA_4V_VA008
Name = .Thr3_User_Data_4v008,
VA = THR3_USER_DATA_4V_VA008,
RA = THR3_USER_DATA_4V_RA008,
PA = THR3_USER_DATA_4V_PA008,
TTE_Context = THR3_PCONTEXT_0,
.global thr3_user_data_begin_4v008
thr3_user_data_begin_4v008:
Name = .Thr3_User_Data_4v008,
PA = THR3_USER_DATA_4V_PA008_8K,
.global thr3_user_data_end_4v008
thr3_user_data_end_4v008:
SECTION .Thr3_User_Data_4v010 DATA_VA=THR3_USER_DATA_4V_VA010
Name = .Thr3_User_Data_4v010,
VA = THR3_USER_DATA_4V_VA010,
RA = THR3_USER_DATA_4V_RA010,
PA = THR3_USER_DATA_4V_PA010,
TTE_Context = THR3_PCONTEXT_0,
.global thr3_user_data_begin_4v010
.global thr3_user_data_end_4v010
thr3_user_data_begin_4v010:
!#*****************************************************************************************
SECTION .Thr3_User_Text_4v001 TEXT_VA=THR3_USER_TEXT_4V_VA001
Name = .Thr3_User_Text_4v001,
VA = THR3_USER_TEXT_4V_VA001,
RA = THR3_USER_TEXT_4V_RA001,
PA = THR3_USER_TEXT_4V_PA001,
TTE_Context = THR3_PCONTEXT_0,
.global thr3_user_code_begin_4v001
thr3_user_code_begin_4v001:
setx THR3_END_PAGE009, %l0, %l5
SECTION .Thr3_User_Data_4v009 DATA_VA=THR3_USER_DATA_4V_VA009
Name = .Thr3_User_Data_4v009,
VA = THR3_USER_DATA_4V_VA009,
RA = THR3_USER_DATA_4V_RA009,
PA = THR3_USER_DATA_4V_PA009,
TTE_Context = THR3_PCONTEXT_0,
.global thr3_user_data_begin_4v009
thr3_user_data_begin_4v009:
Name = .Thr3_User_Data_4v009,
PA = THR3_USER_DATA_4V_PA009_8K,
.global thr3_user_data_end_4v009
thr3_user_data_end_4v009:
SECTION .Thr3_User_Data_4v011 DATA_VA=THR3_USER_DATA_4V_VA011
Name = .Thr3_User_Data_4v011,
VA = THR3_USER_DATA_4V_VA011,
RA = THR3_USER_DATA_4V_RA011,
PA = THR3_USER_DATA_4V_PA011,
TTE_Context = THR3_PCONTEXT_0,
.global thr3_user_data_begin_4v011
thr3_user_data_begin_4v011:
!#*****************************************************************************************
SECTION .Thr4_User_Text_4v000 TEXT_VA=THR4_USER_TEXT_4V_VA000
Name = .Thr4_User_Text_4v000,
VA = THR4_USER_TEXT_4V_VA000,
RA = THR4_USER_TEXT_4V_RA000,
PA = THR4_USER_TEXT_4V_PA000,
TTE_Context = THR4_PCONTEXT_0,
.global thr4_user_code_begin_4v000
thr4_user_code_begin_4v000:
setx THR4_END_PAGE008, %l0, %l4
setx thr4_user_code_begin_4v001, %l0, %l5
SECTION .Thr4_User_Data_4v008 DATA_VA=THR4_USER_DATA_4V_VA008
Name = .Thr4_User_Data_4v008,
VA = THR4_USER_DATA_4V_VA008,
RA = THR4_USER_DATA_4V_RA008,
PA = THR4_USER_DATA_4V_PA008,
TTE_Context = THR4_PCONTEXT_0,
.global thr4_user_data_begin_4v008
thr4_user_data_begin_4v008:
Name = .Thr4_User_Data_4v008,
PA = THR4_USER_DATA_4V_PA008_8K,
.global thr4_user_data_end_4v008
thr4_user_data_end_4v008:
SECTION .Thr4_User_Data_4v010 DATA_VA=THR4_USER_DATA_4V_VA010
Name = .Thr4_User_Data_4v010,
VA = THR4_USER_DATA_4V_VA010,
RA = THR4_USER_DATA_4V_RA010,
PA = THR4_USER_DATA_4V_PA010,
TTE_Context = THR4_PCONTEXT_0,
.global thr4_user_data_begin_4v010
.global thr4_user_data_end_4v010
thr4_user_data_begin_4v010:
!#*****************************************************************************************
SECTION .Thr4_User_Text_4v001 TEXT_VA=THR4_USER_TEXT_4V_VA001
Name = .Thr4_User_Text_4v001,
VA = THR4_USER_TEXT_4V_VA001,
RA = THR4_USER_TEXT_4V_RA001,
PA = THR4_USER_TEXT_4V_PA001,
TTE_Context = THR4_PCONTEXT_0,
.global thr4_user_code_begin_4v001
thr4_user_code_begin_4v001:
setx THR4_END_PAGE009, %l0, %l5
SECTION .Thr4_User_Data_4v009 DATA_VA=THR4_USER_DATA_4V_VA009
Name = .Thr4_User_Data_4v009,
VA = THR4_USER_DATA_4V_VA009,
RA = THR4_USER_DATA_4V_RA009,
PA = THR4_USER_DATA_4V_PA009,
TTE_Context = THR4_PCONTEXT_0,
.global thr4_user_data_begin_4v009
thr4_user_data_begin_4v009:
Name = .Thr4_User_Data_4v009,
PA = THR4_USER_DATA_4V_PA009_8K,
.global thr4_user_data_end_4v009
thr4_user_data_end_4v009:
SECTION .Thr4_User_Data_4v011 DATA_VA=THR4_USER_DATA_4V_VA011
Name = .Thr4_User_Data_4v011,
VA = THR4_USER_DATA_4V_VA011,
RA = THR4_USER_DATA_4V_RA011,
PA = THR4_USER_DATA_4V_PA011,
TTE_Context = THR4_PCONTEXT_0,
.global thr4_user_data_begin_4v011
thr4_user_data_begin_4v011:
!#*****************************************************************************************
SECTION .Thr5_User_Text_4v000 TEXT_VA=THR5_USER_TEXT_4V_VA000
Name = .Thr5_User_Text_4v000,
VA = THR5_USER_TEXT_4V_VA000,
RA = THR5_USER_TEXT_4V_RA000,
PA = THR5_USER_TEXT_4V_PA000,
TTE_Context = THR5_PCONTEXT_0,
.global thr5_user_code_begin_4v000
thr5_user_code_begin_4v000:
setx THR5_END_PAGE008, %l0, %l4
setx thr5_user_code_begin_4v001, %l0, %l5
SECTION .Thr5_User_Data_4v008 DATA_VA=THR5_USER_DATA_4V_VA008
Name = .Thr5_User_Data_4v008,
VA = THR5_USER_DATA_4V_VA008,
RA = THR5_USER_DATA_4V_RA008,
PA = THR5_USER_DATA_4V_PA008,
TTE_Context = THR5_PCONTEXT_0,
.global thr5_user_data_begin_4v008
thr5_user_data_begin_4v008:
Name = .Thr5_User_Data_4v008,
PA = THR5_USER_DATA_4V_PA008_8K,
.global thr5_user_data_end_4v008
thr5_user_data_end_4v008:
SECTION .Thr5_User_Data_4v010 DATA_VA=THR5_USER_DATA_4V_VA010
Name = .Thr5_User_Data_4v010,
VA = THR5_USER_DATA_4V_VA010,
RA = THR5_USER_DATA_4V_RA010,
PA = THR5_USER_DATA_4V_PA010,
TTE_Context = THR5_PCONTEXT_0,
.global thr5_user_data_begin_4v010
.global thr5_user_data_end_4v010
thr5_user_data_begin_4v010:
!#*****************************************************************************************
SECTION .Thr5_User_Text_4v001 TEXT_VA=THR5_USER_TEXT_4V_VA001
Name = .Thr5_User_Text_4v001,
VA = THR5_USER_TEXT_4V_VA001,
RA = THR5_USER_TEXT_4V_RA001,
PA = THR5_USER_TEXT_4V_PA001,
TTE_Context = THR5_PCONTEXT_0,
.global thr5_user_code_begin_4v001
thr5_user_code_begin_4v001:
setx THR5_END_PAGE009, %l0, %l5
SECTION .Thr5_User_Data_4v009 DATA_VA=THR5_USER_DATA_4V_VA009
Name = .Thr5_User_Data_4v009,
VA = THR5_USER_DATA_4V_VA009,
RA = THR5_USER_DATA_4V_RA009,
PA = THR5_USER_DATA_4V_PA009,
TTE_Context = THR5_PCONTEXT_0,
.global thr5_user_data_begin_4v009
thr5_user_data_begin_4v009:
Name = .Thr5_User_Data_4v009,
PA = THR5_USER_DATA_4V_PA009_8K,
.global thr5_user_data_end_4v009
thr5_user_data_end_4v009:
SECTION .Thr5_User_Data_4v011 DATA_VA=THR5_USER_DATA_4V_VA011
Name = .Thr5_User_Data_4v011,
VA = THR5_USER_DATA_4V_VA011,
RA = THR5_USER_DATA_4V_RA011,
PA = THR5_USER_DATA_4V_PA011,
TTE_Context = THR5_PCONTEXT_0,
.global thr5_user_data_begin_4v011
thr5_user_data_begin_4v011:
!#*****************************************************************************************
SECTION .Thr6_User_Text_4v000 TEXT_VA=THR6_USER_TEXT_4V_VA000
Name = .Thr6_User_Text_4v000,
VA = THR6_USER_TEXT_4V_VA000,
RA = THR6_USER_TEXT_4V_RA000,
PA = THR6_USER_TEXT_4V_PA000,
TTE_Context = THR6_PCONTEXT_0,
.global thr6_user_code_begin_4v000
thr6_user_code_begin_4v000:
setx THR6_END_PAGE008, %l0, %l4
setx thr6_user_code_begin_4v001, %l0, %l5
SECTION .Thr6_User_Data_4v008 DATA_VA=THR6_USER_DATA_4V_VA008
Name = .Thr6_User_Data_4v008,
VA = THR6_USER_DATA_4V_VA008,
RA = THR6_USER_DATA_4V_RA008,
PA = THR6_USER_DATA_4V_PA008,
TTE_Context = THR6_PCONTEXT_0,
.global thr6_user_data_begin_4v008
thr6_user_data_begin_4v008:
Name = .Thr6_User_Data_4v008,
PA = THR6_USER_DATA_4V_PA008_8K,
.global thr6_user_data_end_4v008
thr6_user_data_end_4v008:
SECTION .Thr6_User_Data_4v010 DATA_VA=THR6_USER_DATA_4V_VA010
Name = .Thr6_User_Data_4v010,
VA = THR6_USER_DATA_4V_VA010,
RA = THR6_USER_DATA_4V_RA010,
PA = THR6_USER_DATA_4V_PA010,
TTE_Context = THR6_PCONTEXT_0,
.global thr6_user_data_begin_4v010
.global thr6_user_data_end_4v010
thr6_user_data_begin_4v010:
!#*****************************************************************************************
SECTION .Thr6_User_Text_4v001 TEXT_VA=THR6_USER_TEXT_4V_VA001
Name = .Thr6_User_Text_4v001,
VA = THR6_USER_TEXT_4V_VA001,
RA = THR6_USER_TEXT_4V_RA001,
PA = THR6_USER_TEXT_4V_PA001,
TTE_Context = THR6_PCONTEXT_0,
.global thr6_user_code_begin_4v001
thr6_user_code_begin_4v001:
setx THR6_END_PAGE009, %l0, %l5
SECTION .Thr6_User_Data_4v009 DATA_VA=THR6_USER_DATA_4V_VA009
Name = .Thr6_User_Data_4v009,
VA = THR6_USER_DATA_4V_VA009,
RA = THR6_USER_DATA_4V_RA009,
PA = THR6_USER_DATA_4V_PA009,
TTE_Context = THR6_PCONTEXT_0,
.global thr6_user_data_begin_4v009
thr6_user_data_begin_4v009:
Name = .Thr6_User_Data_4v009,
PA = THR6_USER_DATA_4V_PA009_8K,
.global thr6_user_data_end_4v009
thr6_user_data_end_4v009:
SECTION .Thr6_User_Data_4v011 DATA_VA=THR6_USER_DATA_4V_VA011
Name = .Thr6_User_Data_4v011,
VA = THR6_USER_DATA_4V_VA011,
RA = THR6_USER_DATA_4V_RA011,
PA = THR6_USER_DATA_4V_PA011,
TTE_Context = THR6_PCONTEXT_0,
.global thr6_user_data_begin_4v011
thr6_user_data_begin_4v011:
!#*****************************************************************************************
SECTION .Thr7_User_Text_4v000 TEXT_VA=THR7_USER_TEXT_4V_VA000
Name = .Thr7_User_Text_4v000,
VA = THR7_USER_TEXT_4V_VA000,
RA = THR7_USER_TEXT_4V_RA000,
PA = THR7_USER_TEXT_4V_PA000,
TTE_Context = THR7_PCONTEXT_0,
.global thr7_user_code_begin_4v000
thr7_user_code_begin_4v000:
setx THR7_END_PAGE008, %l0, %l4
setx thr7_user_code_begin_4v001, %l0, %l5
SECTION .Thr7_User_Data_4v008 DATA_VA=THR7_USER_DATA_4V_VA008
Name = .Thr7_User_Data_4v008,
VA = THR7_USER_DATA_4V_VA008,
RA = THR7_USER_DATA_4V_RA008,
PA = THR7_USER_DATA_4V_PA008,
TTE_Context = THR7_PCONTEXT_0,
.global thr7_user_data_begin_4v008
thr7_user_data_begin_4v008:
Name = .Thr7_User_Data_4v008,
PA = THR7_USER_DATA_4V_PA008_8K,
.global thr7_user_data_end_4v008
thr7_user_data_end_4v008:
SECTION .Thr7_User_Data_4v010 DATA_VA=THR7_USER_DATA_4V_VA010
Name = .Thr7_User_Data_4v010,
VA = THR7_USER_DATA_4V_VA010,
RA = THR7_USER_DATA_4V_RA010,
PA = THR7_USER_DATA_4V_PA010,
TTE_Context = THR7_PCONTEXT_0,
.global thr7_user_data_begin_4v010
.global thr7_user_data_end_4v010
thr7_user_data_begin_4v010:
!#*****************************************************************************************
SECTION .Thr7_User_Text_4v001 TEXT_VA=THR7_USER_TEXT_4V_VA001
Name = .Thr7_User_Text_4v001,
VA = THR7_USER_TEXT_4V_VA001,
RA = THR7_USER_TEXT_4V_RA001,
PA = THR7_USER_TEXT_4V_PA001,
TTE_Context = THR7_PCONTEXT_0,
.global thr7_user_code_begin_4v001
thr7_user_code_begin_4v001:
setx THR7_END_PAGE009, %l0, %l5
SECTION .Thr7_User_Data_4v009 DATA_VA=THR7_USER_DATA_4V_VA009
Name = .Thr7_User_Data_4v009,
VA = THR7_USER_DATA_4V_VA009,
RA = THR7_USER_DATA_4V_RA009,
PA = THR7_USER_DATA_4V_PA009,
TTE_Context = THR7_PCONTEXT_0,
.global thr7_user_data_begin_4v009
thr7_user_data_begin_4v009:
Name = .Thr7_User_Data_4v009,
PA = THR7_USER_DATA_4V_PA009_8K,
.global thr7_user_data_end_4v009
thr7_user_data_end_4v009:
SECTION .Thr7_User_Data_4v011 DATA_VA=THR7_USER_DATA_4V_VA011
Name = .Thr7_User_Data_4v011,
VA = THR7_USER_DATA_4V_VA011,
RA = THR7_USER_DATA_4V_RA011,
PA = THR7_USER_DATA_4V_PA011,
TTE_Context = THR7_PCONTEXT_0,
.global thr7_user_data_begin_4v011
thr7_user_data_begin_4v011: