* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: mmu_mt_use_ctx1.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* ========== Copyright Header End ============================================
#define THR0_Z_CTX_TSB_CONFIG_0 0x8000000001000110
#define THR0_Z_CTX_TSB_CONFIG_1 0x8000000001010130
#define THR0_Z_CTX_TSB_CONFIG_2 0x8000000001020150
#define THR0_Z_CTX_TSB_CONFIG_3 0x8000000001030100
#define THR0_NZ_CTX_TSB_CONFIG_0 0x8000000001200130
#define THR0_NZ_CTX_TSB_CONFIG_1 0x8000000001210150
#define THR0_NZ_CTX_TSB_CONFIG_2 0x8000000001220100
#define THR0_NZ_CTX_TSB_CONFIG_3 0xa000000001230110
#define THR1_Z_CTX_TSB_CONFIG_0 0x8000000001040110
#define THR1_Z_CTX_TSB_CONFIG_1 0x8000000001050130
#define THR1_Z_CTX_TSB_CONFIG_2 0x8000000001060150
#define THR1_Z_CTX_TSB_CONFIG_3 0x8000000001070100
#define THR1_NZ_CTX_TSB_CONFIG_0 0x8000000001240100
#define THR1_NZ_CTX_TSB_CONFIG_1 0x8000000001250110
#define THR1_NZ_CTX_TSB_CONFIG_2 0x8000000001260130
#define THR1_NZ_CTX_TSB_CONFIG_3 0x8000000001270150
#define THR2_Z_CTX_TSB_CONFIG_0 0x8000000001080130
#define THR2_Z_CTX_TSB_CONFIG_1 0x8000000001090150
#define THR2_Z_CTX_TSB_CONFIG_2 0x80000000010a0100
#define THR2_Z_CTX_TSB_CONFIG_3 0x80000000010b0110
#define THR2_NZ_CTX_TSB_CONFIG_0 0x8000000001280150
#define THR2_NZ_CTX_TSB_CONFIG_1 0x8000000001290100
#define THR2_NZ_CTX_TSB_CONFIG_2 0x80000000012a0110
#define THR2_NZ_CTX_TSB_CONFIG_3 0x80000000012b0130
#define THR3_Z_CTX_TSB_CONFIG_0 0x80000000010c0130
#define THR3_Z_CTX_TSB_CONFIG_1 0x80000000010d0150
#define THR3_Z_CTX_TSB_CONFIG_2 0x80000000010e0100
#define THR3_Z_CTX_TSB_CONFIG_3 0x80000000010f0110
#define THR3_NZ_CTX_TSB_CONFIG_0 0x80000000012c0150
#define THR3_NZ_CTX_TSB_CONFIG_1 0x80000000012d0100
#define THR3_NZ_CTX_TSB_CONFIG_2 0x80000000012e0110
#define THR3_NZ_CTX_TSB_CONFIG_3 0x80000000012f0130
#define THR4_Z_CTX_TSB_CONFIG_0 0x8000000001100150
#define THR4_Z_CTX_TSB_CONFIG_1 0x8000000001110100
#define THR4_Z_CTX_TSB_CONFIG_2 0x8000000001120110
#define THR4_Z_CTX_TSB_CONFIG_3 0x8000000001130130
#define THR4_NZ_CTX_TSB_CONFIG_0 0x8000000001300150
#define THR4_NZ_CTX_TSB_CONFIG_1 0x8000000001310100
#define THR4_NZ_CTX_TSB_CONFIG_2 0x8000000001320110
#define THR4_NZ_CTX_TSB_CONFIG_3 0x8000000001330130
#define THR5_Z_CTX_TSB_CONFIG_0 0x8000000001140150
#define THR5_Z_CTX_TSB_CONFIG_1 0x8000000001150100
#define THR5_Z_CTX_TSB_CONFIG_2 0x8000000001160110
#define THR5_Z_CTX_TSB_CONFIG_3 0x8000000001170130
#define THR5_NZ_CTX_TSB_CONFIG_0 0x8000000001340100
#define THR5_NZ_CTX_TSB_CONFIG_1 0x8000000001350110
#define THR5_NZ_CTX_TSB_CONFIG_2 0x8000000001360130
#define THR5_NZ_CTX_TSB_CONFIG_3 0x8000000001370150
#define THR6_Z_CTX_TSB_CONFIG_0 0x8000000001180150
#define THR6_Z_CTX_TSB_CONFIG_1 0x8000000001190100
#define THR6_Z_CTX_TSB_CONFIG_2 0x80000000011a0110
#define THR6_Z_CTX_TSB_CONFIG_3 0x80000000011b0130
#define THR6_NZ_CTX_TSB_CONFIG_0 0x8000000001380130
#define THR6_NZ_CTX_TSB_CONFIG_1 0x8000000001390150
#define THR6_NZ_CTX_TSB_CONFIG_2 0x80000000013a0100
#define THR6_NZ_CTX_TSB_CONFIG_3 0x80000000013b0110
#define THR7_Z_CTX_TSB_CONFIG_0 0x80000000011c0110
#define THR7_Z_CTX_TSB_CONFIG_1 0x80000000011d0130
#define THR7_Z_CTX_TSB_CONFIG_2 0x80000000011e0150
#define THR7_Z_CTX_TSB_CONFIG_3 0x80000000011f0100
#define THR7_NZ_CTX_TSB_CONFIG_0 0x80000000013c0130
#define THR7_NZ_CTX_TSB_CONFIG_1 0x80000000013d0150
#define THR7_NZ_CTX_TSB_CONFIG_2 0x80000000013e0100
#define THR7_NZ_CTX_TSB_CONFIG_3 0x80000000013f0110
#define THR0_REAL_RANGE_0 0x8000080000000000
#define THR0_REAL_RANGE_1 0x8000400000000000
#define THR0_REAL_RANGE_2 0x8001000000000000
#define THR0_REAL_RANGE_3 0x8008000000000000
#define THR1_REAL_RANGE_0 0x8000080000000000
#define THR1_REAL_RANGE_1 0x8000400000000000
#define THR1_REAL_RANGE_2 0x8001000000000000
#define THR1_REAL_RANGE_3 0x8008000000000000
#define THR2_REAL_RANGE_0 0x8000080000000000
#define THR2_REAL_RANGE_1 0x8000400000000000
#define THR2_REAL_RANGE_2 0x8001000000000000
#define THR2_REAL_RANGE_3 0x8008000000000000
#define THR3_REAL_RANGE_0 0x8000080000000000
#define THR3_REAL_RANGE_1 0x8000400000000000
#define THR3_REAL_RANGE_2 0x8001000000000000
#define THR3_REAL_RANGE_3 0x8008000000000000
#define THR4_REAL_RANGE_0 0x8000080000000000
#define THR4_REAL_RANGE_1 0x8000400000000000
#define THR4_REAL_RANGE_2 0x8001000000000000
#define THR4_REAL_RANGE_3 0x8008000000000000
#define THR5_REAL_RANGE_0 0x8000080000000000
#define THR5_REAL_RANGE_1 0x8000400000000000
#define THR5_REAL_RANGE_2 0x8001000000000000
#define THR5_REAL_RANGE_3 0x8008000000000000
#define THR6_REAL_RANGE_0 0x8000080000000000
#define THR6_REAL_RANGE_1 0x8000400000000000
#define THR6_REAL_RANGE_2 0x8001000000000000
#define THR6_REAL_RANGE_3 0x8008000000000000
#define THR7_REAL_RANGE_0 0x8000080000000000
#define THR7_REAL_RANGE_1 0x8000400000000000
#define THR7_REAL_RANGE_2 0x8001000000000000
#define THR7_REAL_RANGE_3 0x8008000000000000
#define THR0_PHY_OFF_0 0x0000000080000000
#define THR0_PHY_OFF_1 0x0000000200000000
#define THR0_PHY_OFF_2 0x0000000800000000
#define THR0_PHY_OFF_3 0x0000004000000000
#define THR1_PHY_OFF_0 0x0000000080000000
#define THR1_PHY_OFF_1 0x0000000200000000
#define THR1_PHY_OFF_2 0x0000000800000000
#define THR1_PHY_OFF_3 0x0000004000000000
#define THR2_PHY_OFF_0 0x0000000080000000
#define THR2_PHY_OFF_1 0x0000000200000000
#define THR2_PHY_OFF_2 0x0000000800000000
#define THR2_PHY_OFF_3 0x0000004000000000
#define THR3_PHY_OFF_0 0x0000000080000000
#define THR3_PHY_OFF_1 0x0000000200000000
#define THR3_PHY_OFF_2 0x0000000800000000
#define THR3_PHY_OFF_3 0x0000004000000000
#define THR4_PHY_OFF_0 0x0000000080000000
#define THR4_PHY_OFF_1 0x0000000200000000
#define THR4_PHY_OFF_2 0x0000000800000000
#define THR4_PHY_OFF_3 0x0000004000000000
#define THR5_PHY_OFF_0 0x0000000080000000
#define THR5_PHY_OFF_1 0x0000000200000000
#define THR5_PHY_OFF_2 0x0000000800000000
#define THR5_PHY_OFF_3 0x0000004000000000
#define THR6_PHY_OFF_0 0x0000000080000000
#define THR6_PHY_OFF_1 0x0000000200000000
#define THR6_PHY_OFF_2 0x0000000800000000
#define THR6_PHY_OFF_3 0x0000004000000000
#define THR7_PHY_OFF_0 0x0000000080000000
#define THR7_PHY_OFF_1 0x0000000200000000
#define THR7_PHY_OFF_2 0x0000000800000000
#define THR7_PHY_OFF_3 0x0000004000000000
#define THR0_PCONTEXT_0 0x0c80
#define THR0_PCONTEXT_1 0x0565
#define THR0_SCONTEXT_0 0x0ca4
#define THR0_SCONTEXT_1 0x117b
#define THR1_PCONTEXT_0 0x1ef0
#define THR1_PCONTEXT_1 0x0565
#define THR1_SCONTEXT_0 0x1643
#define THR1_SCONTEXT_1 0x0806
#define THR2_PCONTEXT_0 0x1740
#define THR2_PCONTEXT_1 0x192b
#define THR2_SCONTEXT_0 0x1fb2
#define THR2_SCONTEXT_1 0x105d
#define THR3_PCONTEXT_0 0x15c2
#define THR3_PCONTEXT_1 0x1067
#define THR3_SCONTEXT_0 0x0d6f
#define THR3_SCONTEXT_1 0x1af3
#define THR4_PCONTEXT_0 0x0613
#define THR4_PCONTEXT_1 0x172e
#define THR4_SCONTEXT_0 0x12e4
#define THR4_SCONTEXT_1 0x0670
#define THR5_PCONTEXT_0 0x13dd
#define THR5_PCONTEXT_1 0x15c8
#define THR5_SCONTEXT_0 0x1cd9
#define THR5_SCONTEXT_1 0x1586
#define THR6_PCONTEXT_0 0x0c8a
#define THR6_PCONTEXT_1 0x19ac
#define THR6_SCONTEXT_0 0x18ab
#define THR6_SCONTEXT_1 0x1e47
#define THR7_PCONTEXT_0 0x0687
#define THR7_PCONTEXT_1 0x1d84
#define THR7_SCONTEXT_0 0x06bc
#define THR7_SCONTEXT_1 0x05a0
#define THR0_PTRAP_TEXT_VA 0x0000a7690000
#define THR0_PTRAP_TEXT_RA 0x0045b80000
#define THR0_PTRAP_TEXT_PA 0x0245b80000
#define THR1_PTRAP_TEXT_VA 0x0000a75b0000
#define THR1_PTRAP_TEXT_RA 0x00450f0000
#define THR1_PTRAP_TEXT_PA 0x02450f0000
#define THR2_PTRAP_TEXT_VA 0x0000a7800000
#define THR2_PTRAP_TEXT_RA 0x00452b0000
#define THR2_PTRAP_TEXT_PA 0x02452b0000
#define THR3_PTRAP_TEXT_VA 0x0000a74a0000
#define THR3_PTRAP_TEXT_RA 0x0045e60000
#define THR3_PTRAP_TEXT_PA 0x0245e60000
#define THR4_PTRAP_TEXT_VA 0x0000a73e0000
#define THR4_PTRAP_TEXT_RA 0x0045d20000
#define THR4_PTRAP_TEXT_PA 0x0245d20000
#define THR5_PTRAP_TEXT_VA 0x0000a79a0000
#define THR5_PTRAP_TEXT_RA 0x0045c60000
#define THR5_PTRAP_TEXT_PA 0x0245c60000
#define THR6_PTRAP_TEXT_VA 0x0000a7010000
#define THR6_PTRAP_TEXT_RA 0x0045260000
#define THR6_PTRAP_TEXT_PA 0x0245260000
#define THR7_PTRAP_TEXT_VA 0x0000a7cc0000
#define THR7_PTRAP_TEXT_RA 0x0045170000
#define THR7_PTRAP_TEXT_PA 0x0245170000
#define HV_RED_TEXT_PA 0x10000
#define HV_RED_DATA_PA 0x20000
#define HPTRAP_TEXT_PA 0x80000
#define HPTRAPS_EXT_TEXT_PA 0x90000
#define HPTRAPS_EXT_DATA_PA 0x98000
#define HP_GOOD_TRAP 0xa0
#define EXIT_GOOD ta P_GOOD_TRAP; nop
#define EXIT_BAD ta P_BAD_TRAP; nop
#define REALRANGE_LO_MASK 0x0000000007ffffff
#define REALRANGE_HI_MASK 0x003ffffff8000000
#define RANOTPA_MASK 0x100
#define TTE_RA_MASK 0x000000ffffffe000
#define PTRAP_DEMAP_ALL 0x10
#define HPTRAP_DEMAP_ALL 0x80
MIDAS_TSB thr0_z_ctx_tsb_0 THR0_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr0_z_ctx_tsb_1 THR0_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr0_z_ctx_tsb_2 THR0_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr0_z_ctx_tsb_3 THR0_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr0_nz_ctx_tsb_0 THR0_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr0_nz_ctx_tsb_1 THR0_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr0_nz_ctx_tsb_2 THR0_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr0_nz_ctx_tsb_3 THR0_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr1_z_ctx_tsb_0 THR1_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr1_z_ctx_tsb_1 THR1_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr1_z_ctx_tsb_2 THR1_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr1_z_ctx_tsb_3 THR1_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr1_nz_ctx_tsb_0 THR1_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr1_nz_ctx_tsb_1 THR1_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr1_nz_ctx_tsb_2 THR1_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr1_nz_ctx_tsb_3 THR1_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr2_z_ctx_tsb_0 THR2_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr2_z_ctx_tsb_1 THR2_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr2_z_ctx_tsb_2 THR2_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr2_z_ctx_tsb_3 THR2_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr2_nz_ctx_tsb_0 THR2_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr2_nz_ctx_tsb_1 THR2_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr2_nz_ctx_tsb_2 THR2_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr2_nz_ctx_tsb_3 THR2_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr3_z_ctx_tsb_0 THR3_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr3_z_ctx_tsb_1 THR3_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr3_z_ctx_tsb_2 THR3_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr3_z_ctx_tsb_3 THR3_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr3_nz_ctx_tsb_0 THR3_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr3_nz_ctx_tsb_1 THR3_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr3_nz_ctx_tsb_2 THR3_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr3_nz_ctx_tsb_3 THR3_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr4_z_ctx_tsb_0 THR4_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr4_z_ctx_tsb_1 THR4_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr4_z_ctx_tsb_2 THR4_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr4_z_ctx_tsb_3 THR4_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr4_nz_ctx_tsb_0 THR4_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr4_nz_ctx_tsb_1 THR4_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr4_nz_ctx_tsb_2 THR4_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr4_nz_ctx_tsb_3 THR4_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr5_z_ctx_tsb_0 THR5_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr5_z_ctx_tsb_1 THR5_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr5_z_ctx_tsb_2 THR5_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr5_z_ctx_tsb_3 THR5_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr5_nz_ctx_tsb_0 THR5_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr5_nz_ctx_tsb_1 THR5_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr5_nz_ctx_tsb_2 THR5_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr5_nz_ctx_tsb_3 THR5_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr6_z_ctx_tsb_0 THR6_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr6_z_ctx_tsb_1 THR6_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr6_z_ctx_tsb_2 THR6_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr6_z_ctx_tsb_3 THR6_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr6_nz_ctx_tsb_0 THR6_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr6_nz_ctx_tsb_1 THR6_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr6_nz_ctx_tsb_2 THR6_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr6_nz_ctx_tsb_3 THR6_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr7_z_ctx_tsb_0 THR7_Z_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr7_z_ctx_tsb_1 THR7_Z_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr7_z_ctx_tsb_2 THR7_Z_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr7_z_ctx_tsb_3 THR7_Z_CTX_TSB_CONFIG_3 ttefmt=sun4v
MIDAS_TSB thr7_nz_ctx_tsb_0 THR7_NZ_CTX_TSB_CONFIG_0 ttefmt=sun4v
MIDAS_TSB thr7_nz_ctx_tsb_1 THR7_NZ_CTX_TSB_CONFIG_1 ttefmt=sun4v
MIDAS_TSB thr7_nz_ctx_tsb_2 THR7_NZ_CTX_TSB_CONFIG_2 ttefmt=sun4v
MIDAS_TSB thr7_nz_ctx_tsb_3 THR7_NZ_CTX_TSB_CONFIG_3 ttefmt=sun4v
!#*****************************************************************************************
SECTION .RED_SEC TEXT_VA = 0xfffffffff0000000
wrhpr %l1, 0x820, %hpstate
! Power Management - set full power throttle mode ..
stxa %g2, [%g0] ASI_SPARC_PWR_MGMT
! load partition id to %l7
wr %g0, ASI_CORE_ID, %asi
ldxa [ASI_CORE_ID_VA] %asi, %l7
and %l7, %g1, %l7 ! %l7 has TID
setx thr0_red_handler, %l0, %l2
setx thr1_red_handler, %l0, %l2
setx thr2_red_handler, %l0, %l2
setx thr3_red_handler, %l0, %l2
setx thr4_red_handler, %l0, %l2
setx thr5_red_handler, %l0, %l2
setx thr6_red_handler, %l0, %l2
setx thr7_red_handler, %l0, %l2
!#*****************************************************************************************
SECTION .RED_EXT_SEC TEXT_VA = HV_RED_TEXT_PA, DATA_VA = HV_RED_DATA_PA
mov ASI_PARTITION_ID_VAL, %g1
stxa %g2, [%g1] ASI_PARTITION_ID
! set hyper trap base addr
setx HPTRAP_TEXT_PA, %l0, %l7
thr0_hred_context_config:
setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1
setx THR0_PCONTEXT_0, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi
setx THR0_PCONTEXT_1, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi
setx THR0_SCONTEXT_0, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi
setx THR0_SCONTEXT_1, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi
thr0_hred_physical_offset:
setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1
setx THR0_PHY_OFF_0, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi
setx THR0_PHY_OFF_1, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi
setx THR0_PHY_OFF_2, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi
setx THR0_PHY_OFF_3, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi
setx ASI_MMU_REAL_RANGE, %l1, %g1
setx THR0_REAL_RANGE_0, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi
setx THR0_REAL_RANGE_1, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi
setx THR0_REAL_RANGE_2, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi
setx THR0_REAL_RANGE_3, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi
mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3
thr0_hred_tsb_z_config_0:
setx THR0_Z_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR0_Z_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR0_Z_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR0_Z_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi
setx THR0_NZ_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR0_NZ_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR0_NZ_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR0_NZ_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi
stxa %l7, [%g0] ASI_LSU_CONTROL
thr0_transfer_to_priv_code:
setx Thr0_Priv_Sect_text_begin, %g1, %g2
wrhpr %g0, 0x000, %hpstate
mov ASI_PARTITION_ID_VAL, %g1
stxa %g2, [%g1] ASI_PARTITION_ID
! set hyper trap base addr
setx HPTRAP_TEXT_PA, %l0, %l7
thr1_hred_context_config:
setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1
setx THR1_PCONTEXT_0, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi
setx THR1_PCONTEXT_1, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi
setx THR1_SCONTEXT_0, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi
setx THR1_SCONTEXT_1, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi
thr1_hred_physical_offset:
setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1
setx THR1_PHY_OFF_0, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi
setx THR1_PHY_OFF_1, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi
setx THR1_PHY_OFF_2, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi
setx THR1_PHY_OFF_3, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi
setx ASI_MMU_REAL_RANGE, %l1, %g1
setx THR1_REAL_RANGE_0, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi
setx THR1_REAL_RANGE_1, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi
setx THR1_REAL_RANGE_2, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi
setx THR1_REAL_RANGE_3, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi
mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3
thr1_hred_tsb_z_config_0:
setx THR1_Z_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR1_Z_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR1_Z_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR1_Z_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi
setx THR1_NZ_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR1_NZ_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR1_NZ_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR1_NZ_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi
stxa %l7, [%g0] ASI_LSU_CONTROL
thr1_transfer_to_priv_code:
setx Thr1_Priv_Sect_text_begin, %g1, %g2
wrhpr %g0, 0x000, %hpstate
mov ASI_PARTITION_ID_VAL, %g1
stxa %g2, [%g1] ASI_PARTITION_ID
! set hyper trap base addr
setx HPTRAP_TEXT_PA, %l0, %l7
thr2_hred_context_config:
setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1
setx THR2_PCONTEXT_0, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi
setx THR2_PCONTEXT_1, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi
setx THR2_SCONTEXT_0, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi
setx THR2_SCONTEXT_1, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi
thr2_hred_physical_offset:
setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1
setx THR2_PHY_OFF_0, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi
setx THR2_PHY_OFF_1, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi
setx THR2_PHY_OFF_2, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi
setx THR2_PHY_OFF_3, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi
setx ASI_MMU_REAL_RANGE, %l1, %g1
setx THR2_REAL_RANGE_0, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi
setx THR2_REAL_RANGE_1, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi
setx THR2_REAL_RANGE_2, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi
setx THR2_REAL_RANGE_3, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi
mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3
thr2_hred_tsb_z_config_0:
setx THR2_Z_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR2_Z_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR2_Z_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR2_Z_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi
setx THR2_NZ_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR2_NZ_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR2_NZ_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR2_NZ_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi
stxa %l7, [%g0] ASI_LSU_CONTROL
thr2_transfer_to_priv_code:
setx Thr2_Priv_Sect_text_begin, %g1, %g2
wrhpr %g0, 0x000, %hpstate
mov ASI_PARTITION_ID_VAL, %g1
stxa %g2, [%g1] ASI_PARTITION_ID
! set hyper trap base addr
setx HPTRAP_TEXT_PA, %l0, %l7
thr3_hred_context_config:
setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1
setx THR3_PCONTEXT_0, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi
setx THR3_PCONTEXT_1, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi
setx THR3_SCONTEXT_0, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi
setx THR3_SCONTEXT_1, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi
thr3_hred_physical_offset:
setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1
setx THR3_PHY_OFF_0, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi
setx THR3_PHY_OFF_1, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi
setx THR3_PHY_OFF_2, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi
setx THR3_PHY_OFF_3, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi
setx ASI_MMU_REAL_RANGE, %l1, %g1
setx THR3_REAL_RANGE_0, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi
setx THR3_REAL_RANGE_1, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi
setx THR3_REAL_RANGE_2, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi
setx THR3_REAL_RANGE_3, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi
mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3
thr3_hred_tsb_z_config_0:
setx THR3_Z_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR3_Z_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR3_Z_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR3_Z_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi
setx THR3_NZ_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR3_NZ_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR3_NZ_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR3_NZ_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi
stxa %l7, [%g0] ASI_LSU_CONTROL
thr3_transfer_to_priv_code:
setx Thr3_Priv_Sect_text_begin, %g1, %g2
wrhpr %g0, 0x000, %hpstate
mov ASI_PARTITION_ID_VAL, %g1
stxa %g2, [%g1] ASI_PARTITION_ID
! set hyper trap base addr
setx HPTRAP_TEXT_PA, %l0, %l7
thr4_hred_context_config:
setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1
setx THR4_PCONTEXT_0, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi
setx THR4_PCONTEXT_1, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi
setx THR4_SCONTEXT_0, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi
setx THR4_SCONTEXT_1, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi
thr4_hred_physical_offset:
setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1
setx THR4_PHY_OFF_0, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi
setx THR4_PHY_OFF_1, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi
setx THR4_PHY_OFF_2, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi
setx THR4_PHY_OFF_3, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi
setx ASI_MMU_REAL_RANGE, %l1, %g1
setx THR4_REAL_RANGE_0, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi
setx THR4_REAL_RANGE_1, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi
setx THR4_REAL_RANGE_2, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi
setx THR4_REAL_RANGE_3, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi
mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3
thr4_hred_tsb_z_config_0:
setx THR4_Z_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR4_Z_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR4_Z_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR4_Z_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi
setx THR4_NZ_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR4_NZ_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR4_NZ_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR4_NZ_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi
stxa %l7, [%g0] ASI_LSU_CONTROL
thr4_transfer_to_priv_code:
setx Thr4_Priv_Sect_text_begin, %g1, %g2
wrhpr %g0, 0x000, %hpstate
mov ASI_PARTITION_ID_VAL, %g1
stxa %g2, [%g1] ASI_PARTITION_ID
! set hyper trap base addr
setx HPTRAP_TEXT_PA, %l0, %l7
thr5_hred_context_config:
setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1
setx THR5_PCONTEXT_0, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi
setx THR5_PCONTEXT_1, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi
setx THR5_SCONTEXT_0, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi
setx THR5_SCONTEXT_1, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi
thr5_hred_physical_offset:
setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1
setx THR5_PHY_OFF_0, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi
setx THR5_PHY_OFF_1, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi
setx THR5_PHY_OFF_2, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi
setx THR5_PHY_OFF_3, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi
setx ASI_MMU_REAL_RANGE, %l1, %g1
setx THR5_REAL_RANGE_0, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi
setx THR5_REAL_RANGE_1, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi
setx THR5_REAL_RANGE_2, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi
setx THR5_REAL_RANGE_3, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi
mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3
thr5_hred_tsb_z_config_0:
setx THR5_Z_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR5_Z_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR5_Z_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR5_Z_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi
setx THR5_NZ_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR5_NZ_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR5_NZ_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR5_NZ_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi
stxa %l7, [%g0] ASI_LSU_CONTROL
thr5_transfer_to_priv_code:
setx Thr5_Priv_Sect_text_begin, %g1, %g2
wrhpr %g0, 0x000, %hpstate
mov ASI_PARTITION_ID_VAL, %g1
stxa %g2, [%g1] ASI_PARTITION_ID
! set hyper trap base addr
setx HPTRAP_TEXT_PA, %l0, %l7
thr6_hred_context_config:
setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1
setx THR6_PCONTEXT_0, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi
setx THR6_PCONTEXT_1, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi
setx THR6_SCONTEXT_0, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi
setx THR6_SCONTEXT_1, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi
thr6_hred_physical_offset:
setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1
setx THR6_PHY_OFF_0, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi
setx THR6_PHY_OFF_1, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi
setx THR6_PHY_OFF_2, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi
setx THR6_PHY_OFF_3, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi
setx ASI_MMU_REAL_RANGE, %l1, %g1
setx THR6_REAL_RANGE_0, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi
setx THR6_REAL_RANGE_1, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi
setx THR6_REAL_RANGE_2, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi
setx THR6_REAL_RANGE_3, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi
mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3
thr6_hred_tsb_z_config_0:
setx THR6_Z_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR6_Z_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR6_Z_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR6_Z_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi
setx THR6_NZ_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR6_NZ_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR6_NZ_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR6_NZ_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi
stxa %l7, [%g0] ASI_LSU_CONTROL
thr6_transfer_to_priv_code:
setx Thr6_Priv_Sect_text_begin, %g1, %g2
wrhpr %g0, 0x000, %hpstate
mov ASI_PARTITION_ID_VAL, %g1
stxa %g2, [%g1] ASI_PARTITION_ID
! set hyper trap base addr
setx HPTRAP_TEXT_PA, %l0, %l7
thr7_hred_context_config:
setx ASI_PRIMARY_CONTEXT_REG, %l0, %g1
setx THR7_PCONTEXT_0, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_0_REG_VAL] %asi
setx THR7_PCONTEXT_1, %l0, %g1
stxa %g1, [ASI_PRIMARY_CONTEXT_1_REG_VAL] %asi
setx THR7_SCONTEXT_0, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_0_REG_VAL] %asi
setx THR7_SCONTEXT_1, %l0, %g1
stxa %g1, [ASI_SECONDARY_CONTEXT_1_REG_VAL] %asi
thr7_hred_physical_offset:
setx ASI_MMU_PHYSICAL_OFFSET, %l0, %g1
setx THR7_PHY_OFF_0, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_0] %asi
setx THR7_PHY_OFF_1, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_1] %asi
setx THR7_PHY_OFF_2, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_2] %asi
setx THR7_PHY_OFF_3, %l0, %l1
stxa %l1, [ASI_MMU_PHYSICAL_OFFSET_3] %asi
setx ASI_MMU_REAL_RANGE, %l1, %g1
setx THR7_REAL_RANGE_0, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_0] %asi
setx THR7_REAL_RANGE_1, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_1] %asi
setx THR7_REAL_RANGE_2, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_2] %asi
setx THR7_REAL_RANGE_3, %l0, %l1
stxa %l1, [ASI_MMU_REAL_RANGE_3] %asi
mov ASI_MMU_ZERO_CONTEXT_TSB_CONFIG, %g3
thr7_hred_tsb_z_config_0:
setx THR7_Z_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR7_Z_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR7_Z_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR7_Z_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_ZERO_CONTEXT_TSB_CONFIG_3] %asi
setx THR7_NZ_CTX_TSB_CONFIG_0, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_0] %asi
setx THR7_NZ_CTX_TSB_CONFIG_1, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_1] %asi
setx THR7_NZ_CTX_TSB_CONFIG_2, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_2] %asi
setx THR7_NZ_CTX_TSB_CONFIG_3, %g1, %g4
stxa %g4, [ASI_MMU_NONZERO_CONTEXT_TSB_CONFIG_3] %asi
stxa %l7, [%g0] ASI_LSU_CONTROL
thr7_transfer_to_priv_code:
setx Thr7_Priv_Sect_text_begin, %g1, %g2
wrhpr %g0, 0x000, %hpstate
.xword THR_0_PARTID, THR_1_PARTID, THR_2_PARTID, THR_3_PARTID
.xword THR_4_PARTID, THR_5_PARTID, THR_6_PARTID, THR_7_PARTID
!#*********************************************************************
SECTION .Thr0_Priv_Sect TEXT_VA=0x00142d6000
end_label = Thr0_Priv_Sect_text_end,
.global Thr0_Priv_Sect_text_begin
Thr0_Priv_Sect_text_begin:
setx THR0_PTRAP_TEXT_VA, %l0, %l1
setx Thr0_user_code_entry, %l0, %l1
!#*********************************************************************
SECTION .Thr1_Priv_Sect TEXT_VA=0x0014324000
end_label = Thr1_Priv_Sect_text_end,
.global Thr1_Priv_Sect_text_begin
Thr1_Priv_Sect_text_begin:
setx THR1_PTRAP_TEXT_VA, %l0, %l1
setx Thr1_user_code_entry, %l0, %l1
!#*********************************************************************
SECTION .Thr2_Priv_Sect TEXT_VA=0x001424a000
end_label = Thr2_Priv_Sect_text_end,
.global Thr2_Priv_Sect_text_begin
Thr2_Priv_Sect_text_begin:
setx THR2_PTRAP_TEXT_VA, %l0, %l1
setx Thr2_user_code_entry, %l0, %l1
!#*********************************************************************
SECTION .Thr3_Priv_Sect TEXT_VA=0x001430a000
end_label = Thr3_Priv_Sect_text_end,
.global Thr3_Priv_Sect_text_begin
Thr3_Priv_Sect_text_begin:
setx THR3_PTRAP_TEXT_VA, %l0, %l1
setx Thr3_user_code_entry, %l0, %l1
!#*********************************************************************
SECTION .Thr4_Priv_Sect TEXT_VA=0x0014226000
end_label = Thr4_Priv_Sect_text_end,
.global Thr4_Priv_Sect_text_begin
Thr4_Priv_Sect_text_begin:
setx THR4_PTRAP_TEXT_VA, %l0, %l1
setx Thr4_user_code_entry, %l0, %l1
!#*********************************************************************
SECTION .Thr5_Priv_Sect TEXT_VA=0x001432a000
end_label = Thr5_Priv_Sect_text_end,
.global Thr5_Priv_Sect_text_begin
Thr5_Priv_Sect_text_begin:
setx THR5_PTRAP_TEXT_VA, %l0, %l1
setx Thr5_user_code_entry, %l0, %l1
!#*********************************************************************
SECTION .Thr6_Priv_Sect TEXT_VA=0x0014374000
end_label = Thr6_Priv_Sect_text_end,
.global Thr6_Priv_Sect_text_begin
Thr6_Priv_Sect_text_begin:
setx THR6_PTRAP_TEXT_VA, %l0, %l1
setx Thr6_user_code_entry, %l0, %l1
!#*********************************************************************
SECTION .Thr7_Priv_Sect TEXT_VA=0x0014274000
end_label = Thr7_Priv_Sect_text_end,
.global Thr7_Priv_Sect_text_begin
Thr7_Priv_Sect_text_begin:
setx THR7_PTRAP_TEXT_VA, %l0, %l1
setx Thr7_user_code_entry, %l0, %l1
!#*********************************************************************
SECTION .Thr0_Ptrap_Sect TEXT_VA=THR0_PTRAP_TEXT_VA
end_label = Thr0_Ptrap_Sect_text_end,
thr1_ptrap_demap_all_entry:
Thr0_Ptrap_Sect_text_end:
!#*********************************************************************
SECTION .Thr1_Ptrap_Sect TEXT_VA=THR1_PTRAP_TEXT_VA
end_label = Thr1_Ptrap_Sect_text_end,
thr1_ptrap_demap_all_entry:
Thr1_Ptrap_Sect_text_end:
!#*********************************************************************
SECTION .Thr2_Ptrap_Sect TEXT_VA=THR2_PTRAP_TEXT_VA
end_label = Thr2_Ptrap_Sect_text_end,
thr1_ptrap_demap_all_entry:
Thr2_Ptrap_Sect_text_end:
!#*********************************************************************
SECTION .Thr3_Ptrap_Sect TEXT_VA=THR3_PTRAP_TEXT_VA
end_label = Thr3_Ptrap_Sect_text_end,
thr1_ptrap_demap_all_entry:
Thr3_Ptrap_Sect_text_end:
!#*********************************************************************
SECTION .Thr4_Ptrap_Sect TEXT_VA=THR4_PTRAP_TEXT_VA
end_label = Thr4_Ptrap_Sect_text_end,
thr1_ptrap_demap_all_entry:
Thr4_Ptrap_Sect_text_end:
!#*********************************************************************
SECTION .Thr5_Ptrap_Sect TEXT_VA=THR5_PTRAP_TEXT_VA
end_label = Thr5_Ptrap_Sect_text_end,
thr1_ptrap_demap_all_entry:
Thr5_Ptrap_Sect_text_end:
!#*********************************************************************
SECTION .Thr6_Ptrap_Sect TEXT_VA=THR6_PTRAP_TEXT_VA
end_label = Thr6_Ptrap_Sect_text_end,
thr1_ptrap_demap_all_entry:
Thr6_Ptrap_Sect_text_end:
!#*********************************************************************
SECTION .Thr7_Ptrap_Sect TEXT_VA=THR7_PTRAP_TEXT_VA
end_label = Thr7_Ptrap_Sect_text_end,
thr1_ptrap_demap_all_entry:
Thr7_Ptrap_Sect_text_end:
!#*****************************************************************************************
SECTION .HTRAPS TEXT_VA=HPTRAP_TEXT_PA
setx ext_trap_0x64_begin, %g1, %g2
setx ext_trap_0x68_begin, %g1, %g2
stxa %g0, [%g1] ASI_IMMU_DEMAP
stxa %g0, [%g1] ASI_DMMU_DEMAP
!#*****************************************************************************************
SECTION .HPTRAPS_EXT_SECT TEXT_VA=HPTRAPS_EXT_TEXT_PA, DATA_VA=HPTRAPS_EXT_DATA_PA
.global ext_trap_0x64_begin
.global ext_trap_0x68_begin
trap_0x64_save_registers:
trap_0x68_save_registers:
.xword 0x000000ffffffe000
.xword 0x000000ffffffc000
.xword 0x000000ffffff8000
.xword 0x000000ffffff0000
.xword 0x000000fffffe0000
.xword 0x000000fffffc0000
.xword 0x000000fffff80000
.xword 0x000000fffff00000
.xword 0x000000ffffe00000
.xword 0x000000ffffc00000
.xword 0x000000ffff800000
.xword 0x000000ffff000000
.xword 0x000000fffe000000
.xword 0x000000fffc000000
.xword 0x000000fff8000000
.xword 0x000000fff0000000
.xword 0x00000000003fe000
.xword 0x00000000007fe000
.xword 0x0000000000ffe000
.xword 0x0000000001ffe000
.xword 0x0000000003ffe000
.xword 0x0000000007ffe000
.xword 0x000000000fffe000
.xword 0x000000001fffe000
.xword 0x000000003fffe000
.xword 0x000000007fffe000
.xword 0x00000000ffffe000
.xword 0x00000001ffffe000
.xword 0x00000003ffffe000
.xword 0x00000007ffffe000
.xword 0x0000000fffffe000
.xword 0x0000001fffffe000
.xword 0x0000000001ff0000
.xword 0x0000000003ff0000
.xword 0x0000000007ff0000
.xword 0x000000000fff0000
.xword 0x000000001fff0000
.xword 0x000000003fff0000
.xword 0x000000007fff0000
.xword 0x00000000ffff0000
.xword 0x00000001ffff0000
.xword 0x00000003ffff0000
.xword 0x00000007ffff0000
.xword 0x0000000fffff0000
.xword 0x0000001fffff0000
.xword 0x0000003fffff0000
.xword 0x0000007fffff0000
.xword 0x000000ffffff0000
.xword 0x000000007fc00000
.xword 0x00000000ffc00000
.xword 0x00000001ffc00000
.xword 0x00000003ffc00000
.xword 0x00000007ffc00000
.xword 0x0000000fffc00000
.xword 0x0000001fffc00000
.xword 0x0000003fffc00000
.xword 0x0000007fffc00000
.xword 0x000000ffffc00000
.xword 0x000001ffffc00000
.xword 0x000003ffffc00000
.xword 0x000007ffffc00000
.xword 0x00000fffffc00000
.xword 0x00001fffffc00000
.xword 0x00003fffffc00000
.xword 0x0000001fe0000000
.xword 0x0000003fe0000000
.xword 0x0000007fe0000000
.xword 0x000000ffe0000000
.xword 0x000001ffe0000000
.xword 0x000003ffe0000000
.xword 0x000007ffe0000000
.xword 0x00000fffe0000000
.xword 0x00001fffe0000000
.xword 0x00003fffe0000000
.xword 0x00007fffe0000000
.xword 0x0000ffffe0000000
.xword 0x0001ffffe0000000
.xword 0x0003ffffe0000000
.xword 0x0007ffffe0000000
.xword 0x000fffffe0000000
!#*********************************************************************
SECTION .Thr0_User_Text_4v000 TEXT_VA=0x00a7140000
Name = .Thr0_User_Text_4v000,
end_label = Thr0_User_Text_4v000_text_end,
.global Thr0_user_code_entry
.global Thr0_User_Text_4v000_text_begin
Thr0_User_Text_4v000_text_begin:
setx Thr0_User_Data_4u100_data_begin, %l0, %l1
Thr0_User_Text_4v000_text_end:
!#*********************************************************************
SECTION .Thr0_User_Data_4u100 DATA_VA=0x00143c4000
Name = .Thr0_User_Data_4u100,
end_label = Thr0_User_Data_4u100_data_end,
.global Thr0_User_Data_4u100_data_begin
Thr0_User_Data_4u100_data_begin:
Thr0_User_Data_4u100_data_end:
!#*********************************************************************
SECTION .Thr1_User_Text_4u000 TEXT_VA=0x0c60000000
Name = .Thr1_User_Text_4u000,
end_label = Thr1_User_Text_4u000_text_end,
.global Thr1_user_code_entry
.global Thr1_User_Text_4u000_text_begin
Thr1_User_Text_4u000_text_begin:
setx Thr1_User_Data_4v100_data_begin, %l0, %l3
brnz %l0, wait_inner_loop
brnz %l2, wait_outer_loop
setx shared_code, %l0, %l1
Thr1_User_Text_4u000_text_end:
!#*********************************************************************
SECTION .Thr1_User_Data_4v100 DATA_VA=0x1120006000
Name = .Thr1_User_Data_4v100,
end_label = Thr1_User_Data_4v100_data_end,
.global Thr1_User_Data_4v100_data_begin
Thr1_User_Data_4v100_data_begin:
Thr1_User_Data_4v100_data_end:
!#*********************************************************************
SECTION .Thr2_User_Text_4v000 TEXT_VA=0x00a7830000
Name = .Thr2_User_Text_4v000,
end_label = Thr2_User_Text_4v000_text_end,
.global Thr2_user_code_entry
.global Thr2_User_Text_4v000_text_begin
Thr2_User_Text_4v000_text_begin:
Thr2_User_Text_4v000_text_end:
!#*********************************************************************
SECTION .Thr2_User_Data_4v100 DATA_VA=0x00a7d80000
Name = .Thr2_User_Data_4v100,
end_label = Thr2_User_Data_4v100_data_end,
.global Thr2_User_Data_4v100_data_begin
Thr2_User_Data_4v100_data_begin:
Thr2_User_Data_4v100_data_end:
!#*********************************************************************
SECTION .Thr3_User_Text_4v000 TEXT_VA=0x1470000000
Name = .Thr3_User_Text_4v000,
end_label = Thr3_User_Text_4v000_text_end,
.global Thr3_user_code_entry
.global Thr3_User_Text_4v000_text_begin
Thr3_User_Text_4v000_text_begin:
Thr3_User_Text_4v000_text_end:
!#*********************************************************************
SECTION .Thr3_User_Data_4u100 DATA_VA=0x00a7720000
Name = .Thr3_User_Data_4u100,
end_label = Thr3_User_Data_4u100_data_end,
.global Thr3_User_Data_4u100_data_begin
Thr3_User_Data_4u100_data_begin:
Thr3_User_Data_4u100_data_end:
!#*********************************************************************
SECTION .Thr4_User_Text_4v000 TEXT_VA=0x1670000000
Name = .Thr4_User_Text_4v000,
end_label = Thr4_User_Text_4v000_text_end,
.global Thr4_user_code_entry
.global Thr4_User_Text_4v000_text_begin
Thr4_User_Text_4v000_text_begin:
Thr4_User_Text_4v000_text_end:
!#*********************************************************************
SECTION .Thr4_User_Data_4u100 DATA_VA=0x00a7290000
Name = .Thr4_User_Data_4u100,
end_label = Thr4_User_Data_4u100_data_end,
.global Thr4_User_Data_4u100_data_begin
Thr4_User_Data_4u100_data_begin:
Thr4_User_Data_4u100_data_end:
!#*********************************************************************
SECTION .Thr5_User_Text_4v000 TEXT_VA=0x0f20000000
Name = .Thr5_User_Text_4v000,
end_label = Thr5_User_Text_4v000_text_end,
.global Thr5_user_code_entry
.global Thr5_User_Text_4v000_text_begin
Thr5_User_Text_4v000_text_begin:
Thr5_User_Text_4v000_text_end:
!#*********************************************************************
SECTION .Thr5_User_Data_4v100 DATA_VA=0x14e0000000
Name = .Thr5_User_Data_4v100,
end_label = Thr5_User_Data_4v100_data_end,
.global Thr5_User_Data_4v100_data_begin
Thr5_User_Data_4v100_data_begin:
Thr5_User_Data_4v100_data_end:
!#*********************************************************************
SECTION .Thr6_User_Text_4u000 TEXT_VA=0x00a7990000
Name = .Thr6_User_Text_4u000,
end_label = Thr6_User_Text_4u000_text_end,
.global Thr6_user_code_entry
.global Thr6_User_Text_4u000_text_begin
Thr6_User_Text_4u000_text_begin:
Thr6_User_Text_4u000_text_end:
!#*********************************************************************
SECTION .Thr6_User_Data_4u100 DATA_VA=0x0b90000000
Name = .Thr6_User_Data_4u100,
end_label = Thr6_User_Data_4u100_data_end,
.global Thr6_User_Data_4u100_data_begin
Thr6_User_Data_4u100_data_begin:
Thr6_User_Data_4u100_data_end:
!#*********************************************************************
SECTION .Thr7_User_Text_4u000 TEXT_VA=0x0c70000000
Name = .Thr7_User_Text_4u000,
end_label = Thr7_User_Text_4u000_text_end,
.global Thr7_user_code_entry
.global Thr7_User_Text_4u000_text_begin
Thr7_User_Text_4u000_text_begin:
Thr7_User_Text_4u000_text_end:
!#*********************************************************************
SECTION .Thr7_User_Text_4v000 TEXT_VA=0x0014242000
Name = .Thr7_User_Text_4v000,
end_label = Thr7_User_Text_4v000_text_end,
.global Thr7_User_Text_4v000_text_begin
Thr7_User_Text_4v000_text_begin:
Thr7_User_Text_4v000_text_end: