verif/diag/diaglists/pmu/spc_pmu.diaglist

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: spc_pmu.diaglist
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
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// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
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// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
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// ========== Copyright Header End ============================================
#if ((! defined CCM && ! defined FC) || defined ALL_DIAGS)

<sys(pmu) name=sys(pmu)>
<sys(all)>
<sys(all_T2)>
<sys(nightly)>
<runargs -nosas -midas_args=-DNOPMUENABLE>
        isa3_pmu_e2_t1          isa3_pmu_e2_t1.s
        isa3_pmu_imiss_idle     isa3_pmu_imiss_idle.s
        isa3_pmu_int15          isa3_pmu_int15.s
//        isa3_pmu_spu_desbusy    isa3_pmu_spu_desbusy.s
//        isa3_pmu_sl6            isa3_pmu_sl6.s
        isa3_pmu_cpu_ldst       isa3_pmu_cpu_ldst.s
        isa3_pmu_dmiss_idle     isa3_pmu_dmiss_idle.s
        isa3_pmu_other          isa3_pmu_other.s

// test plan

<runargs -vcs_run_args=+TIMEOUT=500000 -vcs_run_args=+skt_timeout=500000 -max_cycle=+5000000 -rtl_timeout=5000000>

//select 5 CCX

//SPU loads to CCX (stream loads)
//pmu_ccx_sel5_0x01_th0 pmu_ccx_sel5_0x01_th0.s
// pmu_ccx_sel5_0x01_thAll pmu_ccx_sel5_0x01_thAll.s -vcs_run_args=+thread=ff

//SPU stores to CCX (stream stores)
// pmu_ccx_sel5_0x02_th0 pmu_ccx_sel5_0x02_th0.s
// pmu_ccx_sel5_0x02_thAll pmu_ccx_sel5_0x02_thAll.s -vcs_run_args=+thread=ff

//CPU loads to CCX
pmu_ccx_sel5_0x04_thAll pmu_ccx_sel5_0x04_thAll.s -vcs_run_args=+thread=ff

//CPU stores to CCX
pmu_ccx_sel5_0x10_thAll pmu_ccx_sel5_0x10_thAll.s -vcs_run_args=+thread=ff

//select 6 SPU operations

// diags are under spu
// DES/3DES
//  spu_des_pmu_sel6 spu_des_pmu_sel6.s -vcs_run_args=+thread=ff
//  spu_3des_pmu_sel6 spu_3des_pmu_sel6.s

// AES
//  spu_aes_pmu_sel6 spu_aes_pmu_sel6.s -vcs_run_args=+thread=ff

// RC4
//  spu_rc4_pmu_sel6 spu_rc4_pmu_sel6.s -vcs_run_args=+thread=ff

// HASH (md5/sha1/sha256)
//  spu_md5_pmu_sel6 spu_md5_pmu_sel6.s
//  spu_sha1_pmu_sel6 spu_sha1_pmu_sel6.s -vcs_run_args=+thread=ff
//  spu_sha256_pmu_sel6 spu_sha256_pmu_sel6.s

// MA
//  spu_ma_pmu_sel6 spu_ma_pmu_sel6.s -vcs_run_args=+thread=ff

// CRC (32c - tcpip)
//  spu_tcpip_pmu_sel6 spu_tcpip_pmu_sel6.s -vcs_run_args=+thread=ff
//  spu_crc32c_pmu_sel6 spu_crc32c_pmu_sel6.s

// subset (MA and something else)

//select 7 SPU busy

// diags are under spu
// DES/3DES
//  spu_des_pmu_sel7 spu_des_pmu_sel7.s -vcs_run_args=+thread=ff
//  spu_3des_pmu_sel7 spu_3des_pmu_sel7.s

// AES
//  spu_aes_pmu_sel7 spu_aes_pmu_sel7.s -vcs_run_args=+thread=ff

// RC4
//  spu_rc4_pmu_sel7 spu_rc4_pmu_sel7.s -vcs_run_args=+thread=ff

// HASH
//  spu_md5_pmu_sel7 spu_md5_pmu_sel7.s
//  spu_sha1_pmu_sel7 spu_sha1_pmu_sel7.s -vcs_run_args=+thread=ff
//  spu_sha256_pmu_sel7 spu_sha256_pmu_sel7.s

// MA
//  spu_ma_pmu_sel7 spu_ma_pmu_sel7.s -vcs_run_args=+thread=ff

// CRC (32c,tcpip)
//  spu_tcpip_pmu_sel7 spu_tcpip_pmu_sel7.s -vcs_run_args=+thread=ff
//  spu_crc32c_pmu_sel7 spu_tcpip_pmu_sel7.s

// subset (MA and something else)
</runargs> // timeout
</runargs> // -nosas

//ICMiss with errors
// had to comment out because it relies on stable RAS_ENV for counting
// however changes in the model can change the ENV_RAS causing this test to fail
//  icMissVariations icMissVariations.pal  -vcs_run_args=+err_l2c_on -vcs_run_args=+err_l2c_freq=30 -vcs_run_args=+err_sync_on -tg_seed=1 -midas_args=-DINC_ERR_TRAPS -nosas.

//TLB Misses
  itlbMiss0     itlbSl3.pal          -vcs_run_args=+thread=01
  itlbMiss1     itlbSl3.pal          -vcs_run_args=+thread=02
  itlbMiss2     itlbSl3.pal          -vcs_run_args=+thread=04
  itlbMiss3     itlbSl3.pal          -vcs_run_args=+thread=08
  itlbMiss4     itlbSl3.pal          -vcs_run_args=+thread=10
  itlbMiss5     itlbSl3.pal          -vcs_run_args=+thread=20
  itlbMiss6     itlbSl3.pal          -vcs_run_args=+thread=40
  itlbMiss7     itlbSl3.pal          -vcs_run_args=+thread=80

  dtlbMiss0     dtlbSl3.pal          -vcs_run_args=+thread=01
  dtlbMiss1     dtlbSl3.pal          -vcs_run_args=+thread=02
  dtlbMiss2     dtlbSl3.pal          -vcs_run_args=+thread=04
  dtlbMiss3     dtlbSl3.pal          -vcs_run_args=+thread=08
  dtlbMiss4     dtlbSl3.pal          -vcs_run_args=+thread=10
  dtlbMiss5     dtlbSl3.pal          -vcs_run_args=+thread=20
  dtlbMiss6     dtlbSl3.pal          -vcs_run_args=+thread=40
  dtlbMiss7     dtlbSl3.pal          -vcs_run_args=+thread=80

  itlbMissLoOv0 itlbSl3OvL.pal       -vcs_run_args=+thread=01
  itlbMissLoOv1 itlbSl3OvL.pal       -vcs_run_args=+thread=02
  itlbMissLoOv2 itlbSl3OvL.pal       -vcs_run_args=+thread=04
  itlbMissLoOv3 itlbSl3OvL.pal       -vcs_run_args=+thread=08
  itlbMissLoOv4 itlbSl3OvL.pal       -vcs_run_args=+thread=10
  itlbMissLoOv5 itlbSl3OvL.pal       -vcs_run_args=+thread=20
  itlbMissLoOv6 itlbSl3OvL.pal       -vcs_run_args=+thread=40
  itlbMissLoOv7 itlbSl3OvL.pal       -vcs_run_args=+thread=80

  itlbMissHiOv0 itlbSl3OvH.pal       -vcs_run_args=+thread=01
  itlbMissHiOv1 itlbSl3OvH.pal       -vcs_run_args=+thread=02
  itlbMissHiOv2 itlbSl3OvH.pal       -vcs_run_args=+thread=04
  itlbMissHiOv3 itlbSl3OvH.pal       -vcs_run_args=+thread=08
  itlbMissHiOv4 itlbSl3OvH.pal       -vcs_run_args=+thread=10
  itlbMissHiOv5 itlbSl3OvH.pal       -vcs_run_args=+thread=20
  itlbMissHiOv6 itlbSl3OvH.pal       -vcs_run_args=+thread=40
  itlbMissHiOv7 itlbSl3OvH.pal       -vcs_run_args=+thread=80

  dtlbMissLoOv0 dtlbSl3OvL.pal       -vcs_run_args=+thread=01
  dtlbMissLoOv1 dtlbSl3OvL.pal       -vcs_run_args=+thread=02
  dtlbMissLoOv2 dtlbSl3OvL.pal       -vcs_run_args=+thread=04
  dtlbMissLoOv3 dtlbSl3OvL.pal       -vcs_run_args=+thread=08
  dtlbMissLoOv4 dtlbSl3OvL.pal       -vcs_run_args=+thread=10
  dtlbMissLoOv5 dtlbSl3OvL.pal       -vcs_run_args=+thread=20
  dtlbMissLoOv6 dtlbSl3OvL.pal       -vcs_run_args=+thread=40
  dtlbMissLoOv7 dtlbSl3OvL.pal       -vcs_run_args=+thread=80

  dtlbMissHiOv0 dtlbSl3OvH.pal       -vcs_run_args=+thread=01
  dtlbMissHiOv1 dtlbSl3OvH.pal       -vcs_run_args=+thread=02
  dtlbMissHiOv2 dtlbSl3OvH.pal       -vcs_run_args=+thread=04
  dtlbMissHiOv3 dtlbSl3OvH.pal       -vcs_run_args=+thread=08
  dtlbMissHiOv4 dtlbSl3OvH.pal       -vcs_run_args=+thread=10
  dtlbMissHiOv5 dtlbSl3OvH.pal       -vcs_run_args=+thread=20
  dtlbMissHiOv6 dtlbSl3OvH.pal       -vcs_run_args=+thread=40
  dtlbMissHiOv7 dtlbSl3OvH.pal       -vcs_run_args=+thread=80

//Cache misses
  icacheMiss0   icacheMissSl3.s    -vcs_run_args=+thread=01
  icacheMiss1   icacheMissSl3.s    -vcs_run_args=+thread=02
  icacheMiss2   icacheMissSl3.s    -vcs_run_args=+thread=04
  icacheMiss3   icacheMissSl3.s    -vcs_run_args=+thread=08
  icacheMiss4   icacheMissSl3.s    -vcs_run_args=+thread=10
  icacheMiss5   icacheMissSl3.s    -vcs_run_args=+thread=20
  icacheMiss6   icacheMissSl3.s    -vcs_run_args=+thread=40
  icacheMiss7   icacheMissSl3.s    -vcs_run_args=+thread=80

  dcacheMiss0   dcacheMissSl3.s    -vcs_run_args=+thread=01
  dcacheMiss1   dcacheMissSl3.s    -vcs_run_args=+thread=02
  dcacheMiss2   dcacheMissSl3.s    -vcs_run_args=+thread=04
  dcacheMiss3   dcacheMissSl3.s    -vcs_run_args=+thread=08
  dcacheMiss4   dcacheMissSl3.s    -vcs_run_args=+thread=10
  dcacheMiss5   dcacheMissSl3.s    -vcs_run_args=+thread=20
  dcacheMiss6   dcacheMissSl3.s    -vcs_run_args=+thread=40
  dcacheMiss7   dcacheMissSl3.s    -vcs_run_args=+thread=80

  dcacheOvH0    dcacheOvH.s        -vcs_run_args=+thread=01
  dcacheOvH1    dcacheOvH.s        -vcs_run_args=+thread=02
  dcacheOvH2    dcacheOvH.s        -vcs_run_args=+thread=04
  dcacheOvH3    dcacheOvH.s        -vcs_run_args=+thread=08
  dcacheOvH4    dcacheOvH.s        -vcs_run_args=+thread=10
  dcacheOvH5    dcacheOvH.s        -vcs_run_args=+thread=20
  dcacheOvH6    dcacheOvH.s        -vcs_run_args=+thread=40
  dcacheOvH7    dcacheOvH.s        -vcs_run_args=+thread=80

  dcacheOvL0    dcacheOvL.s        -vcs_run_args=+thread=01
  dcacheOvL1    dcacheOvL.s        -vcs_run_args=+thread=02
  dcacheOvL2    dcacheOvL.s        -vcs_run_args=+thread=04
  dcacheOvL3    dcacheOvL.s        -vcs_run_args=+thread=08
  dcacheOvL4    dcacheOvL.s        -vcs_run_args=+thread=10
  dcacheOvL5    dcacheOvL.s        -vcs_run_args=+thread=20
  dcacheOvL6    dcacheOvL.s        -vcs_run_args=+thread=40
  dcacheOvL7    dcacheOvL.s        -vcs_run_args=+thread=80

#ifdef SPC
  dcacheMissL20 dcacheL2MissSl3.s  -vcs_run_args=+thread=01 -vcs_run_args=+l2miss_type=1 -nosas
  dcacheMissL21 dcacheL2MissSl3.s  -vcs_run_args=+thread=02 -vcs_run_args=+l2miss_type=1
  dcacheMissL22 dcacheL2MissSl3.s  -vcs_run_args=+thread=04 -vcs_run_args=+l2miss_type=1
  dcacheMissL23 dcacheL2MissSl3.s  -vcs_run_args=+thread=08 -vcs_run_args=+l2miss_type=1
  dcacheMissL24 dcacheL2MissSl3.s  -vcs_run_args=+thread=10 -vcs_run_args=+l2miss_type=1
  dcacheMissL25 dcacheL2MissSl3.s  -vcs_run_args=+thread=20 -vcs_run_args=+l2miss_type=1
  dcacheMissL26 dcacheL2MissSl3.s  -vcs_run_args=+thread=40 -vcs_run_args=+l2miss_type=1
  dcacheMissL27 dcacheL2MissSl3.s  -vcs_run_args=+thread=80 -vcs_run_args=+l2miss_type=1


  icMiss0  icMissL2Miss.pal -vcs_run_args=+thread=01 -vcs_run_args=+l2miss_type=1
  icMiss1  icMissL2Miss.pal -vcs_run_args=+thread=02 -vcs_run_args=+l2miss_type=1
  icMiss2  icMissL2Miss.pal -vcs_run_args=+thread=04 -vcs_run_args=+l2miss_type=1
  icMiss3  icMissL2Miss.pal -vcs_run_args=+thread=08 -vcs_run_args=+l2miss_type=1
  icMiss4  icMissL2Miss.pal -vcs_run_args=+thread=10 -vcs_run_args=+l2miss_type=1
  icMiss5  icMissL2Miss.pal -vcs_run_args=+thread=20 -vcs_run_args=+l2miss_type=1
  icMiss6  icMissL2Miss.pal -vcs_run_args=+thread=40 -vcs_run_args=+l2miss_type=1
  icMiss7  icMissL2Miss.pal -vcs_run_args=+thread=80 -vcs_run_args=+l2miss_type=1
#endif

  pmuAtomic   pmuAtomic.s   -vcs_run_args=+thread=all

  pmuOverflowBit ovBitTest.pal -vcs_run_args=+thread=all

#ifdef SPC
//SL 4 test
  serviceLevel4 pmu_sl4_mask_n2.pal  -vcs_run_args=+l2miss_type=1 -nosas
#endif

</sys(nightly)>
</sys(all_T2)>
</sys(all)>
</sys(pmu)>

#endif