Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / diaglists / tcu / fc8_tcu_clkstop.diaglist
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: fc8_tcu_clkstop.diaglist
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<sys(jtag_debug)>
<fc8_tcu_clkstop name=fc8_tcu_clkstop>
<runargs -vcs_run_args=+BYPASS_AMB_DRAM_INIT> // required since "-config_cpp_args=-DIDT_AMB" is specified in build args
<runargs -nosas -fast_boot -midas_args=-DPART_0_BASE=0x200000000 -midas_args=-DL2_REG_PROG>
<runargs -midas_args=-DCMP_THREAD_START=0x0101010101010101 -finish_mask=0101010101010101> // thread 0 of each core
<runargs -midas_args=-DRESET_STAT_CHECK> // required when do WMR in assembly diag
<runargs -vcs_run_args=+mcu_errmon_disable -vcs_run_args=+mcu_fmon_disable -vcs_run_args=+mcuesr_mon_disable>
<runargs -vcs_run_args=+l2esr_mon_off -vcs_run_args=+l2cpx_errmon_off -vcs_run_args=+l2esr_mon_DEBUG_off>
<runargs -vcs_run_args=+ios_0in_ras_chk_off -vcs_run_args=+ios_ras_interrupt_chk_off>
<runargs -vcs_run_args=+socras_mon_off -vcs_run_args=+sio_dmu_ras_chk_off -vcs_run_args=+sio_niu_ras_chk_off>
<runargs -tg_seed=1>
<runargs -midas_args=-DVERA_PROG_DEL=100 -rtl_timeout=200000 -vcs_run_args=+skt_timeout=200000>
<runargs -midas_args=-DVERA_PROG_DEL=100 -midas_args=-DVERA_PROG_DEL2=100>
<runargs -vcs_run_args=+nowait_asmdiag_done>
fc8_spcdbgevent_hstop tcu_clkstp_spcdbgevent.s fc_tcu_clkstp_spcdbgevent_hstop.vr -midas_args=-DSPC_HARDSTOP
fc8_spcdbgevent_sstop_1core tcu_clkstp_spcdbgevent.s fc_tcu_clkstp_spcdbgevent_sstop.vr -midas_args=-DSPC_SOFTSTOP
fc8_spcdbgevent_sstop_8core tcu_clkstp_spcdbgevent.s fc_tcu_clkstp_spcdbgevent_sstop.vr -midas_args=-DSPC_SOFTSTOP -vcs_run_args=+stop_allcores
fc8_spcdbgevent_trigout tcu_clkstp_spcdbgevent.s fc_tcu_clkstp_spcdbgevent_trigout.vr -midas_args=-DSPC_TRIGOUT
</runargs>
</runargs>
</runargs>
</runargs>
</runargs>
</runargs>
</runargs>
</runargs>
</runargs>
</runargs>
</runargs>
</runargs>
</fc8_tcu_clkstop>
</sys(jtag_debug)>