verif/env/common/coverage/siu/siu_ildq3_rd_sample.vrhpal

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//
// OpenSPARC T2 Processor File: siu_ildq3_rd_sample.vrhpal
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sample siu_coverage_ildq3.rd_adr
{
        state s_ILDQ3_EMPTY             (0:31) if (ildq3_size == 0);
        state s_ILDQ3_BACK_TO_BACK_RD   (0:31) if (ildq3_rd_b2b == 2);
                                        // this happens in 2 cycles since each
                                        // cycle take 32 bits and its reading 64 bits
        state s_ILDQ3_RD_WR             (0:31) if (siu_coverage_ildq3.wr_en === 1'b1);

        trans t_ILDQ3_RD_ADR_00         ( 0 ->  1);
        trans t_ILDQ3_RD_ADR_01         ( 1 ->  2);
        trans t_ILDQ3_RD_ADR_02         ( 2 ->  3);
        trans t_ILDQ3_RD_ADR_03         ( 3 ->  4);
        trans t_ILDQ3_RD_ADR_04         ( 4 ->  5);
        trans t_ILDQ3_RD_ADR_05         ( 5 ->  6);
        trans t_ILDQ3_RD_ADR_06         ( 6 ->  7);
        trans t_ILDQ3_RD_ADR_07         ( 7 ->  8);
        trans t_ILDQ3_RD_ADR_08         ( 8 ->  9);
        trans t_ILDQ3_RD_ADR_09         ( 9 -> 10);
        trans t_ILDQ3_RD_ADR_10         (10 -> 11);
        trans t_ILDQ3_RD_ADR_11         (11 -> 12);
        trans t_ILDQ3_RD_ADR_12         (12 -> 13);
        trans t_ILDQ3_RD_ADR_13         (13 -> 14);
        trans t_ILDQ3_RD_ADR_14         (14 -> 15);
        trans t_ILDQ3_RD_ADR_15         (15 -> 16);
        trans t_ILDQ3_RD_ADR_16         (16 -> 17);
        trans t_ILDQ3_RD_ADR_17         (17 -> 18);
        trans t_ILDQ3_RD_ADR_18         (18 -> 19);
        trans t_ILDQ3_RD_ADR_19         (19 -> 20);
        trans t_ILDQ3_RD_ADR_20         (20 -> 21);
        trans t_ILDQ3_RD_ADR_21         (21 -> 22);
        trans t_ILDQ3_RD_ADR_22         (22 -> 23);
        trans t_ILDQ3_RD_ADR_23         (23 -> 24);
        trans t_ILDQ3_RD_ADR_24         (24 -> 25);
        trans t_ILDQ3_RD_ADR_25         (25 -> 26);
        trans t_ILDQ3_RD_ADR_26         (26 -> 27);
        trans t_ILDQ3_RD_ADR_27         (27 -> 28);
        trans t_ILDQ3_RD_ADR_28         (28 -> 29);
        trans t_ILDQ3_RD_ADR_29         (29 -> 30);
        trans t_ILDQ3_RD_ADR_30         (30 -> 31);
        trans t_ILDQ3_RD_ADR_31         (31 ->  0);
}