// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: FcMcuMonPort.if.vrh
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
#ifndef INC_FC_MCUMON_IF_VRH
#define INC_FC_MCUMON_IF_VRH
#include <vera_defines.vrh>
interface dram_write_Mcu0_if {
input clk CLOCK verilog_node "tb_top.cpu.mcu0.drl2clk";
input ncu_sii_l2_idx_hash_en PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.sii.ncu_sii_l2_idx_hash_en";
input drif_dram_rank_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_rank_a";
input [2:0] drif_dram_dimm_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_dimm_a";
input [2:0] drif_dram_bank_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_bank_a";
input [15:0] drif_dram_addr_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_addr_a";
input [2:0] drif_dram_cmd_a PSAMPLE INPUT_SKEW verilog_node "{ `CPU.mcu0.drif__n32596, `CPU.mcu0.\drif_dram_cmd_a[1] , `CPU.mcu0.\drif_dram_cmd_a[0] }";
input [2:0] drif_dram_cmd_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_cmd_a";
input drif_dram_rank_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_rank_b";
input [2:0] drif_dram_dimm_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_dimm_b";
input [2:0] drif_dram_bank_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_bank_b";
input [15:0] drif_dram_addr_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_addr_b";
input [2:0] drif_dram_cmd_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_cmd_b";
input drif_dram_rank_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_rank_c";
input [2:0] drif_dram_dimm_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_dimm_c";
input [2:0] drif_dram_bank_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_bank_c";
input [15:0] drif_dram_addr_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_addr_c";
input [2:0] drif_dram_cmd_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.drif_dram_cmd_c";
input ncu_mcu_ba01 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.ncu_mcu_ba01";
input ncu_mcu_ba23 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.ncu_mcu_ba23";
input ncu_mcu_ba45 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.ncu_mcu_ba45";
input ncu_mcu_ba67 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu0.ncu_mcu_ba67";
interface dram_write_Mcu1_if {
input clk CLOCK verilog_node "tb_top.cpu.mcu1.drl2clk";
input drif_dram_rank_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_rank_a";
input [2:0] drif_dram_dimm_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_dimm_a";
input [2:0] drif_dram_bank_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_bank_a";
input [15:0] drif_dram_addr_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_addr_a";
input [2:0] drif_dram_cmd_a PSAMPLE INPUT_SKEW verilog_node "{ `CPU.mcu1.drif__n32596, `CPU.mcu1.\drif_dram_cmd_a[1] , `CPU.mcu1.\drif_dram_cmd_a[0] }";
input [2:0] drif_dram_cmd_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_cmd_a";
input drif_dram_rank_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_rank_b";
input [2:0] drif_dram_dimm_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_dimm_b";
input [2:0] drif_dram_bank_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_bank_b";
input [15:0] drif_dram_addr_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_addr_b";
input [2:0] drif_dram_cmd_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_cmd_b";
input drif_dram_rank_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_rank_c";
input [2:0] drif_dram_dimm_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_dimm_c";
input [2:0] drif_dram_bank_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_bank_c";
input [15:0] drif_dram_addr_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_addr_c";
input [2:0] drif_dram_cmd_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.drif_dram_cmd_c";
input ncu_mcu_ba01 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.ncu_mcu_ba01";
input ncu_mcu_ba23 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.ncu_mcu_ba23";
input ncu_mcu_ba45 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.ncu_mcu_ba45";
input ncu_mcu_ba67 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu1.ncu_mcu_ba67";
interface dram_write_Mcu2_if {
input clk CLOCK verilog_node "tb_top.cpu.mcu2.drl2clk";
input drif_dram_rank_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_rank_a";
input [2:0] drif_dram_dimm_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_dimm_a";
input [2:0] drif_dram_bank_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_bank_a";
input [15:0] drif_dram_addr_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_addr_a";
input [2:0] drif_dram_cmd_a PSAMPLE INPUT_SKEW verilog_node "{ `CPU.mcu2.drif__n32596, `CPU.mcu2.\drif_dram_cmd_a[1] , `CPU.mcu2.\drif_dram_cmd_a[0] }";
input [2:0] drif_dram_cmd_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_cmd_a";
input drif_dram_rank_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_rank_b";
input [2:0] drif_dram_dimm_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_dimm_b";
input [2:0] drif_dram_bank_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_bank_b";
input [15:0] drif_dram_addr_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_addr_b";
input [2:0] drif_dram_cmd_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_cmd_b";
input drif_dram_rank_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_rank_c";
input [2:0] drif_dram_dimm_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_dimm_c";
input [2:0] drif_dram_bank_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_bank_c";
input [15:0] drif_dram_addr_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_addr_c";
input [2:0] drif_dram_cmd_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.drif_dram_cmd_c";
input ncu_mcu_ba01 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.ncu_mcu_ba01";
input ncu_mcu_ba23 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.ncu_mcu_ba23";
input ncu_mcu_ba45 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.ncu_mcu_ba45";
input ncu_mcu_ba67 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu2.ncu_mcu_ba67";
interface dram_write_Mcu3_if {
input clk CLOCK verilog_node "tb_top.cpu.mcu3.drl2clk";
input drif_dram_rank_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_rank_a";
input [2:0] drif_dram_dimm_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_dimm_a";
input [2:0] drif_dram_bank_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_bank_a";
input [15:0] drif_dram_addr_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_addr_a";
input [2:0] drif_dram_cmd_a PSAMPLE INPUT_SKEW verilog_node "{ `CPU.mcu3.drif__n32596, `CPU.mcu3.\drif_dram_cmd_a[1] , `CPU.mcu3.\drif_dram_cmd_a[0] }";
input [2:0] drif_dram_cmd_a PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_cmd_a";
input drif_dram_rank_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_rank_b";
input [2:0] drif_dram_dimm_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_dimm_b";
input [2:0] drif_dram_bank_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_bank_b";
input [15:0] drif_dram_addr_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_addr_b";
input [2:0] drif_dram_cmd_b PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_cmd_b";
input drif_dram_rank_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_rank_c";
input [2:0] drif_dram_dimm_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_dimm_c";
input [2:0] drif_dram_bank_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_bank_c";
input [15:0] drif_dram_addr_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_addr_c";
input [2:0] drif_dram_cmd_c PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.drif_dram_cmd_c";
input ncu_mcu_ba01 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.ncu_mcu_ba01";
input ncu_mcu_ba23 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.ncu_mcu_ba23";
input ncu_mcu_ba45 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.ncu_mcu_ba45";
input ncu_mcu_ba67 PSAMPLE INPUT_SKEW verilog_node "tb_top.cpu.mcu3.ncu_mcu_ba67";
bind dram_write_MCU DramWriteMCU0
drl2clk dram_write_Mcu0_if.clk;
index_hashing dram_write_Mcu0_if.ncu_sii_l2_idx_hash_en;
drif_dram_rank_a dram_write_Mcu0_if.drif_dram_rank_a;
drif_dram_dimm_a dram_write_Mcu0_if.drif_dram_dimm_a;
drif_dram_bank_a dram_write_Mcu0_if.drif_dram_bank_a;
drif_dram_addr_a dram_write_Mcu0_if.drif_dram_addr_a;
drif_dram_cmd_a dram_write_Mcu0_if.drif_dram_cmd_a;
drif_dram_rank_b dram_write_Mcu0_if.drif_dram_rank_b;
drif_dram_dimm_b dram_write_Mcu0_if.drif_dram_dimm_b;
drif_dram_bank_b dram_write_Mcu0_if.drif_dram_bank_b;
drif_dram_addr_b dram_write_Mcu0_if.drif_dram_addr_b;
drif_dram_cmd_b dram_write_Mcu0_if.drif_dram_cmd_b;
drif_dram_rank_c dram_write_Mcu0_if.drif_dram_rank_c;
drif_dram_dimm_c dram_write_Mcu0_if.drif_dram_dimm_c;
drif_dram_bank_c dram_write_Mcu0_if.drif_dram_bank_c;
drif_dram_addr_c dram_write_Mcu0_if.drif_dram_addr_c;
drif_dram_cmd_c dram_write_Mcu0_if.drif_dram_cmd_c;
ncu_mcu_ba01 dram_write_Mcu0_if.ncu_mcu_ba01;
ncu_mcu_ba23 dram_write_Mcu0_if.ncu_mcu_ba23;
ncu_mcu_ba45 dram_write_Mcu0_if.ncu_mcu_ba45;
ncu_mcu_ba67 dram_write_Mcu0_if.ncu_mcu_ba67;
bind dram_write_MCU DramWriteMCU1
drl2clk dram_write_Mcu1_if.clk;
index_hashing dram_write_Mcu0_if.ncu_sii_l2_idx_hash_en;
drif_dram_rank_a dram_write_Mcu1_if.drif_dram_rank_a;
drif_dram_dimm_a dram_write_Mcu1_if.drif_dram_dimm_a;
drif_dram_bank_a dram_write_Mcu1_if.drif_dram_bank_a;
drif_dram_addr_a dram_write_Mcu1_if.drif_dram_addr_a;
drif_dram_cmd_a dram_write_Mcu1_if.drif_dram_cmd_a;
drif_dram_rank_b dram_write_Mcu1_if.drif_dram_rank_b;
drif_dram_dimm_b dram_write_Mcu1_if.drif_dram_dimm_b;
drif_dram_bank_b dram_write_Mcu1_if.drif_dram_bank_b;
drif_dram_addr_b dram_write_Mcu1_if.drif_dram_addr_b;
drif_dram_cmd_b dram_write_Mcu1_if.drif_dram_cmd_b;
drif_dram_rank_c dram_write_Mcu1_if.drif_dram_rank_c;
drif_dram_dimm_c dram_write_Mcu1_if.drif_dram_dimm_c;
drif_dram_bank_c dram_write_Mcu1_if.drif_dram_bank_c;
drif_dram_addr_c dram_write_Mcu1_if.drif_dram_addr_c;
drif_dram_cmd_c dram_write_Mcu1_if.drif_dram_cmd_c;
ncu_mcu_ba01 dram_write_Mcu1_if.ncu_mcu_ba01;
ncu_mcu_ba23 dram_write_Mcu1_if.ncu_mcu_ba23;
ncu_mcu_ba45 dram_write_Mcu1_if.ncu_mcu_ba45;
ncu_mcu_ba67 dram_write_Mcu1_if.ncu_mcu_ba67;
bind dram_write_MCU DramWriteMCU2
drl2clk dram_write_Mcu2_if.clk;
index_hashing dram_write_Mcu0_if.ncu_sii_l2_idx_hash_en;
drif_dram_rank_a dram_write_Mcu2_if.drif_dram_rank_a;
drif_dram_dimm_a dram_write_Mcu2_if.drif_dram_dimm_a;
drif_dram_bank_a dram_write_Mcu2_if.drif_dram_bank_a;
drif_dram_addr_a dram_write_Mcu2_if.drif_dram_addr_a;
drif_dram_cmd_a dram_write_Mcu2_if.drif_dram_cmd_a;
drif_dram_rank_b dram_write_Mcu2_if.drif_dram_rank_b;
drif_dram_dimm_b dram_write_Mcu2_if.drif_dram_dimm_b;
drif_dram_bank_b dram_write_Mcu2_if.drif_dram_bank_b;
drif_dram_addr_b dram_write_Mcu2_if.drif_dram_addr_b;
drif_dram_cmd_b dram_write_Mcu2_if.drif_dram_cmd_b;
drif_dram_rank_c dram_write_Mcu2_if.drif_dram_rank_c;
drif_dram_dimm_c dram_write_Mcu2_if.drif_dram_dimm_c;
drif_dram_bank_c dram_write_Mcu2_if.drif_dram_bank_c;
drif_dram_addr_c dram_write_Mcu2_if.drif_dram_addr_c;
drif_dram_cmd_c dram_write_Mcu2_if.drif_dram_cmd_c;
ncu_mcu_ba01 dram_write_Mcu2_if.ncu_mcu_ba01;
ncu_mcu_ba23 dram_write_Mcu2_if.ncu_mcu_ba23;
ncu_mcu_ba45 dram_write_Mcu2_if.ncu_mcu_ba45;
ncu_mcu_ba67 dram_write_Mcu2_if.ncu_mcu_ba67;
bind dram_write_MCU DramWriteMCU3
drl2clk dram_write_Mcu3_if.clk;
index_hashing dram_write_Mcu0_if.ncu_sii_l2_idx_hash_en;
drif_dram_rank_a dram_write_Mcu3_if.drif_dram_rank_a;
drif_dram_dimm_a dram_write_Mcu3_if.drif_dram_dimm_a;
drif_dram_bank_a dram_write_Mcu3_if.drif_dram_bank_a;
drif_dram_addr_a dram_write_Mcu3_if.drif_dram_addr_a;
drif_dram_cmd_a dram_write_Mcu3_if.drif_dram_cmd_a;
drif_dram_rank_b dram_write_Mcu3_if.drif_dram_rank_b;
drif_dram_dimm_b dram_write_Mcu3_if.drif_dram_dimm_b;
drif_dram_bank_b dram_write_Mcu3_if.drif_dram_bank_b;
drif_dram_addr_b dram_write_Mcu3_if.drif_dram_addr_b;
drif_dram_cmd_b dram_write_Mcu3_if.drif_dram_cmd_b;
drif_dram_rank_c dram_write_Mcu3_if.drif_dram_rank_c;
drif_dram_dimm_c dram_write_Mcu3_if.drif_dram_dimm_c;
drif_dram_bank_c dram_write_Mcu3_if.drif_dram_bank_c;
drif_dram_addr_c dram_write_Mcu3_if.drif_dram_addr_c;
drif_dram_cmd_c dram_write_Mcu3_if.drif_dram_cmd_c;
ncu_mcu_ba01 dram_write_Mcu3_if.ncu_mcu_ba01;
ncu_mcu_ba23 dram_write_Mcu3_if.ncu_mcu_ba23;
ncu_mcu_ba45 dram_write_Mcu3_if.ncu_mcu_ba45;
ncu_mcu_ba67 dram_write_Mcu3_if.ncu_mcu_ba67;
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