verif/env/common/vera/include/sparcBenchUtils_if.vrh

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//
// OpenSPARC T2 Processor File: sparcBenchUtils_if.vrh
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#ifndef SPARCBENCHUTILS_IF
#define SPARCBENCHUTILS_IF


interface sparcBenchUtils_if {
  input        clk      CLOCK    hdl_node "tb_top.cpu.cmp_gclk_c3_spc0";
  input  [63:0]  th_check_enable  NSAMPLE #-0   hdl_node "tb_top.verif_args.th_check_enable";

#ifdef SPC_BENCH
  // FC will not have this wire
  input  [63:0]  core_running_status  NSAMPLE #-0   hdl_node "tb_top.cmp_core_running_status";
#else
  // cpu.sv users will be OK with this
  input  [63:0]  core_running_status  NSAMPLE #-0   hdl_node "{tb_top.cpu.spc7_ncu_core_running_status[7:0],tb_top.cpu.spc6_ncu_core_running_status[7:0],tb_top.cpu.spc5_ncu_core_running_status[7:0],tb_top.cpu.spc4_ncu_core_running_status[7:0],tb_top.cpu.spc3_ncu_core_running_status[7:0],tb_top.cpu.spc2_ncu_core_running_status[7:0],tb_top.cpu.spc1_ncu_core_running_status[7:0],tb_top.cpu.spc0_ncu_core_running_status[7:0]}";
#endif

  input [31:0] core_cycle_cnt  NSAMPLE #-0   hdl_node "tb_top.core_cycle_cnt";

}

#endif