verif/env/common/verilog/monitors/psrserdes_l0mon.v

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// OpenSPARC T2 Processor File: psrserdes_l0mon.v
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`timescale 1ps/1ps

module psrserdes_l0mon ();

reg enabled;
reg enable;
reg serdes_mon;
reg psr_l2_d;
initial
begin
  enabled = 1'b1;
  serdes_mon = 1'b1;
  if ($test$plusargs("psrserdes_l0mon_disable")) begin
    serdes_mon = 1'b0;
    enabled = 1'b0;
  end
end

wire flush_reset_complete = `TOP.flush_reset_complete;

always @ (flush_reset_complete)
begin
  if (flush_reset_complete == 1'b0)
    enabled = 1'b0;

  if ((flush_reset_complete == 1'b1) && serdes_mon)
    enabled = 1'b1;
end
//--------------------------------------------------------------------------------------

// added this ifndef
`ifdef PEU_SYSTEMC_T2
`else
`ifndef FC_NO_PEU_T2
wire psr_l2_low2high =  `CPU.peu.l2t_etp_link & ~psr_l2_d;
wire psr_l2_high2low = ~`CPU.peu.l2t_etp_link & psr_l2_d;

always @(`CPU.peu.t2l_rst or `CPU.peu.t2l_por)
   enable = 1'b1;

always @(posedge (`CPU.peu.pcl1clk & enabled & enable))
begin
   psr_l2_d <= `CPU.peu.l2t_etp_link;

   if (psr_l2_low2high) begin
      `PR_NORMAL("psrserdes_l0mon", `NORMAL, "PSR L0 LINK is up" );
   end

   if (psr_l2_high2low)
      `PR_INFO("psrserdes_l0mon", `INFO, "PSR L0 LINK HAS LOSS SYNC");
end
`endif
`endif // !`ifdef PEU_SYSTEMC_T2

//if (`TOP.info===1'b1) $dispmon("NCU_MON", `INFO," NIU->NCU::   TYPE %0h; THR_ID %0h; PA = %0h; DATA = %0h;",  i2c_pkt[3:0], i2c_pkt[9:4], i2c_pkt[54:15], i2c_pkt[127:64] );
//`CPU.peu.l2t_etp_link

endmodule