verif/env/ilu_peu/vera/N2str/ilupeuPioCfgIORdStr.vr

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//
// OpenSPARC T2 Processor File: ilupeuPioCfgIORdStr.vr
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class PioCfgIORdPEUStr extends PioBasePEUStr {


  // ******************************************************************
  // The Test Environment objects need to execute the strategy.
  // ******************************************************************
  protected PEUTestEnv              _env;
  protected integer                 _errQueue;


  // ******************************************************************
  // TLP Fields - These fields will be randomized using the parameters
  // in the following section, and obeying the constraints defined
  // within this class.
  // ******************************************************************
  protected         bit [1:0]       _format_req;
  protected         bit [1:0]       _format_cpl;
  protected         bit [4:0]       _type_req;
  protected         bit [4:0]       _type_cpl;

  protected         bit [2:0]       _tc;

  protected         bit             _td_req;
  protected         bit             _td_cpl;
  protected         bit             _ep_req;
  protected         bit             _ep_cpl;

  protected         bit [1:0]       _attr;
  protected         bit [9:0]       _len_req;
  protected         bit [9:0]       _len_cpl;
  protected         bit [15:0]      _req_id;
  protected         bit [7:0]       _tag;
  protected rand    bit [31:0]      _addr_lsb;

  protected         bit [3:0]       _last_dwbe;
  protected         bit [3:0]       _first_dwbe;

  protected         bit [15:0]      _cpl_id;
  protected         bit [2:0]       _cpl_status;
  protected         bit             _bcm;
  protected         bit [11:0]      _byte_count;
  protected         bit [6:0]       _lower_addr;
  protected         integer         _data;

  protected     bit [PEC_PCI__HDR]      reqHdr;
  protected     bit [PEC_PCI__HDR]      cplHdr;
  protected     bit [PEC_PCI__HDR]      urHdr;


  // ******************************************************************
  // The following constraint is used to generate the correct values
  // for the TLP.
  // ******************************************************************
  constraint generate_tlp {

    this._addr_lsb in {this._addr_lsb_min : this._addr_lsb_max};

    if (this._type_req == PEC_PCI__TYPE_CFG0)
      this._addr_lsb[15:12] == 4'b_0000;

    if (this._type_req == PEC_PCI__TYPE_CFG1)
      this._addr_lsb[15:12] == 4'b_0000;
  }


  // ******************************************************************
  // Constructor
  // ******************************************************************
  public task new(PEUTestEnv a_env, (integer a_errQueue = 'bx));

  // ******************************************************************
  // Break this out as common class fullchip and ios can use
  // ******************************************************************
  public task SetPacketParams();

  // ******************************************************************
  // Execute the strategy.  Drive a TLP into the ILU, and expect it out
  // of the PEU.
  // ******************************************************************
  public task Execute();
}


//-------------------------------------------------------------------
// Method Name:
// Description:
//-------------------------------------------------------------------
task PioCfgIORdPEUStr::new(PEUTestEnv a_env, (integer a_errQueue = 'bx)) {


  super.new(a_env);
  this._env = a_env;
  this._errQueue = a_errQueue;
}


//-------------------------------------------------------------------
// Method Name:
// Description:
//-------------------------------------------------------------------
task PioCfgIORdPEUStr::SetPacketParams() {

  integer pass_constrain = 0;
  this._env.allocRdTag(this._tag);


  this._format_req = PEC_PCI__FMT_NO_DATA_3DW;
  this._type_cpl   = PEC_PCI__TYPE_CPL;
  this._tc         = 3'b_000;
  this._td_req     = 1'b_0;
  this._ep_req     = 1'b_0;
  this._attr       = 2'b_00;
  this._len_req    = 10'h_001;
  this._req_id     = 16'h_0000;
  this._last_dwbe  = 4'b_0000;
  this._byte_count = 12'd_4;
  this._lower_addr = 7'b_000_0000;


  this._first_dwbe = urandom_range(this._first_dwbe_max, this._first_dwbe_min);
  this._cpl_id     = urandom_range(this._cpl_id_max, this._cpl_id_min);
  this._data       = urandom_range(this._data_max, this._data_min);


  randcase {
    this._type_req_prob_cfg0    : this._type_req = PEC_PCI__TYPE_CFG0;
    this._type_req_prob_cfg1    : this._type_req = PEC_PCI__TYPE_CFG1;
    this._type_req_prob_io      : this._type_req = PEC_PCI__TYPE_IO;
  }

  randcase {
    this._td_cpl_prob_false     : this._td_cpl = 1'b_0;
    this._td_cpl_prob_true      : this._td_cpl = 1'b_1;
  }

  randcase {
    this._ep_cpl_prob_false     : this._ep_cpl = 1'b_0;
    this._ep_cpl_prob_true      : this._ep_cpl = 1'b_1;
  }

  randcase {
    this._cpl_status_prob_sc    : this._cpl_status = PEC_PCI__CPL_STATUS_SC;
    this._cpl_status_prob_ur    : this._cpl_status = PEC_PCI__CPL_STATUS_UR;
    this._cpl_status_prob_crs   : this._cpl_status = PEC_PCI__CPL_STATUS_CRS;
    this._cpl_status_prob_ca    : this._cpl_status = PEC_PCI__CPL_STATUS_CA;
    this._cpl_status_prob_rsvd1 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD1;
    this._cpl_status_prob_rsvd2 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD2;
    this._cpl_status_prob_rsvd3 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD3;
    this._cpl_status_prob_rsvd4 : this._cpl_status = PEC_PCI__CPL_STATUS_RSVD4;
  }

  randcase {
    this._bcm_prob_false        : this._bcm = 1'b_0;
    this._bcm_prob_true         : this._bcm = 1'b_1;
  }


  this._format_cpl = (this._cpl_status === PEC_PCI__CPL_STATUS_SC) ?
    PEC_PCI__FMT_DATA_3DW : PEC_PCI__FMT_NO_DATA_3DW;

  this._len_cpl    = (this._cpl_status === PEC_PCI__CPL_STATUS_SC) ?
    10'h_001 : 10'h_000;

// Fu: 8/23/06
#ifdef N2_FC
  while (!pass_constrain)
  {
    this._addr_lsb = urandom_range(this._addr_lsb_max, this._addr_lsb_min);
    pass_constrain = 1;
    if (this._type_req == PEC_PCI__TYPE_CFG0)
      if (this._addr_lsb[15:12] != 4'b_0000) pass_constrain = 0;

    if (this._type_req == PEC_PCI__TYPE_CFG1)
      if (this._addr_lsb[15:12] != 4'b_0000) pass_constrain = 0;
  }
///
#else

  if( this.randomize() != OK ) {
    _env.Report.report(RTYP_TEST_ERROR,"PioCfgIORdPEUStr::SetPacketParams - randomize failure \n" );
  }
#endif

  reqHdr [PEC_PCI__HDR]            = {128{1'b_0}};
  reqHdr [PEC_PCI__FMT]            = this._format_req;
  reqHdr [PEC_PCI__TYPE]           = this._type_req;
  reqHdr [PEC_PCI__TC]             = this._tc;
  reqHdr [PEC_PCI__TD]             = this._td_req;
  reqHdr [PEC_PCI__EP]             = this._ep_req;
  reqHdr [PEC_PCI__ATTR]           = this._attr;
  reqHdr [PEC_PCI__LEN]            = this._len_req;
  reqHdr [PEC_PCI__REQ_ID]         = this._req_id;
  reqHdr [PEC_PCI__TLP_TAG]        = this._tag;
  reqHdr [PEC_PCI__LAST_DWBE]      = this._last_dwbe;
  reqHdr [PEC_PCI__FIRST_DWBE]     = this._first_dwbe;
  reqHdr [PEC_PCI__ADDR32]         = { this._addr_lsb[31:2], 2'b_00 };

  cplHdr [PEC_PCI__HDR]            = {128{1'b_0}};
  cplHdr [PEC_PCI__FMT]            = this._format_cpl;
  cplHdr [PEC_PCI__TYPE]           = this._type_cpl;
  cplHdr [PEC_PCI__TC]             = this._tc;
  cplHdr [PEC_PCI__TD]             = this._td_cpl;
  cplHdr [PEC_PCI__EP]             = this._ep_cpl;
  cplHdr [PEC_PCI__ATTR]           = this._attr;
  cplHdr [PEC_PCI__LEN]            = this._len_cpl;
  cplHdr [PEC_PCI__CPL_ID]         = this._cpl_id;
  cplHdr [PEC_PCI__CPL_STATUS]     = this._cpl_status;
  cplHdr [PEC_PCI__BCM]            = this._bcm;
  cplHdr [PEC_PCI__BYTECOUNT]      = this._byte_count;
  cplHdr [PEC_PCI__CPL_REQ_ID]     = this._req_id;
  cplHdr [PEC_PCI__CPL_TAG]        = this._tag;
  cplHdr [PEC_PCI__LOWADDR]        = this._lower_addr;

  urHdr [PEC_PCI__HDR]             = {128{1'b_0}};
  urHdr [PEC_PCI__FMT]             = this._format_cpl;
  urHdr [PEC_PCI__TYPE]            = this._type_cpl;
  urHdr [PEC_PCI__TC]              = this._tc;
  urHdr [PEC_PCI__TD]              = this._td_cpl;
  urHdr [PEC_PCI__EP]              = this._ep_cpl;
  urHdr [PEC_PCI__ATTR]            = this._attr;
  urHdr [PEC_PCI__LEN]             = this._len_cpl;
  urHdr [PEC_PCI__CPL_ID]          = this._cpl_id;
  urHdr [PEC_PCI__CPL_STATUS]      = PEC_PCI__CPL_STATUS_UR;
  urHdr [PEC_PCI__BCM]             = this._bcm;
  urHdr [PEC_PCI__BYTECOUNT]       = this._byte_count;
  urHdr [PEC_PCI__CPL_REQ_ID]      = this._req_id;
  urHdr [PEC_PCI__CPL_TAG]         = this._tag;
  urHdr [PEC_PCI__LOWADDR]         = this._lower_addr;

}

task PioCfgIORdPEUStr::Execute() {

  bit CfgRdCpl=0;       //If set the env will flip the completion byte order
                        // since Denali does it automatically so DMUXtr doesn't
                        // need to store an array for the payload

  SetPacketParams();

  this._env.driveILU(reqHdr, 0, 0);


  this._env.expectPCIE(reqHdr, 0);


  //Added CfgRdCpl since Denali flips the bytes for Cfg Reads
  // this will flip the bytes back so the DMUXtr doesn't need to be changed
  //IOS extends this class and has its own execute so it won't affect IOS
  //FullChip needs to do the same
  CfgRdCpl = (this._type_req !== PEC_PCI__TYPE_IO);

  if ( (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD1) ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD2) ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD3) ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD4)) {
      this._env.Pod.FNXPCIEEnableTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlCplSt ); //Malformed Completion TLP - Reserved completion status (%u).
  }

  //
  repeat( urandom_range( _env.Scenario.ilupeuPioCfgIORdCplDelayMax, _env.Scenario.ilupeuPioCfgIORdCplDelayMin)) @(posedge CLOCK);

  if ( this._ep_cpl && super.f_abortErrTlp )
    this._env.drivePCIE(cplHdr, this._data, *, *, *, 1,CfgRdCpl);
  else
    this._env.drivePCIE(cplHdr, this._data,*,*,*,*,CfgRdCpl );


  if ((this._cpl_status === PEC_PCI__CPL_STATUS_CA)    ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_UR)    ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD1) ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD2) ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD3) ||
      (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD4)) {
    this._env.expectILU(urHdr, this._data);
    mailbox_put(this._errQueue, e_ERR_oe_ruc);
    mailbox_put(this._errQueue, cplHdr );
    if ( (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD1) ||
         (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD2) ||
         (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD3) ||
         (this._cpl_status === PEC_PCI__CPL_STATUS_RSVD4)) {
       this._env.Pod.FNXPCIEEnableTrans.unSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlCplSt ); //Malformed Completion TLP - Reserved completion status (%u).
  }
  }

  else if (this._cpl_status === PEC_PCI__CPL_STATUS_CRS) {

    this._env.expectTimeoutCpl(reqHdr);
    mailbox_put(this._errQueue, e_ERR_oe_crs);
    mailbox_put(this._errQueue, cplHdr );
  }

  else if (this._ep_cpl === 1'b_1) {

    @(posedge CLOCK);
    cplHdr [PEC_PCI__EP] = 0;
    CfgRdCpl = 0;       //Since a completion has already been sent for this req
                        // Denali won't flip the read bits
    this._env.drivePCIE(cplHdr, this._data,*,*,*,*,CfgRdCpl );
    this._env.expectILU(cplHdr, this._data);
    if ( this._errQueue != 0 )
      {
      cplHdr [PEC_PCI__EP] = 1;
      //N2 - Add checking of request header

//      mailbox_put( this._errQueue, e_ERR_none );
//      mailbox_put( this._errQueue, -1 );
//      mailbox_put( this._errQueue, reqHdr );
      mailbox_put(this._errQueue, e_ERR_ue_pp);
      mailbox_put(this._errQueue, cplHdr);
      }
  }

  else {

    this._env.expectILU(cplHdr, this._data);
  }


  this._env.freePioTag(this._tag);
}