verif/env/ilu_peu/vera/include/ilupeuScenarioDefines.vri

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: ilupeuScenarioDefines.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
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// ========== Copyright Header End ============================================
#ifndef ILUPEU_SCENARIO_DEFINE
#define ILUPEU_SCENARIO_DEFINE

/* These are already defined in lpr_a.csr_define.vri
`define FIRE_PLC_TLU_CTB_LPR_A_CSRBUS_EXT_ADDR_WIDTH    13
`define FIRE_PLC_TLU_CTB_LPR_A_CSRBUS_EXT_ADDR_RANGE    12:0

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ADDR  20'b11011100000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_ADDR     30'b000000011011100000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_NAME     "fire_plc_tlu_ctb_lpr_csr_a_ahb"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_WIDTH    64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DEPTH    8192
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_INT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_FIELD_NAME       "fire_plc_tlu_ctb_lpr_csr_a_ahb"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_LOW_ADDR_WIDTH   13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_SEL_RANGE        12:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_ADDR_RANGE       19:13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_READ_MASK        64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_READ_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_WRITE_MASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_WRITE_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_CLEAR_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_TOGGLE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_RMASK    64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_RESERVED_BIT_MASK        64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_LD_MASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_POR_VALUE        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_INTERNAL_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_EXTERNAL_DECODE_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_ALIASED_FROM     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_ZERO_TIME_OMNI   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_JTAG_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_JTAG_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_SBUS_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_SBUS_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_RAP_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_RAP_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_NUM_FIELDS       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_FID 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_SLC 31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_WIDTH       32
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_INT_SLC     31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_FMASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_HW_LD_MASK  64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_POR_VALUE   32'b00000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_FIELD_NAME  "data"


*/

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_HW_ADDR  20'b11011100010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_ADDR     30'b000000011011100010000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_id"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_WIDTH    64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_DEPTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_INT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_FIELD_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_id"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LOW_ADDR_WIDTH   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_ADDR_RANGE       19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_READ_MASK        64'b0000000000000000000000000000000000000000111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_READ_ONLY_MASK   64'b0000000000000000000000000000000000000000111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_WRITE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_WRITE_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_CLEAR_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TOGGLE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_RMASK    64'b0000000000000000000000000000000000000000111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_RESERVED_BIT_MASK        64'b1111111111111111111111111111111111111111000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_POR_VALUE        64'b0000000000000000000000000000000000000000011001100000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_INTERNAL_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_EXTERNAL_DECODE_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_ALIASED_FROM     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_ZERO_TIME_OMNI   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_HW_ACC_JTAG_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_HW_ACC_JTAG_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_HW_ACC_SBUS_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_HW_ACC_SBUS_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_HW_ACC_RAP_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_HW_ACC_RAP_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_NUM_FIELDS       6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LTBWDTH_FID      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LTBWDTH_SLC      23:20
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LTBWDTH_WIDTH    4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LTBWDTH_INT_SLC  3:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LTBWDTH_POSITION 20
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LTBWDTH_FMASK    64'b0000000000000000000000000000000000000000111100000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LTBWDTH_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LTBWDTH_POR_VALUE        4'b0110
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LTBWDTH_FIELD_NAME       "ltbwdth"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PTLWDTH_FID      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PTLWDTH_SLC      19:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PTLWDTH_WIDTH    4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PTLWDTH_INT_SLC  3:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PTLWDTH_POSITION 16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PTLWDTH_FMASK    64'b0000000000000000000000000000000000000000000011110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PTLWDTH_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PTLWDTH_POR_VALUE        4'b0110
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PTLWDTH_FIELD_NAME       "ptlwdth"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TRID_FID 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TRID_SLC 15:12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TRID_WIDTH       4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TRID_INT_SLC     3:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TRID_POSITION    12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TRID_FMASK       64'b0000000000000000000000000000000000000000000000001111000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TRID_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TRID_POR_VALUE   4'b0000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TRID_FIELD_NAME  "trid"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LNKID_FID        3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LNKID_SLC        11:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LNKID_WIDTH      4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LNKID_INT_SLC    3:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LNKID_POSITION   8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LNKID_FMASK      64'b0000000000000000000000000000000000000000000000000000111100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LNKID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LNKID_POR_VALUE  4'b0000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LNKID_FIELD_NAME "lnkid"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PHYID_FID        4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PHYID_SLC        7:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PHYID_WIDTH      4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PHYID_INT_SLC    3:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PHYID_POSITION   4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PHYID_FMASK      64'b0000000000000000000000000000000000000000000000000000000011110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PHYID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PHYID_POR_VALUE  4'b0000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PHYID_FIELD_NAME "phyid"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_GBID_FID 5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_GBID_SLC 3:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_GBID_WIDTH       4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_GBID_INT_SLC     3:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_GBID_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_GBID_FMASK       64'b0000000000000000000000000000000000000000000000000000000000001111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_GBID_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_GBID_POR_VALUE   4'b0001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_GBID_FIELD_NAME  "gbid"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_HW_ADDR 20'b11011100010000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_ADDR    30'b000000011011100010000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_WIDTH   64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_DEPTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_INT_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_FIELD_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_LOW_ADDR_WIDTH  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_ADDR_RANGE      19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_READ_MASK       64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_READ_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_WRITE_MASK      64'b0000000000000000000000000000000010000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_WRITE_ONLY_MASK 64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RMASK   64'b0000000000000000000000000000000010000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RESERVED_BIT_MASK       64'b1111111111111111111111111111111101111111111111111111000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_HW_LD_MASK      64'b0000000000000000000000000000000010000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_INTERNAL_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_EXTERNAL_DECODE_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_ALIASED_FROM    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_ZERO_TIME_OMNI  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_HW_ACC_JTAG_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_HW_ACC_JTAG_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_HW_ACC_SBUS_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_HW_ACC_SBUS_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_HW_ACC_RAP_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_HW_ACC_RAP_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_NUM_FIELDS      11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTWE_FID       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTWE_SLC       31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTWE_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTWE_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTWE_POSITION  31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTWE_FMASK     64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTWE_HW_LD_MASK        64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTWE_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTWE_FIELD_NAME        "rstwe"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTUNUSED_FID   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTUNUSED_SLC   11:9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTUNUSED_WIDTH 3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTUNUSED_INT_SLC       2:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTUNUSED_POSITION      9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTUNUSED_FMASK 64'b0000000000000000000000000000000000000000000000000000111000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTUNUSED_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000111000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTUNUSED_POR_VALUE     3'b000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTUNUSED_FIELD_NAME    "rstunused"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTERROR_FID    2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTERROR_SLC    8:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTERROR_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTERROR_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTERROR_POSITION       8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTERROR_FMASK  64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTERROR_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTERROR_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTERROR_FIELD_NAME     "rsterror"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXLINK_FID   3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXLINK_SLC   7:7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXLINK_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXLINK_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXLINK_POSITION      7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXLINK_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXLINK_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXLINK_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXLINK_FIELD_NAME    "rsttxlink"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXLINK_FID   4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXLINK_SLC   6:6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXLINK_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXLINK_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXLINK_POSITION      6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXLINK_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXLINK_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXLINK_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXLINK_FIELD_NAME    "rstrxlink"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTSMLINK_FID   5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTSMLINK_SLC   5:5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTSMLINK_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTSMLINK_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTSMLINK_POSITION      5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTSMLINK_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTSMLINK_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTSMLINK_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTSMLINK_FIELD_NAME    "rstsmlink"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTLTSSM_FID    6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTLTSSM_SLC    4:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTLTSSM_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTLTSSM_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTLTSSM_POSITION       4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTLTSSM_FMASK  64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTLTSSM_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTLTSSM_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTLTSSM_FIELD_NAME     "rstltssm"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPHY_FID    7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPHY_SLC    3:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPHY_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPHY_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPHY_POSITION       3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPHY_FMASK  64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPHY_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPHY_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPHY_FIELD_NAME     "rsttxphy"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPHY_FID    8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPHY_SLC    2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPHY_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPHY_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPHY_POSITION       2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPHY_FMASK  64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPHY_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPHY_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPHY_FIELD_NAME     "rstrxphy"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPCS_FID    9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPCS_SLC    1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPCS_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPCS_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPCS_POSITION       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPCS_FMASK  64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPCS_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPCS_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPCS_FIELD_NAME     "rsttxpcs"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPCS_FID    10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPCS_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPCS_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPCS_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPCS_POSITION       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPCS_FMASK  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPCS_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPCS_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPCS_FIELD_NAME     "rstrxpcs"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_HW_ADDR    20'b11011100010000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_ADDR       30'b000000011011100010000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_dbg_stat"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_WIDTH      64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEPTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_INT_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_POSITION   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_dbg_stat"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_LOW_ADDR_WIDTH     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_ADDR_RANGE 19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_READ_MASK  64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_READ_ONLY_MASK     64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_RMASK      64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_RESERVED_BIT_MASK  64'b1111111111111111111111111111111111111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_POR_VALUE  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_INTERNAL_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_EXTERNAL_DECODE_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_ALIASED_FROM       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_ZERO_TIME_OMNI     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_HW_ACC_JTAG_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_HW_ACC_JTAG_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_HW_ACC_SBUS_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_HW_ACC_SBUS_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_HW_ACC_RAP_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_HW_ACC_RAP_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_NUM_FIELDS 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGB_FID 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGB_SLC 15:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGB_WIDTH       8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGB_INT_SLC     7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGB_POSITION    8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGB_FMASK       64'b0000000000000000000000000000000000000000000000001111111100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGB_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGB_POR_VALUE   8'b00000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGB_FIELD_NAME  "debugb"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGA_FID 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGA_SLC 7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGA_WIDTH       8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGA_INT_SLC     7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGA_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGA_FMASK       64'b0000000000000000000000000000000000000000000000000000000011111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGA_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGA_POR_VALUE   8'b00000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGA_FIELD_NAME  "debuga"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_HW_ADDR  20'b11011100010000000011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_ADDR     30'b000000011011100010000000011000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_dbg_config"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_WIDTH    64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DEPTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_INT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_FIELD_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_dbg_config"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_LOW_ADDR_WIDTH   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_ADDR_RANGE       19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_READ_MASK        64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_READ_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_WRITE_MASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_WRITE_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_CLEAR_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_TOGGLE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_RMASK    64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_RESERVED_BIT_MASK        64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_POR_VALUE        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_INTERNAL_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_EXTERNAL_DECODE_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_ALIASED_FROM     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_ZERO_TIME_OMNI   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_HW_ACC_JTAG_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_HW_ACC_JTAG_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_HW_ACC_SBUS_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_HW_ACC_SBUS_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_HW_ACC_RAP_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_HW_ACC_RAP_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_NUM_FIELDS       4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_BLK_SEL_FID        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_BLK_SEL_SLC        31:24
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_BLK_SEL_WIDTH      8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_BLK_SEL_INT_SLC    7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_BLK_SEL_POSITION   24
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_BLK_SEL_FMASK      64'b0000000000000000000000000000000011111111000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_BLK_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_BLK_SEL_POR_VALUE  8'b00000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_BLK_SEL_FIELD_NAME "dbugb_blk_sel"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_SIG_SEL_FID        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_SIG_SEL_SLC        23:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_SIG_SEL_WIDTH      8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_SIG_SEL_INT_SLC    7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_SIG_SEL_POSITION   16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_SIG_SEL_FMASK      64'b0000000000000000000000000000000000000000111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_SIG_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_SIG_SEL_POR_VALUE  8'b00000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_SIG_SEL_FIELD_NAME "dbugb_sig_sel"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_BLK_SEL_FID        2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_BLK_SEL_SLC        15:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_BLK_SEL_WIDTH      8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_BLK_SEL_INT_SLC    7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_BLK_SEL_POSITION   8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_BLK_SEL_FMASK      64'b0000000000000000000000000000000000000000000000001111111100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_BLK_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_BLK_SEL_POR_VALUE  8'b00000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_BLK_SEL_FIELD_NAME "dbuga_blk_sel"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_SIG_SEL_FID        3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_SIG_SEL_SLC        7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_SIG_SEL_WIDTH      8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_SIG_SEL_INT_SLC    7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_SIG_SEL_POSITION   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_SIG_SEL_FMASK      64'b0000000000000000000000000000000000000000000000000000000011111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_SIG_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_SIG_SEL_POR_VALUE  8'b00000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_SIG_SEL_FIELD_NAME "dbuga_sig_sel"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HW_ADDR  20'b11011100010000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_ADDR     30'b000000011011100010000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_cntl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WIDTH    64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DEPTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_INT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_FIELD_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_cntl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LOW_ADDR_WIDTH   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_ADDR_RANGE       19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_READ_MASK        64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_READ_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WRITE_MASK       64'b0000000000000000000000000000000010000000000000000000001011111000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WRITE_ONLY_MASK  64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_SET_MASK 64'b0000000000000000000000000000000000000000000000000000110100000111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_CLEAR_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_TOGGLE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RMASK    64'b0000000000000000000000000000000010000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RESERVED_BIT_MASK        64'b1111111111111111111111111111111101111111111111111111000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_POR_VALUE        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_INTERNAL_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_EXTERNAL_DECODE_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_ALIASED_FROM     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_ZERO_TIME_OMNI   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HW_ACC_JTAG_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HW_ACC_JTAG_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HW_ACC_SBUS_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HW_ACC_SBUS_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HW_ACC_RAP_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HW_ACC_RAP_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_NUM_FIELDS       10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WR_ENABLE_FID    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WR_ENABLE_SLC    31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WR_ENABLE_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WR_ENABLE_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WR_ENABLE_POSITION       31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WR_ENABLE_FMASK  64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WR_ENABLE_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WR_ENABLE_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WR_ENABLE_FIELD_NAME     "wr_enable"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RCOVER_TO_CONFIG_FID     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RCOVER_TO_CONFIG_SLC     11:11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RCOVER_TO_CONFIG_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RCOVER_TO_CONFIG_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RCOVER_TO_CONFIG_POSITION        11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RCOVER_TO_CONFIG_FMASK   64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RCOVER_TO_CONFIG_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RCOVER_TO_CONFIG_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RCOVER_TO_CONFIG_FIELD_NAME      "rcover_to_config"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LO_TO_RECOVER_FID        2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LO_TO_RECOVER_SLC        10:10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LO_TO_RECOVER_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LO_TO_RECOVER_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LO_TO_RECOVER_POSITION   10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LO_TO_RECOVER_FMASK      64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LO_TO_RECOVER_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LO_TO_RECOVER_POR_VALUE  1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LO_TO_RECOVER_FIELD_NAME "lo_to_recover"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_0_FID     3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_0_SLC     9:9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_0_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_0_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_0_POSITION        9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_0_FMASK   64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_0_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_0_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_0_FIELD_NAME      "unused_0"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_GO_TO_DETECT_FID 4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_GO_TO_DETECT_SLC 8:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_GO_TO_DETECT_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_GO_TO_DETECT_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_GO_TO_DETECT_POSITION    8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_GO_TO_DETECT_FMASK       64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_GO_TO_DETECT_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_GO_TO_DETECT_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_GO_TO_DETECT_FIELD_NAME  "go_to_detect"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_1_FID     5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_1_SLC     7:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_1_WIDTH   4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_1_INT_SLC 3:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_1_POSITION        4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_1_FMASK   64'b0000000000000000000000000000000000000000000000000000000011110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_1_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000011110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_1_POR_VALUE       4'b0000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_1_FIELD_NAME      "unused_1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DISABLE_SCRAMBLING_FID   6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DISABLE_SCRAMBLING_SLC   3:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DISABLE_SCRAMBLING_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DISABLE_SCRAMBLING_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DISABLE_SCRAMBLING_POSITION      3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DISABLE_SCRAMBLING_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DISABLE_SCRAMBLING_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DISABLE_SCRAMBLING_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DISABLE_SCRAMBLING_FIELD_NAME    "disable_scrambling"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_LOOPBK_REQ_FID      7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_LOOPBK_REQ_SLC      2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_LOOPBK_REQ_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_LOOPBK_REQ_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_LOOPBK_REQ_POSITION 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_LOOPBK_REQ_FMASK    64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_LOOPBK_REQ_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_LOOPBK_REQ_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_LOOPBK_REQ_FIELD_NAME       "link_loopbk_req"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_DISABLE_REQ_FID     8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_DISABLE_REQ_SLC     1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_DISABLE_REQ_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_DISABLE_REQ_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_DISABLE_REQ_POSITION        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_DISABLE_REQ_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_DISABLE_REQ_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_DISABLE_REQ_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_DISABLE_REQ_FIELD_NAME      "link_disable_req"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HOT_RESET_FID    9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HOT_RESET_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HOT_RESET_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HOT_RESET_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HOT_RESET_POSITION       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HOT_RESET_FMASK  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HOT_RESET_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HOT_RESET_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HOT_RESET_FIELD_NAME     "hot_reset"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_HW_ADDR 20'b11011100010000000101
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_ADDR    30'b000000011011100010000000101000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_status"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_WIDTH   64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_DEPTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_INT_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_FIELD_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_status"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LOW_ADDR_WIDTH  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_ADDR_RANGE      19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_READ_MASK       64'b0000000000000000000000000000000000000000000000000001111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_READ_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000001111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_WRITE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_RMASK   64'b0000000000000000000000000000000000000000000000000001111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_RESERVED_BIT_MASK       64'b1111111111111111111111111111111111111111111111111110000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000001111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000010000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_INTERNAL_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_EXTERNAL_DECODE_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_ALIASED_FROM    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_ZERO_TIME_OMNI  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_HW_ACC_JTAG_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_HW_ACC_JTAG_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_HW_ACC_SBUS_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_HW_ACC_SBUS_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_HW_ACC_RAP_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_HW_ACC_RAP_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NUM_FIELDS      5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLOT_CLK_CONFG_PIN_FID  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLOT_CLK_CONFG_PIN_SLC  12:12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLOT_CLK_CONFG_PIN_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLOT_CLK_CONFG_PIN_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLOT_CLK_CONFG_PIN_POSITION     12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLOT_CLK_CONFG_PIN_FMASK        64'b0000000000000000000000000000000000000000000000000001000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLOT_CLK_CONFG_PIN_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000001000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLOT_CLK_CONFG_PIN_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLOT_CLK_CONFG_PIN_FIELD_NAME   "slot_clk_confg_pin"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_FID       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_SLC       11:11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_POSITION  11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_FMASK     64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_FIELD_NAME        "link_training"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_ERR_FID   2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_ERR_SLC   10:10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_ERR_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_ERR_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_ERR_POSITION      10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_ERR_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_ERR_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_ERR_FIELD_NAME    "link_training_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NEGOTIATED_WIDTH_FID    3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NEGOTIATED_WIDTH_SLC    9:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NEGOTIATED_WIDTH_WIDTH  6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NEGOTIATED_WIDTH_INT_SLC        5:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NEGOTIATED_WIDTH_POSITION       4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NEGOTIATED_WIDTH_FMASK  64'b0000000000000000000000000000000000000000000000000000001111110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NEGOTIATED_WIDTH_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000001111110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NEGOTIATED_WIDTH_POR_VALUE      6'b001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NEGOTIATED_WIDTH_FIELD_NAME     "negotiated_width"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_SPEED_FID  4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_SPEED_SLC  3:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_SPEED_WIDTH        4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_SPEED_INT_SLC      3:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_SPEED_POSITION     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_SPEED_FMASK        64'b0000000000000000000000000000000000000000000000000000000000001111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_SPEED_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000001111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_SPEED_POR_VALUE    4'b0001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_SPEED_FIELD_NAME   "link_speed"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_HW_ADDR    20'b11011100010000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_ADDR       30'b000000011011100010000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_interrupt_status"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_WIDTH      64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_DEPTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_POSITION   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_interrupt_status"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_LOW_ADDR_WIDTH     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_ADDR_RANGE 19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_READ_MASK  64'b0000000000000000000000000000000010000000000000000000000011111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_READ_ONLY_MASK     64'b0000000000000000000000000000000010000000000000000000000011111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_RMASK      64'b0000000000000000000000000000000010000000000000000000000011111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_RESERVED_BIT_MASK  64'b1111111111111111111111111111111101111111111111111111111100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_HW_LD_MASK 64'b0000000000000000000000000000000010000000000000000000000011111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_POR_VALUE  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERNAL_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_EXTERNAL_DECODE_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_ALIASED_FROM       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_ZERO_TIME_OMNI     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_HW_ACC_JTAG_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_HW_ACC_JTAG_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_HW_ACC_SBUS_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_HW_ACC_SBUS_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_HW_ACC_RAP_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_HW_ACC_RAP_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_NUM_FIELDS 9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERRUPT_FID      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERRUPT_SLC      31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERRUPT_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERRUPT_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERRUPT_POSITION 31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERRUPT_FMASK    64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERRUPT_HW_LD_MASK       64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERRUPT_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERRUPT_FIELD_NAME       "interrupt"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_2_OVFLW_FID  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_2_OVFLW_SLC  7:7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_2_OVFLW_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_2_OVFLW_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_2_OVFLW_POSITION     7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_2_OVFLW_FMASK        64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_2_OVFLW_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_2_OVFLW_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_2_OVFLW_FIELD_NAME   "int_perf_cntr_2_ovflw"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_1_OVFLW_FID  2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_1_OVFLW_SLC  6:6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_1_OVFLW_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_1_OVFLW_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_1_OVFLW_POSITION     6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_1_OVFLW_FMASK        64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_1_OVFLW_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_1_OVFLW_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_1_OVFLW_FIELD_NAME   "int_perf_cntr_1_ovflw"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LINK_LAYER_FID 3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LINK_LAYER_SLC 5:5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LINK_LAYER_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LINK_LAYER_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LINK_LAYER_POSITION    5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LINK_LAYER_FMASK       64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LINK_LAYER_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LINK_LAYER_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LINK_LAYER_FIELD_NAME  "int_link_layer"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_ERROR_FID  4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_ERROR_SLC  4:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_ERROR_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_ERROR_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_ERROR_POSITION     4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_ERROR_FMASK        64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_ERROR_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_ERROR_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_ERROR_FIELD_NAME   "int_phy_error"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LTSSM_FID      5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LTSSM_SLC      3:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LTSSM_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LTSSM_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LTSSM_POSITION 3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LTSSM_FMASK    64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LTSSM_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LTSSM_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LTSSM_FIELD_NAME       "int_ltssm"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_TX_FID     6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_TX_SLC     2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_TX_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_TX_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_TX_POSITION        2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_TX_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_TX_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_TX_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_TX_FIELD_NAME      "int_phy_tx"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_RX_FID     7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_RX_SLC     1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_RX_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_RX_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_RX_POSITION        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_RX_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_RX_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_RX_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_RX_FIELD_NAME      "int_phy_rx"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_GB_FID     8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_GB_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_GB_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_GB_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_GB_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_GB_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_GB_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_GB_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_GB_FIELD_NAME      "int_phy_gb"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_HW_ADDR      20'b11011100010000001001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_ADDR 30'b000000011011100010000001001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_interrupt_mask"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_WIDTH        64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_DEPTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_INT_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_POSITION     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_FIELD_NAME   "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_interrupt_mask"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_LOW_ADDR_WIDTH       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_ADDR_RANGE   19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_READ_MASK    64'b0000000000000000000000000000000010000000000000000000000011111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_READ_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_WRITE_MASK   64'b0000000000000000000000000000000010000000000000000000000011111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_WRITE_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_SET_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_CLEAR_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_TOGGLE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_RMASK        64'b0000000000000000000000000000000010000000000000000000000011111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_RESERVED_BIT_MASK    64'b1111111111111111111111111111111101111111111111111111111100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_POR_VALUE    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_INTERNAL_REG 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_EXTERNAL_DECODE_REG  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_ALIASED_FROM 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_ZERO_TIME_OMNI       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_HW_ACC_JTAG_RD       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_HW_ACC_JTAG_WR       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_HW_ACC_SBUS_RD       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_HW_ACC_SBUS_WR       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_HW_ACC_RAP_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_HW_ACC_RAP_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_NUM_FIELDS   9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_INTERRUPT_EN_FID 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_INTERRUPT_EN_SLC 31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_INTERRUPT_EN_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_INTERRUPT_EN_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_INTERRUPT_EN_POSITION    31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_INTERRUPT_EN_FMASK       64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_INTERRUPT_EN_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_INTERRUPT_EN_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_INTERRUPT_EN_FIELD_NAME  "msk_interrupt_en"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_2_OVFLW_FID    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_2_OVFLW_SLC    7:7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_2_OVFLW_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_2_OVFLW_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_2_OVFLW_POSITION       7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_2_OVFLW_FMASK  64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_2_OVFLW_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_2_OVFLW_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_2_OVFLW_FIELD_NAME     "msk_perf_cntr_2_ovflw"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_1_OVFLW_FID    2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_1_OVFLW_SLC    6:6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_1_OVFLW_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_1_OVFLW_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_1_OVFLW_POSITION       6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_1_OVFLW_FMASK  64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_1_OVFLW_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_1_OVFLW_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_1_OVFLW_FIELD_NAME     "msk_perf_cntr_1_ovflw"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LINK_LAYER_FID   3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LINK_LAYER_SLC   5:5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LINK_LAYER_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LINK_LAYER_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LINK_LAYER_POSITION      5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LINK_LAYER_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LINK_LAYER_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LINK_LAYER_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LINK_LAYER_FIELD_NAME    "msk_link_layer"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_ERROR_FID    4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_ERROR_SLC    4:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_ERROR_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_ERROR_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_ERROR_POSITION       4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_ERROR_FMASK  64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_ERROR_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_ERROR_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_ERROR_FIELD_NAME     "msk_phy_error"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LTSSM_FID        5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LTSSM_SLC        3:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LTSSM_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LTSSM_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LTSSM_POSITION   3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LTSSM_FMASK      64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LTSSM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LTSSM_POR_VALUE  1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LTSSM_FIELD_NAME "msk_ltssm"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_TX_FID       6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_TX_SLC       2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_TX_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_TX_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_TX_POSITION  2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_TX_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_TX_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_TX_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_TX_FIELD_NAME        "msk_phy_tx"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_RX_FID       7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_RX_SLC       1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_RX_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_RX_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_RX_POSITION  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_RX_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_RX_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_RX_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_RX_FIELD_NAME        "msk_phy_rx"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_GB_FID       8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_GB_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_GB_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_GB_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_GB_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_GB_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_GB_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_GB_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_GB_FIELD_NAME        "msk_phy_gb"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_HW_ADDR 20'b11011100010000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_ADDR    30'b000000011011100010000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr1_sel"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_WIDTH   64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_DEPTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_INT_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_FIELD_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr1_sel"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_LOW_ADDR_WIDTH  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_ADDR_RANGE      19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_READ_MASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_READ_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_WRITE_MASK      64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_RMASK   64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_RESERVED_BIT_MASK       64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_INTERNAL_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_EXTERNAL_DECODE_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_ALIASED_FROM    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_ZERO_TIME_OMNI  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_HW_ACC_JTAG_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_HW_ACC_JTAG_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_HW_ACC_SBUS_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_HW_ACC_SBUS_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_HW_ACC_RAP_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_HW_ACC_RAP_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_NUM_FIELDS      2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR2_SELECT_FID   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR2_SELECT_SLC   31:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR2_SELECT_WIDTH 16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR2_SELECT_INT_SLC       15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR2_SELECT_POSITION      16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR2_SELECT_FMASK 64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR2_SELECT_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR2_SELECT_POR_VALUE     16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR2_SELECT_FIELD_NAME    "perf_cntr2_select"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR1_SELECT_FID   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR1_SELECT_SLC   15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR1_SELECT_WIDTH 16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR1_SELECT_INT_SLC       15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR1_SELECT_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR1_SELECT_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR1_SELECT_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR1_SELECT_POR_VALUE     16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR1_SELECT_FIELD_NAME    "perf_cntr1_select"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_HW_ADDR  20'b11011100010000100010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_ADDR     30'b000000011011100010000100010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr_ctl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_WIDTH    64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_DEPTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_INT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_FIELD_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr_ctl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_LOW_ADDR_WIDTH   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_ADDR_RANGE       19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_READ_MASK        64'b0000000000000000000000000000000000000000000000000000000001101111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_READ_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_WRITE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_WRITE_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000001100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_CLEAR_MASK       64'b0000000000000000000000000000000000000000000000000000000000001111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_TOGGLE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RMASK    64'b0000000000000000000000000000000000000000000000000000000001101111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RESERVED_BIT_MASK        64'b1111111111111111111111111111111111111111111111111111111110010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000001101111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_POR_VALUE        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_INTERNAL_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_EXTERNAL_DECODE_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_ALIASED_FROM     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_ZERO_TIME_OMNI   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_HW_ACC_JTAG_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_HW_ACC_JTAG_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_HW_ACC_SBUS_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_HW_ACC_SBUS_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_HW_ACC_RAP_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_HW_ACC_RAP_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_NUM_FIELDS       6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR2_OVERFLOW_FID      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR2_OVERFLOW_SLC      6:6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR2_OVERFLOW_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR2_OVERFLOW_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR2_OVERFLOW_POSITION 6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR2_OVERFLOW_FMASK    64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR2_OVERFLOW_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR2_OVERFLOW_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR2_OVERFLOW_FIELD_NAME       "set_perf_cntr2_overflow"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR1_OVERFLOW_FID      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR1_OVERFLOW_SLC      5:5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR1_OVERFLOW_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR1_OVERFLOW_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR1_OVERFLOW_POSITION 5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR1_OVERFLOW_FMASK    64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR1_OVERFLOW_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR1_OVERFLOW_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR1_OVERFLOW_FIELD_NAME       "set_perf_cntr1_overflow"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_OVERFLOW_FID      2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_OVERFLOW_SLC      3:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_OVERFLOW_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_OVERFLOW_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_OVERFLOW_POSITION 3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_OVERFLOW_FMASK    64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_OVERFLOW_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_OVERFLOW_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_OVERFLOW_FIELD_NAME       "rst_perf_cntr2_overflow"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_FID       3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_SLC       2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_POSITION  2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_FIELD_NAME        "rst_perf_cntr2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_OVERFLOW_FID      4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_OVERFLOW_SLC      1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_OVERFLOW_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_OVERFLOW_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_OVERFLOW_POSITION 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_OVERFLOW_FMASK    64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_OVERFLOW_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_OVERFLOW_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_OVERFLOW_FIELD_NAME       "rst_perf_cntr1_overflow"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_FID       5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_FIELD_NAME        "rst_perf_cntr1"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_HW_ADDR     20'b11011100010000100100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_ADDR        30'b000000011011100010000100100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_NAME        "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_WIDTH       64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_DEPTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_INT_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_FIELD_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_LOW_ADDR_WIDTH      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_ADDR_RANGE  19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_READ_MASK   64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_READ_ONLY_MASK      64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_WRITE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SET_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_CLEAR_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_RMASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_RESERVED_BIT_MASK   64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_HW_LD_MASK  64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_INTERNAL_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_EXTERNAL_DECODE_REG 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_ALIASED_FROM        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_ZERO_TIME_OMNI      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_HW_ACC_JTAG_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_HW_ACC_JTAG_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_HW_ACC_SBUS_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_HW_ACC_SBUS_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_HW_ACC_RAP_RD       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_HW_ACC_RAP_WR       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_NUM_FIELDS  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_PERF_CNTR1_FID      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_PERF_CNTR1_SLC      31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_PERF_CNTR1_WIDTH    32
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_PERF_CNTR1_INT_SLC  31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_PERF_CNTR1_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_PERF_CNTR1_FMASK    64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_PERF_CNTR1_HW_LD_MASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_PERF_CNTR1_POR_VALUE        32'b00000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_PERF_CNTR1_FIELD_NAME       "perf_cntr1"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_HW_ADDR        20'b11011100010000100101
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_ADDR   30'b000000011011100010000100101000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_NAME   "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr1_test"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_WIDTH  64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_DEPTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_INT_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_POSITION       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_FIELD_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr1_test"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_LOW_ADDR_WIDTH 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_ADDR_RANGE     19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_READ_MASK      64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_WRITE_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_WRITE_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_SET_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_CLEAR_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_TOGGLE_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_RMASK  64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_RESERVED_BIT_MASK      64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_HW_LD_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_POR_VALUE      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_INTERNAL_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_EXTERNAL_DECODE_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_ALIASED_FROM   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_ZERO_TIME_OMNI 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_HW_ACC_JTAG_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_HW_ACC_JTAG_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_HW_ACC_SBUS_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_HW_ACC_SBUS_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_HW_ACC_RAP_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_HW_ACC_RAP_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_NUM_FIELDS     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_PERF_CNTR1_TEST_FID    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_PERF_CNTR1_TEST_SLC    31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_PERF_CNTR1_TEST_WIDTH  32
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_PERF_CNTR1_TEST_INT_SLC        31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_PERF_CNTR1_TEST_POSITION       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_PERF_CNTR1_TEST_FMASK  64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_PERF_CNTR1_TEST_HW_LD_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_PERF_CNTR1_TEST_POR_VALUE      32'b00000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_PERF_CNTR1_TEST_FIELD_NAME     "perf_cntr1_test"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_HW_ADDR     20'b11011100010000100110
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_ADDR        30'b000000011011100010000100110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_NAME        "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_WIDTH       64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_DEPTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_INT_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_FIELD_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_LOW_ADDR_WIDTH      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_ADDR_RANGE  19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_READ_MASK   64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_READ_ONLY_MASK      64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_WRITE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_SET_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_CLEAR_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_RMASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_RESERVED_BIT_MASK   64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_HW_LD_MASK  64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_INTERNAL_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_EXTERNAL_DECODE_REG 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_ALIASED_FROM        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_ZERO_TIME_OMNI      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_HW_ACC_JTAG_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_HW_ACC_JTAG_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_HW_ACC_SBUS_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_HW_ACC_SBUS_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_HW_ACC_RAP_RD       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_HW_ACC_RAP_WR       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_NUM_FIELDS  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_PERF_CNTR2_FID      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_PERF_CNTR2_SLC      31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_PERF_CNTR2_WIDTH    32
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_PERF_CNTR2_INT_SLC  31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_PERF_CNTR2_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_PERF_CNTR2_FMASK    64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_PERF_CNTR2_HW_LD_MASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_PERF_CNTR2_POR_VALUE        32'b00000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_PERF_CNTR2_FIELD_NAME       "perf_cntr2"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_HW_ADDR        20'b11011100010000100111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_ADDR   30'b000000011011100010000100111000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_NAME   "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr2_test"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_WIDTH  64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_DEPTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_INT_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_POSITION       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_FIELD_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr2_test"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_LOW_ADDR_WIDTH 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_ADDR_RANGE     19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_READ_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_WRITE_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_WRITE_ONLY_MASK        64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_SET_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_CLEAR_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_TOGGLE_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_RMASK  64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_RESERVED_BIT_MASK      64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_HW_LD_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_POR_VALUE      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_INTERNAL_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_EXTERNAL_DECODE_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_ALIASED_FROM   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_ZERO_TIME_OMNI 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_HW_ACC_JTAG_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_HW_ACC_JTAG_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_HW_ACC_SBUS_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_HW_ACC_SBUS_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_HW_ACC_RAP_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_HW_ACC_RAP_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_NUM_FIELDS     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_PERF_CNTR2_TEST_FID    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_PERF_CNTR2_TEST_SLC    31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_PERF_CNTR2_TEST_WIDTH  32
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_PERF_CNTR2_TEST_INT_SLC        31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_PERF_CNTR2_TEST_POSITION       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_PERF_CNTR2_TEST_FMASK  64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_PERF_CNTR2_TEST_HW_LD_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_PERF_CNTR2_TEST_POR_VALUE      32'b00000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_PERF_CNTR2_TEST_FIELD_NAME     "perf_cntr2_test"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_HW_ADDR   20'b11011100010001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_ADDR      30'b000000011011100010001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_config"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_WIDTH     64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_DEPTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_INT_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FIELD_NAME        "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_config"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_LOW_ADDR_WIDTH    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_ADDR_RANGE        19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000111101110
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_READ_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_WRITE_MASK        64'b0000000000000000000000000000000000000000000000000000000111101110
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_WRITE_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_SET_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_CLEAR_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TOGGLE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RMASK     64'b0000000000000000000000000000000000000000000000000000000111101110
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111000010001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_INTERNAL_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_EXTERNAL_DECODE_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_ALIASED_FROM      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_ZERO_TIME_OMNI    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_HW_ACC_JTAG_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_HW_ACC_JTAG_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_HW_ACC_SBUS_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_HW_ACC_SBUS_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_HW_ACC_RAP_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_HW_ACC_RAP_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_NUM_FIELDS        5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_VC0_EN_FID        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_VC0_EN_SLC        8:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_VC0_EN_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_VC0_EN_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_VC0_EN_POSITION   8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_VC0_EN_FMASK      64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_VC0_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_VC0_EN_POR_VALUE  1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_VC0_EN_FIELD_NAME "vc0_en"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_MAX_PAYLOAD_FID   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_MAX_PAYLOAD_SLC   7:5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_MAX_PAYLOAD_WIDTH 3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_MAX_PAYLOAD_INT_SLC       2:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_MAX_PAYLOAD_POSITION      5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_MAX_PAYLOAD_FMASK 64'b0000000000000000000000000000000000000000000000000000000011100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_MAX_PAYLOAD_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_MAX_PAYLOAD_POR_VALUE     3'b000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_MAX_PAYLOAD_FIELD_NAME    "max_payload"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TLP_XMIT_FC_EN_FID        2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TLP_XMIT_FC_EN_SLC        3:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TLP_XMIT_FC_EN_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TLP_XMIT_FC_EN_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TLP_XMIT_FC_EN_POSITION   3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TLP_XMIT_FC_EN_FMASK      64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TLP_XMIT_FC_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TLP_XMIT_FC_EN_POR_VALUE  1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TLP_XMIT_FC_EN_FIELD_NAME "tlp_xmit_fc_en"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FREQ_ACK_ENABLE_FID       3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FREQ_ACK_ENABLE_SLC       2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FREQ_ACK_ENABLE_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FREQ_ACK_ENABLE_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FREQ_ACK_ENABLE_POSITION  2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FREQ_ACK_ENABLE_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FREQ_ACK_ENABLE_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FREQ_ACK_ENABLE_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FREQ_ACK_ENABLE_FIELD_NAME        "freq_ack_enable"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RETRY_DISABLE_FID 4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RETRY_DISABLE_SLC 1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RETRY_DISABLE_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RETRY_DISABLE_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RETRY_DISABLE_POSITION    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RETRY_DISABLE_FMASK       64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RETRY_DISABLE_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RETRY_DISABLE_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RETRY_DISABLE_FIELD_NAME  "retry_disable"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_HW_ADDR     20'b11011100010001000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_ADDR        30'b000000011011100010001000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_NAME        "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_stat"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_WIDTH       64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DEPTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INT_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_FIELD_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_stat"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LOW_ADDR_WIDTH      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_ADDR_RANGE  19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_READ_MASK   64'b0000000000000000000000000000000000000000000000000000000000111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_READ_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_WRITE_MASK  64'b0000000000000000000000000000000000000000000000000000001100111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000001100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_SET_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_CLEAR_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_RMASK       64'b0000000000000000000000000000000000000000000000000000001100111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_RESERVED_BIT_MASK   64'b1111111111111111111111111111111111111111111111111111110011000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000001100111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INTERNAL_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_EXTERNAL_DECODE_REG 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_ALIASED_FROM        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_ZERO_TIME_OMNI      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_HW_ACC_JTAG_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_HW_ACC_JTAG_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_HW_ACC_SBUS_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_HW_ACC_SBUS_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_HW_ACC_RAP_RD       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_HW_ACC_RAP_WR       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_NUM_FIELDS  5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_WE_FID   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_WE_SLC   9:9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_WE_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_WE_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_WE_POSITION      9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_WE_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_WE_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_WE_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_WE_FIELD_NAME    "init_fc_sm_we"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_ST_DLUP_WE_FID  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_ST_DLUP_WE_SLC  8:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_ST_DLUP_WE_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_ST_DLUP_WE_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_ST_DLUP_WE_POSITION     8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_ST_DLUP_WE_FMASK        64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_ST_DLUP_WE_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_ST_DLUP_WE_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_ST_DLUP_WE_FIELD_NAME   "lnk_st_dlup_we"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_FID  2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_SLC  5:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_WIDTH        2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_INT_SLC      1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_POSITION     4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_FMASK        64'b0000000000000000000000000000000000000000000000000000000000110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_POR_VALUE    2'b00
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_FIELD_NAME   "init_fc_sm_sts"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_FID        3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_SLC        3:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_POSITION   3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_FMASK      64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_POR_VALUE  1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_FIELD_NAME "dlup_sts"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_FID      4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_SLC      2:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_WIDTH    3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_INT_SLC  2:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_FMASK    64'b0000000000000000000000000000000000000000000000000000000000000111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_POR_VALUE        3'b001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_FIELD_NAME       "lnk_state_mach_sts"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_HW_ADDR  20'b11011100010001000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_ADDR     30'b000000011011100010001000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_err_int"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_WIDTH    64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_DEPTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_FIELD_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_err_int"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_LOW_ADDR_WIDTH   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_ADDR_RANGE       19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_READ_MASK        64'b0000000000000000000000000000000010000000011101110000001111110111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_READ_ONLY_MASK   64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_WRITE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_WRITE_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_CLEAR_MASK       64'b0000000000000000000000000000000000000000011101110000001111110111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_TOGGLE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_RMASK    64'b0000000000000000000000000000000010000000011101110000001111110111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_RESERVED_BIT_MASK        64'b1111111111111111111111111111111101111111100010001111110000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_HW_LD_MASK       64'b0000000000000000000000000000000000000000011101110000001111110111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_POR_VALUE        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INTERNAL_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_EXTERNAL_DECODE_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_ALIASED_FROM     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_ZERO_TIME_OMNI   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_HW_ACC_JTAG_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_HW_ACC_JTAG_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_HW_ACC_SBUS_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_HW_ACC_SBUS_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_HW_ACC_RAP_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_HW_ACC_RAP_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_NUM_FIELDS       16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_LINK_ERR_ACT_FID     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_LINK_ERR_ACT_SLC     31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_LINK_ERR_ACT_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_LINK_ERR_ACT_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_LINK_ERR_ACT_POSITION        31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_LINK_ERR_ACT_FMASK   64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_LINK_ERR_ACT_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_LINK_ERR_ACT_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_LINK_ERR_ACT_FIELD_NAME      "int_link_err_act"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_UNSPRTD_DLLP_FID     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_UNSPRTD_DLLP_SLC     22:22
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_UNSPRTD_DLLP_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_UNSPRTD_DLLP_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_UNSPRTD_DLLP_POSITION        22
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_UNSPRTD_DLLP_FMASK   64'b0000000000000000000000000000000000000000010000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_UNSPRTD_DLLP_HW_LD_MASK      64'b0000000000000000000000000000000000000000010000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_UNSPRTD_DLLP_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_UNSPRTD_DLLP_FIELD_NAME      "int_unsprtd_dllp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLLP_RCV_ERR_FID     2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLLP_RCV_ERR_SLC     21:21
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLLP_RCV_ERR_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLLP_RCV_ERR_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLLP_RCV_ERR_POSITION        21
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLLP_RCV_ERR_FMASK   64'b0000000000000000000000000000000000000000001000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLLP_RCV_ERR_HW_LD_MASK      64'b0000000000000000000000000000000000000000001000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLLP_RCV_ERR_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLLP_RCV_ERR_FIELD_NAME      "int_dllp_rcv_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_DLLP_FID 3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_DLLP_SLC 20:20
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_DLLP_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_DLLP_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_DLLP_POSITION    20
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_DLLP_FMASK       64'b0000000000000000000000000000000000000000000100000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_DLLP_HW_LD_MASK  64'b0000000000000000000000000000000000000000000100000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_DLLP_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_DLLP_FIELD_NAME  "int_bad_dllp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_TLP_RCV_ERR_FID      4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_TLP_RCV_ERR_SLC      18:18
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_TLP_RCV_ERR_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_TLP_RCV_ERR_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_TLP_RCV_ERR_POSITION 18
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_TLP_RCV_ERR_FMASK    64'b0000000000000000000000000000000000000000000001000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_TLP_RCV_ERR_HW_LD_MASK       64'b0000000000000000000000000000000000000000000001000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_TLP_RCV_ERR_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_TLP_RCV_ERR_FIELD_NAME       "int_tlp_rcv_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SRC_ERR_TLP_FID      5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SRC_ERR_TLP_SLC      17:17
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SRC_ERR_TLP_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SRC_ERR_TLP_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SRC_ERR_TLP_POSITION 17
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SRC_ERR_TLP_FMASK    64'b0000000000000000000000000000000000000000000000100000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SRC_ERR_TLP_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000100000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SRC_ERR_TLP_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SRC_ERR_TLP_FIELD_NAME       "int_src_err_tlp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_TLP_FID  6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_TLP_SLC  16:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_TLP_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_TLP_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_TLP_POSITION     16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_TLP_FMASK        64'b0000000000000000000000000000000000000000000000010000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_TLP_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000010000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_TLP_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_TLP_FIELD_NAME   "int_bad_tlp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_UDF_ERR_FID 7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_UDF_ERR_SLC 9:9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_UDF_ERR_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_UDF_ERR_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_UDF_ERR_POSITION    9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_UDF_ERR_FMASK       64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_UDF_ERR_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_UDF_ERR_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_UDF_ERR_FIELD_NAME  "int_rtry_buf_udf_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_OVF_ERR_FID 8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_OVF_ERR_SLC 8:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_OVF_ERR_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_OVF_ERR_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_OVF_ERR_POSITION    8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_OVF_ERR_FMASK       64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_OVF_ERR_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_OVF_ERR_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_OVF_ERR_FIELD_NAME  "int_rtry_buf_ovf_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TLP_MIN_ERR_FID   9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TLP_MIN_ERR_SLC   7:7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TLP_MIN_ERR_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TLP_MIN_ERR_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TLP_MIN_ERR_POSITION      7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TLP_MIN_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TLP_MIN_ERR_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TLP_MIN_ERR_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TLP_MIN_ERR_FIELD_NAME    "int_eg_tlp_min_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TRNC_FRM_ERR_FID  10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TRNC_FRM_ERR_SLC  6:6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TRNC_FRM_ERR_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TRNC_FRM_ERR_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TRNC_FRM_ERR_POSITION     6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TRNC_FRM_ERR_FMASK        64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TRNC_FRM_ERR_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TRNC_FRM_ERR_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TRNC_FRM_ERR_FIELD_NAME   "int_eg_trnc_frm_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_PE_FID      11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_PE_SLC      5:5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_PE_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_PE_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_PE_POSITION 5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_PE_FMASK    64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_PE_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_PE_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_PE_FIELD_NAME       "int_rtry_buf_pe"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EGRESS_PE_FID        12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EGRESS_PE_SLC        4:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EGRESS_PE_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EGRESS_PE_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EGRESS_PE_POSITION   4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EGRESS_PE_FMASK      64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EGRESS_PE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EGRESS_PE_POR_VALUE  1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EGRESS_PE_FIELD_NAME "int_egress_pe"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_TMR_TO_FID     13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_TMR_TO_SLC     2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_TMR_TO_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_TMR_TO_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_TMR_TO_POSITION        2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_TMR_TO_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_TMR_TO_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_TMR_TO_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_TMR_TO_FIELD_NAME      "int_rplay_tmr_to"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_NUM_RO_FID     14
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_NUM_RO_SLC     1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_NUM_RO_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_NUM_RO_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_NUM_RO_POSITION        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_NUM_RO_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_NUM_RO_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_NUM_RO_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_NUM_RO_FIELD_NAME      "int_rplay_num_ro"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLNK_PES_FID 15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLNK_PES_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLNK_PES_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLNK_PES_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLNK_PES_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLNK_PES_FMASK       64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLNK_PES_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLNK_PES_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLNK_PES_FIELD_NAME  "int_dlnk_pes"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_HW_ADDR  20'b11011100010001000011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_ADDR     30'b000000011011100010001000011000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_err_tst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_WIDTH    64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_DEPTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_INT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_FIELD_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_err_tst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_LOW_ADDR_WIDTH   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_ADDR_RANGE       19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_READ_MASK        64'b0000000000000000000000000000000000000000011101110000001111110111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_READ_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_WRITE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_WRITE_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_SET_MASK 64'b0000000000000000000000000000000000000000011101110000001111110111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_CLEAR_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TOGGLE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_RMASK    64'b0000000000000000000000000000000000000000011101110000001111110111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_RESERVED_BIT_MASK        64'b1111111111111111111111111111111111111111100010001111110000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_HW_LD_MASK       64'b0000000000000000000000000000000000000000011101110000001111110111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_POR_VALUE        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_INTERNAL_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_EXTERNAL_DECODE_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_ALIASED_FROM     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_ZERO_TIME_OMNI   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_HW_ACC_JTAG_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_HW_ACC_JTAG_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_HW_ACC_SBUS_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_HW_ACC_SBUS_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_HW_ACC_RAP_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_HW_ACC_RAP_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_NUM_FIELDS       15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_UNSPRTD_DLLP_FID     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_UNSPRTD_DLLP_SLC     22:22
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_UNSPRTD_DLLP_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_UNSPRTD_DLLP_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_UNSPRTD_DLLP_POSITION        22
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_UNSPRTD_DLLP_FMASK   64'b0000000000000000000000000000000000000000010000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_UNSPRTD_DLLP_HW_LD_MASK      64'b0000000000000000000000000000000000000000010000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_UNSPRTD_DLLP_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_UNSPRTD_DLLP_FIELD_NAME      "tst_unsprtd_dllp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLLP_RCV_ERR_FID     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLLP_RCV_ERR_SLC     21:21
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLLP_RCV_ERR_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLLP_RCV_ERR_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLLP_RCV_ERR_POSITION        21
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLLP_RCV_ERR_FMASK   64'b0000000000000000000000000000000000000000001000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLLP_RCV_ERR_HW_LD_MASK      64'b0000000000000000000000000000000000000000001000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLLP_RCV_ERR_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLLP_RCV_ERR_FIELD_NAME      "tst_dllp_rcv_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_DLLP_FID 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_DLLP_SLC 20:20
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_DLLP_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_DLLP_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_DLLP_POSITION    20
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_DLLP_FMASK       64'b0000000000000000000000000000000000000000000100000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_DLLP_HW_LD_MASK  64'b0000000000000000000000000000000000000000000100000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_DLLP_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_DLLP_FIELD_NAME  "tst_bad_dllp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_TLP_RCV_ERR_FID      3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_TLP_RCV_ERR_SLC      18:18
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_TLP_RCV_ERR_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_TLP_RCV_ERR_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_TLP_RCV_ERR_POSITION 18
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_TLP_RCV_ERR_FMASK    64'b0000000000000000000000000000000000000000000001000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_TLP_RCV_ERR_HW_LD_MASK       64'b0000000000000000000000000000000000000000000001000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_TLP_RCV_ERR_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_TLP_RCV_ERR_FIELD_NAME       "tst_tlp_rcv_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_SRC_ERR_TLP_FID      4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_SRC_ERR_TLP_SLC      17:17
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_SRC_ERR_TLP_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_SRC_ERR_TLP_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_SRC_ERR_TLP_POSITION 17
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_SRC_ERR_TLP_FMASK    64'b0000000000000000000000000000000000000000000000100000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_SRC_ERR_TLP_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000100000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_SRC_ERR_TLP_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_SRC_ERR_TLP_FIELD_NAME       "tst_src_err_tlp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_TLP_FID  5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_TLP_SLC  16:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_TLP_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_TLP_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_TLP_POSITION     16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_TLP_FMASK        64'b0000000000000000000000000000000000000000000000010000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_TLP_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000010000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_TLP_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_TLP_FIELD_NAME   "tst_bad_tlp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_UDF_ERR_FID 6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_UDF_ERR_SLC 9:9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_UDF_ERR_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_UDF_ERR_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_UDF_ERR_POSITION    9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_UDF_ERR_FMASK       64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_UDF_ERR_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_UDF_ERR_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_UDF_ERR_FIELD_NAME  "tst_rtry_buf_udf_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_OVF_FID     7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_OVF_SLC     8:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_OVF_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_OVF_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_OVF_POSITION        8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_OVF_FMASK   64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_OVF_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_OVF_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_OVF_FIELD_NAME      "tst_rtry_buf_ovf"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TLP_MIN_ERR_FID   8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TLP_MIN_ERR_SLC   7:7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TLP_MIN_ERR_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TLP_MIN_ERR_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TLP_MIN_ERR_POSITION      7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TLP_MIN_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TLP_MIN_ERR_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TLP_MIN_ERR_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TLP_MIN_ERR_FIELD_NAME    "tst_eg_tlp_min_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TRNC_FRM_ERR_FID  9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TRNC_FRM_ERR_SLC  6:6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TRNC_FRM_ERR_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TRNC_FRM_ERR_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TRNC_FRM_ERR_POSITION     6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TRNC_FRM_ERR_FMASK        64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TRNC_FRM_ERR_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TRNC_FRM_ERR_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TRNC_FRM_ERR_FIELD_NAME   "tst_eg_trnc_frm_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_PE_FID      10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_PE_SLC      5:5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_PE_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_PE_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_PE_POSITION 5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_PE_FMASK    64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_PE_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_PE_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_PE_FIELD_NAME       "tst_rtry_buf_pe"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EGRESS_PE_FID        11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EGRESS_PE_SLC        4:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EGRESS_PE_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EGRESS_PE_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EGRESS_PE_POSITION   4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EGRESS_PE_FMASK      64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EGRESS_PE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EGRESS_PE_POR_VALUE  1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EGRESS_PE_FIELD_NAME "tst_egress_pe"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_TMR_TO_FID     12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_TMR_TO_SLC     2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_TMR_TO_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_TMR_TO_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_TMR_TO_POSITION        2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_TMR_TO_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_TMR_TO_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_TMR_TO_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_TMR_TO_FIELD_NAME      "tst_rplay_tmr_to"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_NUM_RO_FID     13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_NUM_RO_SLC     1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_NUM_RO_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_NUM_RO_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_NUM_RO_POSITION        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_NUM_RO_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_NUM_RO_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_NUM_RO_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_NUM_RO_FIELD_NAME      "tst_rplay_num_ro"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLNK_PES_FID 14
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLNK_PES_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLNK_PES_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLNK_PES_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLNK_PES_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLNK_PES_FMASK       64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLNK_PES_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLNK_PES_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLNK_PES_FIELD_NAME  "tst_dlnk_pes"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_HW_ADDR  20'b11011100010001000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_ADDR     30'b000000011011100010001000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_err_msk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_WIDTH    64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_DEPTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_INT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_FIELD_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_err_msk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_LOW_ADDR_WIDTH   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_ADDR_RANGE       19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_READ_MASK        64'b0000000000000000000000000000000010000000011101110000001111110111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_READ_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_WRITE_MASK       64'b0000000000000000000000000000000010000000011101110000001111110111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_WRITE_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_CLEAR_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_TOGGLE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_RMASK    64'b0000000000000000000000000000000010000000011101110000001111110111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_RESERVED_BIT_MASK        64'b1111111111111111111111111111111101111111100010001111110000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_POR_VALUE        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_INTERNAL_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_EXTERNAL_DECODE_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_ALIASED_FROM     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_ZERO_TIME_OMNI   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_HW_ACC_JTAG_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_HW_ACC_JTAG_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_HW_ACC_SBUS_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_HW_ACC_SBUS_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_HW_ACC_RAP_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_HW_ACC_RAP_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_NUM_FIELDS       16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_LINK_ERR_ACT_FID     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_LINK_ERR_ACT_SLC     31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_LINK_ERR_ACT_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_LINK_ERR_ACT_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_LINK_ERR_ACT_POSITION        31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_LINK_ERR_ACT_FMASK   64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_LINK_ERR_ACT_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_LINK_ERR_ACT_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_LINK_ERR_ACT_FIELD_NAME      "msk_link_err_act"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_UNSPRTD_DLLP_FID     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_UNSPRTD_DLLP_SLC     22:22
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_UNSPRTD_DLLP_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_UNSPRTD_DLLP_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_UNSPRTD_DLLP_POSITION        22
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_UNSPRTD_DLLP_FMASK   64'b0000000000000000000000000000000000000000010000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_UNSPRTD_DLLP_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_UNSPRTD_DLLP_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_UNSPRTD_DLLP_FIELD_NAME      "msk_unsprtd_dllp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLLP_RCV_ERR_FID     2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLLP_RCV_ERR_SLC     21:21
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLLP_RCV_ERR_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLLP_RCV_ERR_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLLP_RCV_ERR_POSITION        21
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLLP_RCV_ERR_FMASK   64'b0000000000000000000000000000000000000000001000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLLP_RCV_ERR_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLLP_RCV_ERR_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLLP_RCV_ERR_FIELD_NAME      "msk_dllp_rcv_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_DLLP_FID 3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_DLLP_SLC 20:20
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_DLLP_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_DLLP_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_DLLP_POSITION    20
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_DLLP_FMASK       64'b0000000000000000000000000000000000000000000100000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_DLLP_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_DLLP_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_DLLP_FIELD_NAME  "msk_bad_dllp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_TLP_RCV_ERR_FID      4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_TLP_RCV_ERR_SLC      18:18
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_TLP_RCV_ERR_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_TLP_RCV_ERR_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_TLP_RCV_ERR_POSITION 18
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_TLP_RCV_ERR_FMASK    64'b0000000000000000000000000000000000000000000001000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_TLP_RCV_ERR_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_TLP_RCV_ERR_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_TLP_RCV_ERR_FIELD_NAME       "msk_tlp_rcv_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_SRC_ERR_TLP_FID      5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_SRC_ERR_TLP_SLC      17:17
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_SRC_ERR_TLP_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_SRC_ERR_TLP_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_SRC_ERR_TLP_POSITION 17
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_SRC_ERR_TLP_FMASK    64'b0000000000000000000000000000000000000000000000100000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_SRC_ERR_TLP_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_SRC_ERR_TLP_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_SRC_ERR_TLP_FIELD_NAME       "msk_src_err_tlp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_TLP_FID  6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_TLP_SLC  16:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_TLP_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_TLP_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_TLP_POSITION     16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_TLP_FMASK        64'b0000000000000000000000000000000000000000000000010000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_TLP_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_TLP_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_TLP_FIELD_NAME   "msk_bad_tlp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_UNF_OVF_FID     7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_UNF_OVF_SLC     9:9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_UNF_OVF_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_UNF_OVF_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_UNF_OVF_POSITION        9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_UNF_OVF_FMASK   64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_UNF_OVF_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_UNF_OVF_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_UNF_OVF_FIELD_NAME      "msk_rtry_unf_ovf"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_OVF_FID     8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_OVF_SLC     8:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_OVF_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_OVF_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_OVF_POSITION        8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_OVF_FMASK   64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_OVF_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_OVF_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_OVF_FIELD_NAME      "msk_rtry_buf_ovf"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TLP_MIN_ERR_FID   9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TLP_MIN_ERR_SLC   7:7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TLP_MIN_ERR_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TLP_MIN_ERR_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TLP_MIN_ERR_POSITION      7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TLP_MIN_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TLP_MIN_ERR_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TLP_MIN_ERR_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TLP_MIN_ERR_FIELD_NAME    "msk_eg_tlp_min_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TRNC_FRM_ERR_FID  10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TRNC_FRM_ERR_SLC  6:6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TRNC_FRM_ERR_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TRNC_FRM_ERR_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TRNC_FRM_ERR_POSITION     6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TRNC_FRM_ERR_FMASK        64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TRNC_FRM_ERR_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TRNC_FRM_ERR_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TRNC_FRM_ERR_FIELD_NAME   "msk_eg_trnc_frm_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_PE_FID      11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_PE_SLC      5:5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_PE_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_PE_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_PE_POSITION 5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_PE_FMASK    64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_PE_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_PE_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_PE_FIELD_NAME       "msk_rtry_buf_pe"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EGRESS_PE_FID        12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EGRESS_PE_SLC        4:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EGRESS_PE_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EGRESS_PE_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EGRESS_PE_POSITION   4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EGRESS_PE_FMASK      64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EGRESS_PE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EGRESS_PE_POR_VALUE  1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EGRESS_PE_FIELD_NAME "msk_egress_pe"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_TMR_TO_FID     13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_TMR_TO_SLC     2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_TMR_TO_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_TMR_TO_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_TMR_TO_POSITION        2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_TMR_TO_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_TMR_TO_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_TMR_TO_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_TMR_TO_FIELD_NAME      "msk_rplay_tmr_to"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_NUM_RO_FID     14
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_NUM_RO_SLC     1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_NUM_RO_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_NUM_RO_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_NUM_RO_POSITION        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_NUM_RO_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_NUM_RO_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_NUM_RO_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_NUM_RO_FIELD_NAME      "msk_rplay_num_ro"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLNK_PES_FID 15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLNK_PES_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLNK_PES_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLNK_PES_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLNK_PES_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLNK_PES_FMASK       64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLNK_PES_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLNK_PES_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLNK_PES_FIELD_NAME  "msk_dlnk_pes"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_HW_ADDR  20'b11011100010001001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_ADDR     30'b000000011011100010001001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_fc_up_cntl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_WIDTH    64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_DEPTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_INT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FIELD_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_fc_up_cntl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_LOW_ADDR_WIDTH   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_ADDR_RANGE       19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_READ_MASK        64'b0000000000000000000000000000000000000000000000000000000000000111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_READ_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_WRITE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_WRITE_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_CLEAR_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_TOGGLE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_RMASK    64'b0000000000000000000000000000000000000000000000000000000000000111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_RESERVED_BIT_MASK        64'b1111111111111111111111111111111111111111111111111111111111111000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_POR_VALUE        64'b0000000000000000000000000000000000000000000000000000000000000011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_INTERNAL_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_EXTERNAL_DECODE_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_ALIASED_FROM     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_ZERO_TIME_OMNI   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_HW_ACC_JTAG_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_HW_ACC_JTAG_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_HW_ACC_SBUS_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_HW_ACC_SBUS_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_HW_ACC_RAP_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_HW_ACC_RAP_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_NUM_FIELDS       3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_C_EN_FID   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_C_EN_SLC   2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_C_EN_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_C_EN_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_C_EN_POSITION      2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_C_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_C_EN_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_C_EN_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_C_EN_FIELD_NAME    "fc0_u_c_en"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_NP_EN_FID  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_NP_EN_SLC  1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_NP_EN_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_NP_EN_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_NP_EN_POSITION     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_NP_EN_FMASK        64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_NP_EN_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_NP_EN_POR_VALUE    1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_NP_EN_FIELD_NAME   "fc0_u_np_en"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_P_EN_FID   2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_P_EN_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_P_EN_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_P_EN_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_P_EN_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_P_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_P_EN_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_P_EN_POR_VALUE     1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_P_EN_FIELD_NAME    "fc0_u_p_en"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_HW_ADDR        20'b11011100010001001100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_ADDR   30'b000000011011100010001001100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_NAME   "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_fc_up_to_val"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_WIDTH  64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_DEPTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_INT_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_POSITION       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FIELD_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_fc_up_to_val"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_LOW_ADDR_WIDTH 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_ADDR_RANGE     19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_READ_MASK      64'b0000000000000000000000000000000000000000000000000111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_WRITE_MASK     64'b0000000000000000000000000000000000000000000000000111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_WRITE_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_SET_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_CLEAR_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_TOGGLE_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_RMASK  64'b0000000000000000000000000000000000000000000000000111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_RESERVED_BIT_MASK      64'b1111111111111111111111111111111111111111111111111000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_POR_VALUE      64'b0000000000000000000000000000000000000000000000000001110101001100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_INTERNAL_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_EXTERNAL_DECODE_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_ALIASED_FROM   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_ZERO_TIME_OMNI 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_HW_ACC_JTAG_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_HW_ACC_JTAG_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_HW_ACC_SBUS_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_HW_ACC_SBUS_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_HW_ACC_RAP_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_HW_ACC_RAP_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_NUM_FIELDS     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FC_UPDATE_TO_FID       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FC_UPDATE_TO_SLC       14:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FC_UPDATE_TO_WIDTH     15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FC_UPDATE_TO_INT_SLC   14:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FC_UPDATE_TO_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FC_UPDATE_TO_FMASK     64'b0000000000000000000000000000000000000000000000000111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FC_UPDATE_TO_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FC_UPDATE_TO_POR_VALUE 15'b001110101001100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FC_UPDATE_TO_FIELD_NAME        "fc_update_to"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_HW_ADDR 20'b11011100010001001101
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_ADDR    30'b000000011011100010001001101000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_vco_fc_cntl_up_tmr0"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_WIDTH   64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_DEPTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_INT_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_FIELD_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_vco_fc_cntl_up_tmr0"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_LOW_ADDR_WIDTH  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_ADDR_RANGE      19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_READ_MASK       64'b0000000000000000000000000000000001111111111111110111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_READ_ONLY_MASK  64'b0000000000000000000000000000000001111111111111110111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_WRITE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_RMASK   64'b0000000000000000000000000000000001111111111111110111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_RESERVED_BIT_MASK       64'b1111111111111111111111111111111110000000000000001000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_INTERNAL_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_EXTERNAL_DECODE_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_ALIASED_FROM    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_ZERO_TIME_OMNI  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_HW_ACC_JTAG_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_HW_ACC_JTAG_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_HW_ACC_SBUS_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_HW_ACC_SBUS_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_HW_ACC_RAP_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_HW_ACC_RAP_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_NUM_FIELDS      2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_NP_FID    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_NP_SLC    30:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_NP_WIDTH  15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_NP_INT_SLC        14:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_NP_POSITION       16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_NP_FMASK  64'b0000000000000000000000000000000001111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_NP_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_NP_POR_VALUE      15'b000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_NP_FIELD_NAME     "vc0_fc_up_tmr_np"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_P_FID     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_P_SLC     14:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_P_WIDTH   15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_P_INT_SLC 14:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_P_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_P_FMASK   64'b0000000000000000000000000000000000000000000000000111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_P_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_P_POR_VALUE       15'b000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_P_FIELD_NAME      "vc0_fc_up_tmr_p"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_HW_ADDR 20'b11011100010001001110
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_ADDR    30'b000000011011100010001001110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_vco_fc_cntl_up_tmr1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_WIDTH   64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_DEPTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_INT_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_FIELD_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_vco_fc_cntl_up_tmr1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_LOW_ADDR_WIDTH  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_ADDR_RANGE      19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_READ_MASK       64'b0000000000000000000000000000000000000000000000000111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_READ_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_WRITE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_RMASK   64'b0000000000000000000000000000000000000000000000000111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_RESERVED_BIT_MASK       64'b1111111111111111111111111111111111111111111111111000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_INTERNAL_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_EXTERNAL_DECODE_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_ALIASED_FROM    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_ZERO_TIME_OMNI  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_HW_ACC_JTAG_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_HW_ACC_JTAG_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_HW_ACC_SBUS_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_HW_ACC_SBUS_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_HW_ACC_RAP_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_HW_ACC_RAP_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_NUM_FIELDS      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_VC0_FC_UP_TMR_CPL_FID   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_VC0_FC_UP_TMR_CPL_SLC   14:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_VC0_FC_UP_TMR_CPL_WIDTH 15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_VC0_FC_UP_TMR_CPL_INT_SLC       14:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_VC0_FC_UP_TMR_CPL_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_VC0_FC_UP_TMR_CPL_FMASK 64'b0000000000000000000000000000000000000000000000000111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_VC0_FC_UP_TMR_CPL_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_VC0_FC_UP_TMR_CPL_POR_VALUE     15'b000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_VC0_FC_UP_TMR_CPL_FIELD_NAME    "vc0_fc_up_tmr_cpl"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_HW_ADDR      20'b11011100010010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ADDR 30'b000000011011100010010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_acknak_latency"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_WIDTH        64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_DEPTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_INT_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_POSITION     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_FIELD_NAME   "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_acknak_latency"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_LOW_ADDR_WIDTH       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ADDR_RANGE   19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_READ_MASK    64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_READ_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_WRITE_MASK   64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_WRITE_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_SET_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_CLEAR_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TOGGLE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_RMASK        64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_RESERVED_BIT_MASK    64'b1111111111111111111111111111111111111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_POR_VALUE    64'b0000000000000000000000000000000000000000000000000000000000110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_INTERNAL_REG 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_EXTERNAL_DECODE_REG  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ALIASED_FROM 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ZERO_TIME_OMNI       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_HW_ACC_JTAG_RD       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_HW_ACC_JTAG_WR       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_HW_ACC_SBUS_RD       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_HW_ACC_SBUS_WR       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_HW_ACC_RAP_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_HW_ACC_RAP_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_NUM_FIELDS   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ACK_NAK_THR_FID      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ACK_NAK_THR_SLC      15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ACK_NAK_THR_WIDTH    16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ACK_NAK_THR_INT_SLC  15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ACK_NAK_THR_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ACK_NAK_THR_FMASK    64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ACK_NAK_THR_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ACK_NAK_THR_POR_VALUE        16'b0000000000110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ACK_NAK_THR_FIELD_NAME       "ack_nak_thr"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_HW_ADDR  20'b11011100010010000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ADDR     30'b000000011011100010010000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_acknak_latency_tmr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_WIDTH    64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_DEPTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_INT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_FIELD_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_acknak_latency_tmr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_LOW_ADDR_WIDTH   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ADDR_RANGE       19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_READ_MASK        64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_READ_ONLY_MASK   64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_WRITE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_WRITE_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_CLEAR_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_TOGGLE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_RMASK    64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_RESERVED_BIT_MASK        64'b1111111111111111111111111111111111111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_POR_VALUE        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_INTERNAL_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_EXTERNAL_DECODE_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ALIASED_FROM     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ZERO_TIME_OMNI   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_HW_ACC_JTAG_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_HW_ACC_JTAG_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_HW_ACC_SBUS_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_HW_ACC_SBUS_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_HW_ACC_RAP_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_HW_ACC_RAP_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_NUM_FIELDS       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ACK_NAK_TMR_FID  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ACK_NAK_TMR_SLC  15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ACK_NAK_TMR_WIDTH        16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ACK_NAK_TMR_INT_SLC      15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ACK_NAK_TMR_POSITION     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ACK_NAK_TMR_FMASK        64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ACK_NAK_TMR_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ACK_NAK_TMR_POR_VALUE    16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ACK_NAK_TMR_FIELD_NAME   "ack_nak_tmr"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_HW_ADDR    20'b11011100010010000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_ADDR       30'b000000011011100010010000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rplay_tmr_thhold"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_WIDTH      64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_DEPTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_INT_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_POSITION   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rplay_tmr_thhold"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_LOW_ADDR_WIDTH     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_ADDR_RANGE 19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_READ_MASK  64'b0000000000000000000000000000000000000000000011111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_READ_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_WRITE_MASK 64'b0000000000000000000000000000000000000000000011111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RMASK      64'b0000000000000000000000000000000000000000000011111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RESERVED_BIT_MASK  64'b1111111111111111111111111111111111111111111100000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_POR_VALUE  64'b0000000000000000000000000000000000000000000000000000000010010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_INTERNAL_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_EXTERNAL_DECODE_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_ALIASED_FROM       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_ZERO_TIME_OMNI     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_HW_ACC_JTAG_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_HW_ACC_JTAG_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_HW_ACC_SBUS_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_HW_ACC_SBUS_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_HW_ACC_RAP_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_HW_ACC_RAP_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_NUM_FIELDS 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RPLAY_TMR_THR_FID  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RPLAY_TMR_THR_SLC  19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RPLAY_TMR_THR_WIDTH        20
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RPLAY_TMR_THR_INT_SLC      19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RPLAY_TMR_THR_POSITION     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RPLAY_TMR_THR_FMASK        64'b0000000000000000000000000000000000000000000011111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RPLAY_TMR_THR_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RPLAY_TMR_THR_POR_VALUE    20'b00000000000010010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RPLAY_TMR_THR_FIELD_NAME   "rplay_tmr_thr"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_HW_ADDR   20'b11011100010010000011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_ADDR      30'b000000011011100010010000011000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rplay_tmr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_WIDTH     64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_DEPTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_INT_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_FIELD_NAME        "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rplay_tmr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_LOW_ADDR_WIDTH    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_ADDR_RANGE        19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_READ_MASK 64'b0000000000000000000000000000000000000000000011111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_READ_ONLY_MASK    64'b0000000000000000000000000000000000000000000011111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_WRITE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_WRITE_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_SET_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_CLEAR_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_TOGGLE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RMASK     64'b0000000000000000000000000000000000000000000011111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111100000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000010010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_INTERNAL_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_EXTERNAL_DECODE_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_ALIASED_FROM      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_ZERO_TIME_OMNI    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_HW_ACC_JTAG_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_HW_ACC_JTAG_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_HW_ACC_SBUS_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_HW_ACC_SBUS_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_HW_ACC_RAP_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_HW_ACC_RAP_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_NUM_FIELDS        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RPLAY_TMR_FID     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RPLAY_TMR_SLC     19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RPLAY_TMR_WIDTH   20
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RPLAY_TMR_INT_SLC 19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RPLAY_TMR_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RPLAY_TMR_FMASK   64'b0000000000000000000000000000000000000000000011111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RPLAY_TMR_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RPLAY_TMR_POR_VALUE       20'b00000000000010010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RPLAY_TMR_FIELD_NAME      "rplay_tmr"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_HW_ADDR      20'b11011100010010000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_ADDR 30'b000000011011100010010000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rplay_num_stat"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WIDTH        64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_DEPTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_INT_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_POSITION     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_FIELD_NAME   "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rplay_num_stat"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_LOW_ADDR_WIDTH       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_ADDR_RANGE   19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_READ_MASK    64'b0000000000000000000000000000000010000000000000000000000000000011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_READ_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WRITE_MASK   64'b0000000000000000000000000000000010000000000000000000000000000011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WRITE_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_SET_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_CLEAR_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_TOGGLE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RMASK        64'b0000000000000000000000000000000010000000000000000000000000000011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RESERVED_BIT_MASK    64'b1111111111111111111111111111111101111111111111111111111111111100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_POR_VALUE    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_INTERNAL_REG 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_EXTERNAL_DECODE_REG  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_ALIASED_FROM 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_ZERO_TIME_OMNI       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_HW_ACC_JTAG_RD       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_HW_ACC_JTAG_WR       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_HW_ACC_SBUS_RD       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_HW_ACC_SBUS_WR       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_HW_ACC_RAP_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_HW_ACC_RAP_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_NUM_FIELDS   2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WE_FID       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WE_SLC       31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WE_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WE_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WE_POSITION  31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WE_FMASK     64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WE_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WE_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WE_FIELD_NAME        "we"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RPLAY_NUM_CNTR_FID   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RPLAY_NUM_CNTR_SLC   1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RPLAY_NUM_CNTR_WIDTH 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RPLAY_NUM_CNTR_INT_SLC       1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RPLAY_NUM_CNTR_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RPLAY_NUM_CNTR_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RPLAY_NUM_CNTR_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RPLAY_NUM_CNTR_POR_VALUE     2'b00
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RPLAY_NUM_CNTR_FIELD_NAME    "rplay_num_cntr"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_HW_ADDR  20'b11011100010010000101
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_ADDR     30'b000000011011100010010000101000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_buff_max_addr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_WIDTH    64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_DEPTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_INT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_FIELD_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_buff_max_addr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_LOW_ADDR_WIDTH   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_ADDR_RANGE       19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_READ_MASK        64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_READ_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_WRITE_MASK       64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_WRITE_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_CLEAR_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_TOGGLE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RMASK    64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RESERVED_BIT_MASK        64'b1111111111111111111111111111111111111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_POR_VALUE        64'b0000000000000000000000000000000000000000000000000001010101111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_INTERNAL_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_EXTERNAL_DECODE_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_ALIASED_FROM     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_ZERO_TIME_OMNI   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_HW_ACC_JTAG_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_HW_ACC_JTAG_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_HW_ACC_SBUS_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_HW_ACC_SBUS_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_HW_ACC_RAP_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_HW_ACC_RAP_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_NUM_FIELDS       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RTRY_BUFF_MAX_ADDR_FID   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RTRY_BUFF_MAX_ADDR_SLC   15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RTRY_BUFF_MAX_ADDR_WIDTH 16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RTRY_BUFF_MAX_ADDR_INT_SLC       15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RTRY_BUFF_MAX_ADDR_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RTRY_BUFF_MAX_ADDR_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RTRY_BUFF_MAX_ADDR_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RTRY_BUFF_MAX_ADDR_POR_VALUE     16'b0001010101111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RTRY_BUFF_MAX_ADDR_FIELD_NAME    "rtry_buff_max_addr"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_HW_ADDR       20'b11011100010010000110
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_ADDR  30'b000000011011100010010000110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_fifo_ptr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_WIDTH 64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_DEPTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_INT_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_FIELD_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_fifo_ptr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_LOW_ADDR_WIDTH        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_ADDR_RANGE    19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_READ_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_READ_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_WRITE_MASK    64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_WRITE_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_SET_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_CLEAR_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_TOGGLE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RESERVED_BIT_MASK     64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_HW_LD_MASK    64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_POR_VALUE     64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_INTERNAL_REG  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_EXTERNAL_DECODE_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_ALIASED_FROM  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_ZERO_TIME_OMNI        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_HW_ACC_JTAG_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_HW_ACC_JTAG_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_HW_ACC_SBUS_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_HW_ACC_SBUS_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_HW_ACC_RAP_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_HW_ACC_RAP_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_NUM_FIELDS    2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_TLPTR_FID   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_TLPTR_SLC   31:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_TLPTR_WIDTH 16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_TLPTR_INT_SLC       15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_TLPTR_POSITION      16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_TLPTR_FMASK 64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_TLPTR_HW_LD_MASK    64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_TLPTR_POR_VALUE     16'b1111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_TLPTR_FIELD_NAME    "rtry_fifo_tlptr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_HDPTR_FID   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_HDPTR_SLC   15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_HDPTR_WIDTH 16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_HDPTR_INT_SLC       15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_HDPTR_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_HDPTR_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_HDPTR_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_HDPTR_POR_VALUE     16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_HDPTR_FIELD_NAME    "rtry_fifo_hdptr"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_HW_ADDR    20'b11011100010010000111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_ADDR       30'b000000011011100010010000111000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_fifo_rw_ptr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_WIDTH      64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_DEPTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_INT_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_POSITION   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_fifo_rw_ptr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_LOW_ADDR_WIDTH     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_ADDR_RANGE 19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_READ_MASK  64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_READ_ONLY_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RMASK      64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RESERVED_BIT_MASK  64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_POR_VALUE  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_INTERNAL_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_EXTERNAL_DECODE_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_ALIASED_FROM       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_ZERO_TIME_OMNI     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_HW_ACC_JTAG_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_HW_ACC_JTAG_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_HW_ACC_SBUS_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_HW_ACC_SBUS_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_HW_ACC_RAP_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_HW_ACC_RAP_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_NUM_FIELDS 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_WRPTR_FID        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_WRPTR_SLC        31:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_WRPTR_WIDTH      16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_WRPTR_INT_SLC    15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_WRPTR_POSITION   16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_WRPTR_FMASK      64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_WRPTR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_WRPTR_POR_VALUE  16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_WRPTR_FIELD_NAME "rtry_bffr_wrptr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_RDPTR_FID        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_RDPTR_SLC        15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_RDPTR_WIDTH      16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_RDPTR_INT_SLC    15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_RDPTR_POSITION   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_RDPTR_FMASK      64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_RDPTR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_RDPTR_POR_VALUE  16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_RDPTR_FIELD_NAME "rtry_bffr_rdptr"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_HW_ADDR      20'b11011100010010001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_ADDR 30'b000000011011100010010001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_fifo_crdt"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_WIDTH        64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_DEPTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_INT_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_POSITION     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_FIELD_NAME   "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_fifo_crdt"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_LOW_ADDR_WIDTH       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_ADDR_RANGE   19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_READ_MASK    64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_READ_ONLY_MASK       64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_WRITE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_WRITE_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_SET_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_CLEAR_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_TOGGLE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RMASK        64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RESERVED_BIT_MASK    64'b1111111111111111111111111111111111111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_POR_VALUE    64'b0000000000000000000000000000000000000000000000000001010110000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_INTERNAL_REG 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_EXTERNAL_DECODE_REG  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_ALIASED_FROM 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_ZERO_TIME_OMNI       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_HW_ACC_JTAG_RD       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_HW_ACC_JTAG_WR       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_HW_ACC_SBUS_RD       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_HW_ACC_SBUS_WR       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_HW_ACC_RAP_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_HW_ACC_RAP_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_NUM_FIELDS   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RTRY_FIFO_CRDT_FID   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RTRY_FIFO_CRDT_SLC   15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RTRY_FIFO_CRDT_WIDTH 16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RTRY_FIFO_CRDT_INT_SLC       15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RTRY_FIFO_CRDT_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RTRY_FIFO_CRDT_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RTRY_FIFO_CRDT_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RTRY_FIFO_CRDT_POR_VALUE     16'b0001010110000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RTRY_FIFO_CRDT_FIELD_NAME    "rtry_fifo_crdt"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_HW_ADDR    20'b11011100010010001001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ADDR       30'b000000011011100010010001001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_cntr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WIDTH      64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_DEPTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_INT_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_POSITION   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_cntr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_LOW_ADDR_WIDTH     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ADDR_RANGE 19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_READ_MASK  64'b0000000000000000000000000000000000001111111111110000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_READ_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WRITE_MASK 64'b0000000000000000000000000000000011001111111111110000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WRITE_ONLY_MASK    64'b0000000000000000000000000000000011000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_RMASK      64'b0000000000000000000000000000000011001111111111110000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_RESERVED_BIT_MASK  64'b1111111111111111111111111111111100110000000000001111000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_HW_LD_MASK 64'b0000000000000000000000000000000011001111111111110000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_POR_VALUE  64'b0000000000000000000000000000000000001111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_INTERNAL_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_EXTERNAL_DECODE_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ALIASED_FROM       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ZERO_TIME_OMNI     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_HW_ACC_JTAG_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_HW_ACC_JTAG_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_HW_ACC_SBUS_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_HW_ACC_SBUS_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_HW_ACC_RAP_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_HW_ACC_RAP_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NUM_FIELDS 4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WE_FID     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WE_SLC     31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WE_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WE_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WE_POSITION        31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WE_FMASK   64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WE_HW_LD_MASK      64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WE_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WE_FIELD_NAME      "we"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_WE_FID     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_WE_SLC     30:30
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_WE_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_WE_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_WE_POSITION        30
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_WE_FMASK   64'b0000000000000000000000000000000001000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_WE_HW_LD_MASK      64'b0000000000000000000000000000000001000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_WE_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_WE_FIELD_NAME      "ack_seq_we"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_CNTR_FID   2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_CNTR_SLC   27:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_CNTR_WIDTH 12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_CNTR_INT_SLC       11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_CNTR_POSITION      16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_CNTR_FMASK 64'b0000000000000000000000000000000000001111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_CNTR_HW_LD_MASK    64'b0000000000000000000000000000000000001111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_CNTR_POR_VALUE     12'b111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_CNTR_FIELD_NAME    "ack_seq_cntr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NXT_TX_SEQ_CNTR_FID        3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NXT_TX_SEQ_CNTR_SLC        11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NXT_TX_SEQ_CNTR_WIDTH      12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NXT_TX_SEQ_CNTR_INT_SLC    11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NXT_TX_SEQ_CNTR_POSITION   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NXT_TX_SEQ_CNTR_FMASK      64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NXT_TX_SEQ_CNTR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NXT_TX_SEQ_CNTR_POR_VALUE  12'b000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NXT_TX_SEQ_CNTR_FIELD_NAME "nxt_tx_seq_cntr"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_HW_ADDR     20'b11011100010010001010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_ADDR        30'b000000011011100010010001010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_NAME        "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ack_snd_seq_num"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_WIDTH       64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_DEPTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_INT_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_FIELD_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ack_snd_seq_num"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_LOW_ADDR_WIDTH      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_ADDR_RANGE  19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_READ_MASK   64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_READ_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_WRITE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SET_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_CLEAR_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_RMASK       64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_RESERVED_BIT_MASK   64'b1111111111111111111111111111111111111111111111111111000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_INTERNAL_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_EXTERNAL_DECODE_REG 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_ALIASED_FROM        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_ZERO_TIME_OMNI      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_HW_ACC_JTAG_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_HW_ACC_JTAG_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_HW_ACC_SBUS_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_HW_ACC_SBUS_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_HW_ACC_RAP_RD       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_HW_ACC_RAP_WR       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_NUM_FIELDS  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SEQ_NUM_FID 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SEQ_NUM_SLC 11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SEQ_NUM_WIDTH       12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SEQ_NUM_INT_SLC     11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SEQ_NUM_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SEQ_NUM_FMASK       64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SEQ_NUM_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SEQ_NUM_POR_VALUE   12'b111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SEQ_NUM_FIELD_NAME  "seq_num"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_HW_ADDR       20'b11011100010010001011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_ADDR  30'b000000011011100010010001011000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_cnt_fifo_max_addr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_WIDTH 64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_DEPTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_INT_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_FIELD_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_cnt_fifo_max_addr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_LOW_ADDR_WIDTH        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_ADDR_RANGE    19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_READ_MASK     64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_READ_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_WRITE_MASK    64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_WRITE_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SET_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_CLEAR_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_TOGGLE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_RMASK 64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_RESERVED_BIT_MASK     64'b1111111111111111111111111111111111111111111111111111000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_POR_VALUE     64'b0000000000000000000000000000000000000000000000000000000101010111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_INTERNAL_REG  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_EXTERNAL_DECODE_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_ALIASED_FROM  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_ZERO_TIME_OMNI        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_HW_ACC_JTAG_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_HW_ACC_JTAG_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_HW_ACC_SBUS_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_HW_ACC_SBUS_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_HW_ACC_RAP_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_HW_ACC_RAP_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_NUM_FIELDS    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_FID  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_SLC  11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_WIDTH        12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_INT_SLC      11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_POSITION     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_FMASK        64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_POR_VALUE    12'b000101010111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_FIELD_NAME   "seq_cnt_max_addr"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_HW_ADDR    20'b11011100010010001100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_ADDR       30'b000000011011100010010001100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_cnt_fifo_ptr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_WIDTH      64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_DEPTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_INT_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_POSITION   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_cnt_fifo_ptr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_LOW_ADDR_WIDTH     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_ADDR_RANGE 19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_READ_MASK  64'b0000000000000000000000000000000000001111111111110000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_READ_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_WRITE_MASK 64'b0000000000000000000000000000000000001111111111110000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_RMASK      64'b0000000000000000000000000000000000001111111111110000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_RESERVED_BIT_MASK  64'b1111111111111111111111111111111111110000000000001111000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_HW_LD_MASK 64'b0000000000000000000000000000000000001111111111110000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_POR_VALUE  64'b0000000000000000000000000000000000001111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_INTERNAL_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_EXTERNAL_DECODE_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_ALIASED_FROM       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_ZERO_TIME_OMNI     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_HW_ACC_JTAG_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_HW_ACC_JTAG_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_HW_ACC_SBUS_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_HW_ACC_SBUS_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_HW_ACC_RAP_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_HW_ACC_RAP_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_NUM_FIELDS 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_TLPTR_FID  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_TLPTR_SLC  27:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_TLPTR_WIDTH        12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_TLPTR_INT_SLC      11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_TLPTR_POSITION     16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_TLPTR_FMASK        64'b0000000000000000000000000000000000001111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_TLPTR_HW_LD_MASK   64'b0000000000000000000000000000000000001111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_TLPTR_POR_VALUE    12'b111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_TLPTR_FIELD_NAME   "seq_cnt_tlptr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_HDPTR_FID  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_HDPTR_SLC  11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_HDPTR_WIDTH        12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_HDPTR_INT_SLC      11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_HDPTR_POSITION     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_HDPTR_FMASK        64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_HDPTR_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_HDPTR_POR_VALUE    12'b000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_HDPTR_FIELD_NAME   "seq_cnt_hdptr"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_HW_ADDR      20'b11011100010010001101
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_ADDR 30'b000000011011100010010001101000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_cnt_rw_ptr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_WIDTH        64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_DEPTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_INT_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_POSITION     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_FIELD_NAME   "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_cnt_rw_ptr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_LOW_ADDR_WIDTH       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_ADDR_RANGE   19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_READ_MASK    64'b0000000000000000000000000000000000001111111111110000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_READ_ONLY_MASK       64'b0000000000000000000000000000000000001111111111110000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_WRITE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_WRITE_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SET_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_CLEAR_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_TOGGLE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_RMASK        64'b0000000000000000000000000000000000001111111111110000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_RESERVED_BIT_MASK    64'b1111111111111111111111111111111111110000000000001111000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_HW_LD_MASK   64'b0000000000000000000000000000000000001111111111110000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_POR_VALUE    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_INTERNAL_REG 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_EXTERNAL_DECODE_REG  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_ALIASED_FROM 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_ZERO_TIME_OMNI       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_HW_ACC_JTAG_RD       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_HW_ACC_JTAG_WR       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_HW_ACC_SBUS_RD       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_HW_ACC_SBUS_WR       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_HW_ACC_RAP_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_HW_ACC_RAP_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_NUM_FIELDS   2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_WRPTR_FID    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_WRPTR_SLC    27:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_WRPTR_WIDTH  12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_WRPTR_INT_SLC        11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_WRPTR_POSITION       16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_WRPTR_FMASK  64'b0000000000000000000000000000000000001111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_WRPTR_HW_LD_MASK     64'b0000000000000000000000000000000000001111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_WRPTR_POR_VALUE      12'b000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_WRPTR_FIELD_NAME     "seq_cnt_wrptr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_RDPTR_FID    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_RDPTR_SLC    11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_RDPTR_WIDTH  12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_RDPTR_INT_SLC        11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_RDPTR_POSITION       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_RDPTR_FMASK  64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_RDPTR_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_RDPTR_POR_VALUE      12'b000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_RDPTR_FIELD_NAME     "seq_cnt_rdptr"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_HW_ADDR 20'b11011100010010001110
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_ADDR    30'b000000011011100010010001110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_tst_cntl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_WIDTH   64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DEPTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_INT_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FIELD_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_tst_cntl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_LOW_ADDR_WIDTH  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_ADDR_RANGE      19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_READ_MASK       64'b0000000000000000000000000000000000000000000000000000000000001111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_READ_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_WRITE_MASK      64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_RMASK   64'b0000000000000000000000000000000000000000000000000000000000001111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_RESERVED_BIT_MASK       64'b1111111111111111111111111111111111111111111111111111111111110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000001111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_INTERNAL_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_EXTERNAL_DECODE_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_ALIASED_FROM    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_ZERO_TIME_OMNI  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_HW_ACC_JTAG_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_HW_ACC_JTAG_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_HW_ACC_SBUS_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_HW_ACC_SBUS_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_HW_ACC_RAP_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_HW_ACC_RAP_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_NUM_FIELDS      4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DIS_ACK_FID     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DIS_ACK_SLC     3:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DIS_ACK_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DIS_ACK_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DIS_ACK_POSITION        3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DIS_ACK_FMASK   64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DIS_ACK_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DIS_ACK_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DIS_ACK_FIELD_NAME      "dis_ack"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_NAK_FID   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_NAK_SLC   2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_NAK_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_NAK_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_NAK_POSITION      2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_NAK_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_NAK_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_NAK_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_NAK_FIELD_NAME    "force_nak"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_BAD_TLP_CRC_FID   2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_BAD_TLP_CRC_SLC   1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_BAD_TLP_CRC_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_BAD_TLP_CRC_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_BAD_TLP_CRC_POSITION      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_BAD_TLP_CRC_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_BAD_TLP_CRC_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_BAD_TLP_CRC_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_BAD_TLP_CRC_FIELD_NAME    "force_bad_tlp_crc"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_RTX_TLP_FID       3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_RTX_TLP_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_RTX_TLP_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_RTX_TLP_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_RTX_TLP_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_RTX_TLP_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_RTX_TLP_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_RTX_TLP_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_RTX_TLP_FIELD_NAME        "force_rtx_tlp"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_HW_ADDR       20'b11011100010010010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_ADDR  30'b000000011011100010010010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_addr_cntl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_WIDTH 64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DEPTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_INT_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIELD_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_addr_cntl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_LOW_ADDR_WIDTH        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_ADDR_RANGE    19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_READ_MASK     64'b0000000000000000000000000000000011110000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_READ_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_WRITE_MASK    64'b0000000000000000000000000000000000110000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_WRITE_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_SET_MASK      64'b0000000000000000000000000000000001000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_CLEAR_MASK    64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_TOGGLE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RMASK 64'b0000000000000000000000000000000011110000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RESERVED_BIT_MASK     64'b1111111111111111111111111111111100001111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_HW_LD_MASK    64'b0000000000000000000000000000000011000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_POR_VALUE     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_INTERNAL_REG  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_EXTERNAL_DECODE_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_ALIASED_FROM  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_ZERO_TIME_OMNI        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_HW_ACC_JTAG_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_HW_ACC_JTAG_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_HW_ACC_SBUS_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_HW_ACC_SBUS_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_HW_ACC_RAP_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_HW_ACC_RAP_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_NUM_FIELDS    5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DONE_FID      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DONE_SLC      31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DONE_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DONE_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DONE_POSITION 31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DONE_FMASK    64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DONE_HW_LD_MASK       64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DONE_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DONE_FIELD_NAME       "done"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_GO_BIT_FID    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_GO_BIT_SLC    30:30
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_GO_BIT_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_GO_BIT_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_GO_BIT_POSITION       30
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_GO_BIT_FMASK  64'b0000000000000000000000000000000001000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_GO_BIT_HW_LD_MASK     64'b0000000000000000000000000000000001000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_GO_BIT_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_GO_BIT_FIELD_NAME     "go_bit"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RD_WR_SEL_FID 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RD_WR_SEL_SLC 29:29
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RD_WR_SEL_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RD_WR_SEL_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RD_WR_SEL_POSITION    29
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RD_WR_SEL_FMASK       64'b0000000000000000000000000000000000100000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RD_WR_SEL_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RD_WR_SEL_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RD_WR_SEL_FIELD_NAME  "rd_wr_sel"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIFO_SEL_FID  3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIFO_SEL_SLC  28:28
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIFO_SEL_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIFO_SEL_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIFO_SEL_POSITION     28
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIFO_SEL_FMASK        64'b0000000000000000000000000000000000010000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIFO_SEL_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIFO_SEL_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIFO_SEL_FIELD_NAME   "fifo_sel"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_MEM_ADDR_FID  4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_MEM_ADDR_SLC  15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_MEM_ADDR_WIDTH        16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_MEM_ADDR_INT_SLC      15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_MEM_ADDR_POSITION     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_MEM_ADDR_FMASK        64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_MEM_ADDR_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_MEM_ADDR_POR_VALUE    16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_MEM_ADDR_FIELD_NAME   "mem_addr"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_HW_ADDR     20'b11011100010010010001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_ADDR        30'b000000011011100010010010001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_NAME        "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld0"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_WIDTH       64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_DEPTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_INT_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_FIELD_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld0"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_LOW_ADDR_WIDTH      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_ADDR_RANGE  19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_READ_MASK   64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_READ_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_WRITE_MASK  64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_SET_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_CLEAR_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_RMASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_RESERVED_BIT_MASK   64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_INTERNAL_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_EXTERNAL_DECODE_REG 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_ALIASED_FROM        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_ZERO_TIME_OMNI      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_HW_ACC_JTAG_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_HW_ACC_JTAG_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_HW_ACC_SBUS_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_HW_ACC_SBUS_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_HW_ACC_RAP_RD       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_HW_ACC_RAP_WR       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_NUM_FIELDS  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_MEM_RD_WR_DATA0_FID 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_MEM_RD_WR_DATA0_SLC 31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_MEM_RD_WR_DATA0_WIDTH       32
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_MEM_RD_WR_DATA0_INT_SLC     31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_MEM_RD_WR_DATA0_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_MEM_RD_WR_DATA0_FMASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_MEM_RD_WR_DATA0_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_MEM_RD_WR_DATA0_POR_VALUE   32'b00000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_MEM_RD_WR_DATA0_FIELD_NAME  "mem_rd_wr_data0"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_HW_ADDR     20'b11011100010010010010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_ADDR        30'b000000011011100010010010010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_NAME        "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_WIDTH       64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_DEPTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_INT_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_FIELD_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_LOW_ADDR_WIDTH      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_ADDR_RANGE  19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_READ_MASK   64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_READ_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_WRITE_MASK  64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_SET_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_CLEAR_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_RMASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_RESERVED_BIT_MASK   64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_INTERNAL_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_EXTERNAL_DECODE_REG 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_ALIASED_FROM        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_ZERO_TIME_OMNI      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_HW_ACC_JTAG_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_HW_ACC_JTAG_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_HW_ACC_SBUS_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_HW_ACC_SBUS_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_HW_ACC_RAP_RD       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_HW_ACC_RAP_WR       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_NUM_FIELDS  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_MEM_RD_WR_DATA1_FID 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_MEM_RD_WR_DATA1_SLC 31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_MEM_RD_WR_DATA1_WIDTH       32
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_MEM_RD_WR_DATA1_INT_SLC     31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_MEM_RD_WR_DATA1_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_MEM_RD_WR_DATA1_FMASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_MEM_RD_WR_DATA1_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_MEM_RD_WR_DATA1_POR_VALUE   32'b00000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_MEM_RD_WR_DATA1_FIELD_NAME  "mem_rd_wr_data1"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_HW_ADDR     20'b11011100010010010011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_ADDR        30'b000000011011100010010010011000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_NAME        "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_WIDTH       64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_DEPTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_INT_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_FIELD_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_LOW_ADDR_WIDTH      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_ADDR_RANGE  19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_READ_MASK   64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_READ_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_WRITE_MASK  64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_SET_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_CLEAR_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_RMASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_RESERVED_BIT_MASK   64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_INTERNAL_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_EXTERNAL_DECODE_REG 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_ALIASED_FROM        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_ZERO_TIME_OMNI      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_HW_ACC_JTAG_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_HW_ACC_JTAG_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_HW_ACC_SBUS_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_HW_ACC_SBUS_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_HW_ACC_RAP_RD       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_HW_ACC_RAP_WR       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_NUM_FIELDS  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_MEM_RD_WR_DATA2_FID 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_MEM_RD_WR_DATA2_SLC 31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_MEM_RD_WR_DATA2_WIDTH       32
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_MEM_RD_WR_DATA2_INT_SLC     31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_MEM_RD_WR_DATA2_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_MEM_RD_WR_DATA2_FMASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_MEM_RD_WR_DATA2_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_MEM_RD_WR_DATA2_POR_VALUE   32'b00000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_MEM_RD_WR_DATA2_FIELD_NAME  "mem_rd_wr_data2"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_HW_ADDR     20'b11011100010010010100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_ADDR        30'b000000011011100010010010100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_NAME        "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld3"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_WIDTH       64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_DEPTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_INT_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_FIELD_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld3"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_LOW_ADDR_WIDTH      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_ADDR_RANGE  19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_READ_MASK   64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_READ_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_WRITE_MASK  64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_SET_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_CLEAR_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_RMASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_RESERVED_BIT_MASK   64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_INTERNAL_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_EXTERNAL_DECODE_REG 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_ALIASED_FROM        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_ZERO_TIME_OMNI      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_HW_ACC_JTAG_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_HW_ACC_JTAG_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_HW_ACC_SBUS_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_HW_ACC_SBUS_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_HW_ACC_RAP_RD       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_HW_ACC_RAP_WR       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_NUM_FIELDS  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_MEM_RD_WR_DATA3_FID 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_MEM_RD_WR_DATA3_SLC 31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_MEM_RD_WR_DATA3_WIDTH       32
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_MEM_RD_WR_DATA3_INT_SLC     31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_MEM_RD_WR_DATA3_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_MEM_RD_WR_DATA3_FMASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_MEM_RD_WR_DATA3_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_MEM_RD_WR_DATA3_POR_VALUE   32'b00000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_MEM_RD_WR_DATA3_FIELD_NAME  "mem_rd_wr_data3"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_HW_ADDR     20'b11011100010010010101
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_ADDR        30'b000000011011100010010010101000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_NAME        "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld4"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_WIDTH       64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_DEPTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_INT_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_FIELD_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld4"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_LOW_ADDR_WIDTH      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_ADDR_RANGE  19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_READ_MASK   64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_READ_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_WRITE_MASK  64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_SET_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_CLEAR_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_RMASK       64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_RESERVED_BIT_MASK   64'b1111111111111111111111111111111111111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_INTERNAL_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_EXTERNAL_DECODE_REG 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_ALIASED_FROM        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_ZERO_TIME_OMNI      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_HW_ACC_JTAG_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_HW_ACC_JTAG_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_HW_ACC_SBUS_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_HW_ACC_SBUS_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_HW_ACC_RAP_RD       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_HW_ACC_RAP_WR       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_NUM_FIELDS  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_MEM_RD_WR_DATA4_FID 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_MEM_RD_WR_DATA4_SLC 15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_MEM_RD_WR_DATA4_WIDTH       16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_MEM_RD_WR_DATA4_INT_SLC     15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_MEM_RD_WR_DATA4_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_MEM_RD_WR_DATA4_FMASK       64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_MEM_RD_WR_DATA4_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_MEM_RD_WR_DATA4_POR_VALUE   16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_MEM_RD_WR_DATA4_FIELD_NAME  "mem_rd_wr_data4"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_HW_ADDR    20'b11011100010010011000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_ADDR       30'b000000011011100010010011000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_cnt"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_WIDTH      64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_DEPTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_INT_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_POSITION   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_cnt"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_LOW_ADDR_WIDTH     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_ADDR_RANGE 19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_READ_MASK  64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_READ_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_WRITE_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RMASK      64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RESERVED_BIT_MASK  64'b1111111111111111111111111111111111111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_POR_VALUE  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_INTERNAL_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_EXTERNAL_DECODE_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_ALIASED_FROM       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_ZERO_TIME_OMNI     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_HW_ACC_JTAG_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_HW_ACC_JTAG_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_HW_ACC_SBUS_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_HW_ACC_SBUS_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_HW_ACC_RAP_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_HW_ACC_RAP_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_NUM_FIELDS 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RTRY_DATA_CNT_FID  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RTRY_DATA_CNT_SLC  15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RTRY_DATA_CNT_WIDTH        16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RTRY_DATA_CNT_INT_SLC      15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RTRY_DATA_CNT_POSITION     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RTRY_DATA_CNT_FMASK        64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RTRY_DATA_CNT_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RTRY_DATA_CNT_POR_VALUE    16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RTRY_DATA_CNT_FIELD_NAME   "rtry_data_cnt"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_HW_ADDR        20'b11011100010010011001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_ADDR   30'b000000011011100010010011001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_NAME   "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_buff_cnt"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_WIDTH  64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_DEPTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_INT_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_POSITION       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_FIELD_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_buff_cnt"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_LOW_ADDR_WIDTH 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_ADDR_RANGE     19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_READ_MASK      64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_WRITE_MASK     64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_WRITE_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SET_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_CLEAR_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_TOGGLE_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_RMASK  64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_RESERVED_BIT_MASK      64'b1111111111111111111111111111111111111111111111111111000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_POR_VALUE      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_INTERNAL_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_EXTERNAL_DECODE_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_ALIASED_FROM   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_ZERO_TIME_OMNI 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_HW_ACC_JTAG_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_HW_ACC_JTAG_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_HW_ACC_SBUS_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_HW_ACC_SBUS_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_HW_ACC_RAP_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_HW_ACC_RAP_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_NUM_FIELDS     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SEQ_BUFF_CNT_FID       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SEQ_BUFF_CNT_SLC       11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SEQ_BUFF_CNT_WIDTH     12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SEQ_BUFF_CNT_INT_SLC   11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SEQ_BUFF_CNT_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SEQ_BUFF_CNT_FMASK     64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SEQ_BUFF_CNT_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SEQ_BUFF_CNT_POR_VALUE 12'b000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SEQ_BUFF_CNT_FIELD_NAME        "seq_buff_cnt"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_HW_ADDR        20'b11011100010010011010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_ADDR   30'b000000011011100010010011010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_NAME   "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_buff_btm"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_WIDTH  64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_DEPTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_INT_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_POSITION       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_FIELD_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_buff_btm"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_LOW_ADDR_WIDTH 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_ADDR_RANGE     19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_READ_MASK      64'b0000000000000000000000000000000001111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_WRITE_MASK     64'b0000000000000000000000000000000001111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_WRITE_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SET_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_CLEAR_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_TOGGLE_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_RMASK  64'b0000000000000000000000000000000001111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_RESERVED_BIT_MASK      64'b1111111111111111111111111111111110000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_HW_LD_MASK     64'b0000000000000000000000000000000001111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_POR_VALUE      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_INTERNAL_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_EXTERNAL_DECODE_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_ALIASED_FROM   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_ZERO_TIME_OMNI 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_HW_ACC_JTAG_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_HW_ACC_JTAG_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_HW_ACC_SBUS_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_HW_ACC_SBUS_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_HW_ACC_RAP_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_HW_ACC_RAP_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_NUM_FIELDS     4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBUF_BDATA_PAR_FID     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBUF_BDATA_PAR_SLC     30:30
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBUF_BDATA_PAR_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBUF_BDATA_PAR_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBUF_BDATA_PAR_POSITION        30
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBUF_BDATA_PAR_FMASK   64'b0000000000000000000000000000000001000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBUF_BDATA_PAR_HW_LD_MASK      64'b0000000000000000000000000000000001000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBUF_BDATA_PAR_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBUF_BDATA_PAR_FIELD_NAME      "sbuf_bdata_par"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_SEQ_NUM_FID     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_SEQ_NUM_SLC     29:18
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_SEQ_NUM_WIDTH   12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_SEQ_NUM_INT_SLC 11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_SEQ_NUM_POSITION        18
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_SEQ_NUM_FMASK   64'b0000000000000000000000000000000000111111111111000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_SEQ_NUM_HW_LD_MASK      64'b0000000000000000000000000000000000111111111111000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_SEQ_NUM_POR_VALUE       12'b000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_SEQ_NUM_FIELD_NAME      "sbdata_seq_num"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_RTRY_PTR_FID    2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_RTRY_PTR_SLC    17:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_RTRY_PTR_WIDTH  16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_RTRY_PTR_INT_SLC        15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_RTRY_PTR_POSITION       2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_RTRY_PTR_FMASK  64'b0000000000000000000000000000000000000000000000111111111111111100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_RTRY_PTR_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000111111111111111100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_RTRY_PTR_POR_VALUE      16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_RTRY_PTR_FIELD_NAME     "sbdata_rtry_ptr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_EOP_POS_FID     3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_EOP_POS_SLC     1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_EOP_POS_WIDTH   2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_EOP_POS_INT_SLC 1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_EOP_POS_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_EOP_POS_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_EOP_POS_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_EOP_POS_POR_VALUE       2'b00
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_EOP_POS_FIELD_NAME      "sbdata_eop_pos"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_HW_ADDR    20'b11011100010010100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_ADDR       30'b000000011011100010010100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_nxt_rcv_seq_cntr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_WIDTH      64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_DEPTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_INT_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_POSITION   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_nxt_rcv_seq_cntr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_LOW_ADDR_WIDTH     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_ADDR_RANGE 19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_READ_MASK  64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_READ_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_RMASK      64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_RESERVED_BIT_MASK  64'b1111111111111111111111111111111111111111111111111111000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_POR_VALUE  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_INTERNAL_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_EXTERNAL_DECODE_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_ALIASED_FROM       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_ZERO_TIME_OMNI     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_HW_ACC_JTAG_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_HW_ACC_JTAG_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_HW_ACC_SBUS_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_HW_ACC_SBUS_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_HW_ACC_RAP_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_HW_ACC_RAP_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NUM_FIELDS 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NXT_RX_SEQ_CNTR_FID        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NXT_RX_SEQ_CNTR_SLC        11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NXT_RX_SEQ_CNTR_WIDTH      12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NXT_RX_SEQ_CNTR_INT_SLC    11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NXT_RX_SEQ_CNTR_POSITION   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NXT_RX_SEQ_CNTR_FMASK      64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NXT_RX_SEQ_CNTR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NXT_RX_SEQ_CNTR_POR_VALUE  12'b000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NXT_RX_SEQ_CNTR_FIELD_NAME "nxt_rx_seq_cntr"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_HW_ADDR   20'b11011100010010100001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_ADDR      30'b000000011011100010010100001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_dllp_rcvd"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_WIDTH     64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_DEPTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_INT_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_FIELD_NAME        "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_dllp_rcvd"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_LOW_ADDR_WIDTH    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_ADDR_RANGE        19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_READ_ONLY_MASK    64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_WRITE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_WRITE_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_SET_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_CLEAR_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_TOGGLE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_RMASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_INTERNAL_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_EXTERNAL_DECODE_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_ALIASED_FROM      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_ZERO_TIME_OMNI    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_HW_ACC_JTAG_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_HW_ACC_JTAG_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_HW_ACC_SBUS_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_HW_ACC_SBUS_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_HW_ACC_RAP_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_HW_ACC_RAP_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_NUM_FIELDS        4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE3_FID 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE3_SLC 31:24
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE3_WIDTH       8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE3_INT_SLC     7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE3_POSITION    24
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE3_FMASK       64'b0000000000000000000000000000000011111111000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE3_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE3_POR_VALUE   8'b00000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE3_FIELD_NAME  "byte3"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE2_FID 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE2_SLC 23:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE2_WIDTH       8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE2_INT_SLC     7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE2_POSITION    16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE2_FMASK       64'b0000000000000000000000000000000000000000111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE2_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE2_POR_VALUE   8'b00000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE2_FIELD_NAME  "byte2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE1_FID 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE1_SLC 15:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE1_WIDTH       8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE1_INT_SLC     7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE1_POSITION    8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE1_FMASK       64'b0000000000000000000000000000000000000000000000001111111100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE1_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE1_POR_VALUE   8'b00000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE1_FIELD_NAME  "byte1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE0_FID 3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE0_SLC 7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE0_WIDTH       8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE0_INT_SLC     7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE0_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE0_FMASK       64'b0000000000000000000000000000000000000000000000000000000011111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE0_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE0_POR_VALUE   8'b00000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE0_FIELD_NAME  "byte0"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_HW_ADDR   20'b11011100010010100010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_ADDR      30'b000000011011100010010100010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_link_test_cntl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_WIDTH     64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_DEPTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_INT_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FIELD_NAME        "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_link_test_cntl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_LOW_ADDR_WIDTH    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_ADDR_RANGE        19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_READ_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_WRITE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_WRITE_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_SET_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_CLEAR_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_TOGGLE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_RMASK     64'b0000000000000000000000000000000000000000000000000000000000000011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_INTERNAL_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_EXTERNAL_DECODE_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_ALIASED_FROM      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_ZERO_TIME_OMNI    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_HW_ACC_JTAG_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_HW_ACC_JTAG_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_HW_ACC_SBUS_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_HW_ACC_SBUS_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_HW_ACC_RAP_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_HW_ACC_RAP_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_NUM_FIELDS        2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_SEND_INIT_FC_DLLP_FID       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_SEND_INIT_FC_DLLP_SLC       1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_SEND_INIT_FC_DLLP_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_SEND_INIT_FC_DLLP_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_SEND_INIT_FC_DLLP_POSITION  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_SEND_INIT_FC_DLLP_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_SEND_INIT_FC_DLLP_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_SEND_INIT_FC_DLLP_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_SEND_INIT_FC_DLLP_FIELD_NAME        "force_send_init_fc_dllp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_PAR_ERR_DLLP_FID    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_PAR_ERR_DLLP_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_PAR_ERR_DLLP_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_PAR_ERR_DLLP_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_PAR_ERR_DLLP_POSITION       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_PAR_ERR_DLLP_FMASK  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_PAR_ERR_DLLP_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_PAR_ERR_DLLP_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_PAR_ERR_DLLP_FIELD_NAME     "force_par_err_dllp"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_HW_ADDR    20'b11011100010011000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_ADDR       30'b000000011011100010011000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_cnfg"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_WIDTH      64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_DEPTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_INT_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_POSITION   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_cnfg"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_LOW_ADDR_WIDTH     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_ADDR_RANGE 19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_READ_MASK  64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_READ_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_RMASK      64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_RESERVED_BIT_MASK  64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_HW_LD_MASK 64'b0000000000000000000000000000000000010000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_POR_VALUE  64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_INTERNAL_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_EXTERNAL_DECODE_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_ALIASED_FROM       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_ZERO_TIME_OMNI     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_HW_ACC_JTAG_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_HW_ACC_JTAG_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_HW_ACC_SBUS_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_HW_ACC_SBUS_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_HW_ACC_RAP_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_HW_ACC_RAP_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_NUM_FIELDS 13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_PHY_TST_EN_FID     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_PHY_TST_EN_SLC     31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_PHY_TST_EN_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_PHY_TST_EN_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_PHY_TST_EN_POSITION        31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_PHY_TST_EN_FMASK   64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_PHY_TST_EN_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_PHY_TST_EN_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_PHY_TST_EN_FIELD_NAME      "phy_tst_en"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FAST_SIM_FID       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FAST_SIM_SLC       30:30
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FAST_SIM_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FAST_SIM_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FAST_SIM_POSITION  30
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FAST_SIM_FMASK     64'b0000000000000000000000000000000001000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FAST_SIM_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FAST_SIM_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FAST_SIM_FIELD_NAME        "fast_sim"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_DIS_SCRAM_FID 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_DIS_SCRAM_SLC 29:29
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_DIS_SCRAM_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_DIS_SCRAM_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_DIS_SCRAM_POSITION    29
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_DIS_SCRAM_FMASK       64'b0000000000000000000000000000000000100000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_DIS_SCRAM_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_DIS_SCRAM_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_DIS_SCRAM_FIELD_NAME  "frce_dis_scram"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_EXTEN_SYNC_FID        3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_EXTEN_SYNC_SLC        28:28
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_EXTEN_SYNC_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_EXTEN_SYNC_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_EXTEN_SYNC_POSITION   28
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_EXTEN_SYNC_FMASK      64'b0000000000000000000000000000000000010000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_EXTEN_SYNC_HW_LD_MASK 64'b0000000000000000000000000000000000010000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_EXTEN_SYNC_POR_VALUE  1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_EXTEN_SYNC_FIELD_NAME "frce_exten_sync"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL2_FID   4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL2_SLC   27:12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL2_WIDTH 16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL2_INT_SLC       15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL2_POSITION      12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL2_FMASK 64'b0000000000000000000000000000000000001111111111111111000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL2_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL2_POR_VALUE     16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL2_FIELD_NAME    "unused_cntl2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_EIDLE_POST_EN_FID       5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_EIDLE_POST_EN_SLC       11:11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_EIDLE_POST_EN_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_EIDLE_POST_EN_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_EIDLE_POST_EN_POSITION  11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_EIDLE_POST_EN_FMASK     64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_EIDLE_POST_EN_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_EIDLE_POST_EN_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_EIDLE_POST_EN_FIELD_NAME        "tx_eidle_post_en"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_POST_VAL_FID 6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_POST_VAL_SLC 10:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_POST_VAL_WIDTH       3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_POST_VAL_INT_SLC     2:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_POST_VAL_POSITION    8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_POST_VAL_FMASK       64'b0000000000000000000000000000000000000000000000000000011100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_POST_VAL_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_POST_VAL_POR_VALUE   3'b000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_POST_VAL_FIELD_NAME  "tx_os_post_val"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_BYTE_SEL_FID 7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_BYTE_SEL_SLC 7:7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_BYTE_SEL_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_BYTE_SEL_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_BYTE_SEL_POSITION    7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_BYTE_SEL_FMASK       64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_BYTE_SEL_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_BYTE_SEL_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_BYTE_SEL_FIELD_NAME  "tx_os_byte_sel"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_PREAM_VAL_FID        8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_PREAM_VAL_SLC        6:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_PREAM_VAL_WIDTH      3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_PREAM_VAL_INT_SLC    2:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_PREAM_VAL_POSITION   4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_PREAM_VAL_FMASK      64'b0000000000000000000000000000000000000000000000000000000001110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_PREAM_VAL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_PREAM_VAL_POR_VALUE  3'b001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_PREAM_VAL_FIELD_NAME "tx_os_pream_val"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_BYP_MODE_FID       9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_BYP_MODE_SLC       3:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_BYP_MODE_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_BYP_MODE_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_BYP_MODE_POSITION  3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_BYP_MODE_FMASK     64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_BYP_MODE_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_BYP_MODE_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_BYP_MODE_FIELD_NAME        "tx_rdet_byp_mode"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_SAFE_MODE_FID      10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_SAFE_MODE_SLC      2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_SAFE_MODE_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_SAFE_MODE_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_SAFE_MODE_POSITION 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_SAFE_MODE_FMASK    64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_SAFE_MODE_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_SAFE_MODE_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_SAFE_MODE_FIELD_NAME       "tx_rdet_safe_mode"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL1_FID   11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL1_SLC   1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL1_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL1_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL1_POSITION      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL1_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL1_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL1_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL1_FIELD_NAME    "unused_cntl1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_PAR_ERR_FID     12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_PAR_ERR_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_PAR_ERR_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_PAR_ERR_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_PAR_ERR_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_PAR_ERR_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_PAR_ERR_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_PAR_ERR_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_PAR_ERR_FIELD_NAME      "tx_par_err"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_HW_ADDR    20'b11011100010011000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_ADDR       30'b000000011011100010011000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_stat"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_WIDTH      64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_DEPTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_INT_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_POSITION   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_stat"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_LOW_ADDR_WIDTH     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_ADDR_RANGE 19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_READ_MASK  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_READ_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RMASK      64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RESERVED_BIT_MASK  64'b1111111111111111111111111111111111111111111111111111111111111110
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_POR_VALUE  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_INTERNAL_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_EXTERNAL_DECODE_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_ALIASED_FROM       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_ZERO_TIME_OMNI     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_HW_ACC_JTAG_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_HW_ACC_JTAG_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_HW_ACC_SBUS_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_HW_ACC_SBUS_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_HW_ACC_RAP_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_HW_ACC_RAP_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_NUM_FIELDS 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RSVDP_FID  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RSVDP_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RSVDP_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RSVDP_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RSVDP_POSITION     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RSVDP_FMASK        64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RSVDP_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RSVDP_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RSVDP_FIELD_NAME   "rsvdp"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_HW_ADDR 20'b11011100010011000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_ADDR    30'b000000011011100010011000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_err_int"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_WIDTH   64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_DEPTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_FIELD_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_err_int"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_LOW_ADDR_WIDTH  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_ADDR_RANGE      19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_READ_MASK       64'b0000000000000000000000000000000010000000000000000011111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_READ_ONLY_MASK  64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_WRITE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000011111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_RMASK   64'b0000000000000000000000000000000010000000000000000011111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_RESERVED_BIT_MASK       64'b1111111111111111111111111111111101111111111111111100000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000011111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INTERNAL_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_EXTERNAL_DECODE_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_ALIASED_FROM    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_ZERO_TIME_OMNI  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_HW_ACC_JTAG_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_HW_ACC_JTAG_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_HW_ACC_SBUS_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_HW_ACC_SBUS_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_HW_ACC_RAP_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_HW_ACC_RAP_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_NUM_FIELDS      15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_PHY_LAYER_ERR_FID   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_PHY_LAYER_ERR_SLC   31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_PHY_LAYER_ERR_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_PHY_LAYER_ERR_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_PHY_LAYER_ERR_POSITION      31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_PHY_LAYER_ERR_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_PHY_LAYER_ERR_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_PHY_LAYER_ERR_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_PHY_LAYER_ERR_FIELD_NAME    "int_phy_layer_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_NON_CONS_ES_ERR_FID 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_NON_CONS_ES_ERR_SLC 13:13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_NON_CONS_ES_ERR_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_NON_CONS_ES_ERR_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_NON_CONS_ES_ERR_POSITION    13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_NON_CONS_ES_ERR_FMASK       64'b0000000000000000000000000000000000000000000000000010000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_NON_CONS_ES_ERR_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000010000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_NON_CONS_ES_ERR_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_NON_CONS_ES_ERR_FIELD_NAME  "int_non_cons_es_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ENDS_SYM_TM_ERR_FID 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ENDS_SYM_TM_ERR_SLC 12:12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ENDS_SYM_TM_ERR_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ENDS_SYM_TM_ERR_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ENDS_SYM_TM_ERR_POSITION    12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ENDS_SYM_TM_ERR_FMASK       64'b0000000000000000000000000000000000000000000000000001000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ENDS_SYM_TM_ERR_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000001000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ENDS_SYM_TM_ERR_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ENDS_SYM_TM_ERR_FIELD_NAME  "int_ends_sym_tm_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_KCHAR_DLLP_ERR_FID  3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_KCHAR_DLLP_ERR_SLC  11:11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_KCHAR_DLLP_ERR_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_KCHAR_DLLP_ERR_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_KCHAR_DLLP_ERR_POSITION     11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_KCHAR_DLLP_ERR_FMASK        64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_KCHAR_DLLP_ERR_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_KCHAR_DLLP_ERR_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_KCHAR_DLLP_ERR_FIELD_NAME   "int_kchar_dllp_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_END_POS_ERR_FID 4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_END_POS_ERR_SLC 10:10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_END_POS_ERR_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_END_POS_ERR_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_END_POS_ERR_POSITION    10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_END_POS_ERR_FMASK       64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_END_POS_ERR_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_END_POS_ERR_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_END_POS_ERR_FIELD_NAME  "int_ill_end_pos_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_LNK_ERR_FID 5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_LNK_ERR_SLC 9:9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_LNK_ERR_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_LNK_ERR_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_LNK_ERR_POSITION    9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_LNK_ERR_FMASK       64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_LNK_ERR_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_LNK_ERR_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_LNK_ERR_FIELD_NAME  "int_lnk_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_TRN_ERR_FID 6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_TRN_ERR_SLC 8:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_TRN_ERR_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_TRN_ERR_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_TRN_ERR_POSITION    8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_TRN_ERR_FMASK       64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_TRN_ERR_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_TRN_ERR_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_TRN_ERR_FIELD_NAME  "int_trn_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_EDB_DET_FID 7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_EDB_DET_SLC 7:7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_EDB_DET_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_EDB_DET_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_EDB_DET_POSITION    7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_EDB_DET_FMASK       64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_EDB_DET_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_EDB_DET_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_EDB_DET_FIELD_NAME  "int_edb_det"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SDP_END_FID 8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SDP_END_SLC 6:6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SDP_END_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SDP_END_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SDP_END_POSITION    6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SDP_END_FMASK       64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SDP_END_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SDP_END_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SDP_END_FIELD_NAME  "int_sdp_end"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_STP_END_EDB_FID     9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_STP_END_EDB_SLC     5:5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_STP_END_EDB_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_STP_END_EDB_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_STP_END_EDB_POSITION        5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_STP_END_EDB_FMASK   64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_STP_END_EDB_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_STP_END_EDB_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_STP_END_EDB_FIELD_NAME      "int_stp_end_edb"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_PAD_POS_FID     10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_PAD_POS_SLC     4:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_PAD_POS_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_PAD_POS_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_PAD_POS_POSITION        4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_PAD_POS_FMASK   64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_PAD_POS_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_PAD_POS_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_PAD_POS_FIELD_NAME      "int_ill_pad_pos"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_SDP_FID       11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_SDP_SLC       3:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_SDP_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_SDP_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_SDP_POSITION  3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_SDP_FMASK     64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_SDP_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_SDP_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_SDP_FIELD_NAME        "int_multi_sdp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_STP_FID       12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_STP_SLC       2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_STP_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_STP_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_STP_POSITION  2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_STP_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_STP_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_STP_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_STP_FIELD_NAME        "int_multi_stp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_SDP_POS_FID     13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_SDP_POS_SLC     1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_SDP_POS_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_SDP_POS_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_SDP_POS_POSITION        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_SDP_POS_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_SDP_POS_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_SDP_POS_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_SDP_POS_FIELD_NAME      "int_ill_sdp_pos"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_STP_POS_FID     14
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_STP_POS_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_STP_POS_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_STP_POS_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_STP_POS_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_STP_POS_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_STP_POS_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_STP_POS_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_STP_POS_FIELD_NAME      "int_ill_stp_pos"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_HW_ADDR 20'b11011100010011000011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_ADDR    30'b000000011011100010011000011000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_err_tst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_WIDTH   64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_DEPTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_INT_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_FIELD_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_err_tst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_LOW_ADDR_WIDTH  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_ADDR_RANGE      19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_READ_MASK       64'b0000000000000000000000000000000000000000000000000011111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_READ_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_WRITE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_SET_MASK        64'b0000000000000000000000000000000000000000000000000011111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_RMASK   64'b0000000000000000000000000000000000000000000000000011111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_RESERVED_BIT_MASK       64'b1111111111111111111111111111111111111111111111111100000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000011111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_INTERNAL_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_EXTERNAL_DECODE_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_ALIASED_FROM    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_ZERO_TIME_OMNI  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_HW_ACC_JTAG_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_HW_ACC_JTAG_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_HW_ACC_SBUS_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_HW_ACC_SBUS_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_HW_ACC_RAP_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_HW_ACC_RAP_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_NUM_FIELDS      14
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_NON_CONS_ES_ERR_FID 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_NON_CONS_ES_ERR_SLC 13:13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_NON_CONS_ES_ERR_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_NON_CONS_ES_ERR_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_NON_CONS_ES_ERR_POSITION    13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_NON_CONS_ES_ERR_FMASK       64'b0000000000000000000000000000000000000000000000000010000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_NON_CONS_ES_ERR_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000010000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_NON_CONS_ES_ERR_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_NON_CONS_ES_ERR_FIELD_NAME  "tst_non_cons_es_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ENDS_SYM_TM_ERR_FID 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ENDS_SYM_TM_ERR_SLC 12:12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ENDS_SYM_TM_ERR_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ENDS_SYM_TM_ERR_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ENDS_SYM_TM_ERR_POSITION    12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ENDS_SYM_TM_ERR_FMASK       64'b0000000000000000000000000000000000000000000000000001000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ENDS_SYM_TM_ERR_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000001000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ENDS_SYM_TM_ERR_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ENDS_SYM_TM_ERR_FIELD_NAME  "tst_ends_sym_tm_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_KCHAR_DLLP_ERR_FID  2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_KCHAR_DLLP_ERR_SLC  11:11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_KCHAR_DLLP_ERR_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_KCHAR_DLLP_ERR_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_KCHAR_DLLP_ERR_POSITION     11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_KCHAR_DLLP_ERR_FMASK        64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_KCHAR_DLLP_ERR_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_KCHAR_DLLP_ERR_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_KCHAR_DLLP_ERR_FIELD_NAME   "tst_kchar_dllp_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_END_POS_ERR_FID 3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_END_POS_ERR_SLC 10:10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_END_POS_ERR_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_END_POS_ERR_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_END_POS_ERR_POSITION    10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_END_POS_ERR_FMASK       64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_END_POS_ERR_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_END_POS_ERR_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_END_POS_ERR_FIELD_NAME  "tst_ill_end_pos_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_LNK_ERR_FID 4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_LNK_ERR_SLC 9:9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_LNK_ERR_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_LNK_ERR_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_LNK_ERR_POSITION    9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_LNK_ERR_FMASK       64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_LNK_ERR_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_LNK_ERR_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_LNK_ERR_FIELD_NAME  "tst_lnk_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_TRN_ERR_FID 5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_TRN_ERR_SLC 8:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_TRN_ERR_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_TRN_ERR_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_TRN_ERR_POSITION    8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_TRN_ERR_FMASK       64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_TRN_ERR_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_TRN_ERR_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_TRN_ERR_FIELD_NAME  "tst_trn_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_EDB_DET_FID 6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_EDB_DET_SLC 7:7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_EDB_DET_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_EDB_DET_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_EDB_DET_POSITION    7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_EDB_DET_FMASK       64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_EDB_DET_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_EDB_DET_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_EDB_DET_FIELD_NAME  "tst_edb_det"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_SDP_END_FID 7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_SDP_END_SLC 6:6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_SDP_END_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_SDP_END_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_SDP_END_POSITION    6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_SDP_END_FMASK       64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_SDP_END_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_SDP_END_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_SDP_END_FIELD_NAME  "tst_sdp_end"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_STP_END_EDB_FID     8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_STP_END_EDB_SLC     5:5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_STP_END_EDB_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_STP_END_EDB_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_STP_END_EDB_POSITION        5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_STP_END_EDB_FMASK   64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_STP_END_EDB_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_STP_END_EDB_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_STP_END_EDB_FIELD_NAME      "tst_stp_end_edb"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_PAD_POS_FID     9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_PAD_POS_SLC     4:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_PAD_POS_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_PAD_POS_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_PAD_POS_POSITION        4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_PAD_POS_FMASK   64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_PAD_POS_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_PAD_POS_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_PAD_POS_FIELD_NAME      "tst_ill_pad_pos"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_SDP_FID       10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_SDP_SLC       3:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_SDP_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_SDP_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_SDP_POSITION  3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_SDP_FMASK     64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_SDP_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_SDP_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_SDP_FIELD_NAME        "tst_multi_sdp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_STP_FID       11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_STP_SLC       2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_STP_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_STP_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_STP_POSITION  2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_STP_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_STP_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_STP_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_STP_FIELD_NAME        "tst_multi_stp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_SDP_POS_FID     12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_SDP_POS_SLC     1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_SDP_POS_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_SDP_POS_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_SDP_POS_POSITION        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_SDP_POS_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_SDP_POS_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_SDP_POS_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_SDP_POS_FIELD_NAME      "tst_ill_sdp_pos"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_STP_POS_FID     13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_STP_POS_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_STP_POS_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_STP_POS_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_STP_POS_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_STP_POS_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_STP_POS_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_STP_POS_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_STP_POS_FIELD_NAME      "tst_ill_stp_pos"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_HW_ADDR 20'b11011100010011000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_ADDR    30'b000000011011100010011000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_err_msk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_WIDTH   64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_DEPTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_INT_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_FIELD_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_err_msk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_LOW_ADDR_WIDTH  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_ADDR_RANGE      19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_READ_MASK       64'b0000000000000000000000000000000010000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_READ_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_WRITE_MASK      64'b0000000000000000000000000000000010000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_RMASK   64'b0000000000000000000000000000000010000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_RESERVED_BIT_MASK       64'b1111111111111111111111111111111101111111111111111111000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_INTERNAL_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_EXTERNAL_DECODE_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_ALIASED_FROM    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_ZERO_TIME_OMNI  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_HW_ACC_JTAG_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_HW_ACC_JTAG_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_HW_ACC_SBUS_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_HW_ACC_SBUS_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_HW_ACC_RAP_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_HW_ACC_RAP_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_NUM_FIELDS      13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_PHY_LAYER_ERR_FID   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_PHY_LAYER_ERR_SLC   31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_PHY_LAYER_ERR_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_PHY_LAYER_ERR_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_PHY_LAYER_ERR_POSITION      31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_PHY_LAYER_ERR_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_PHY_LAYER_ERR_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_PHY_LAYER_ERR_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_PHY_LAYER_ERR_FIELD_NAME    "msk_phy_layer_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_KCHAR_DLLP_ERR_FID  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_KCHAR_DLLP_ERR_SLC  11:11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_KCHAR_DLLP_ERR_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_KCHAR_DLLP_ERR_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_KCHAR_DLLP_ERR_POSITION     11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_KCHAR_DLLP_ERR_FMASK        64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_KCHAR_DLLP_ERR_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_KCHAR_DLLP_ERR_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_KCHAR_DLLP_ERR_FIELD_NAME   "msk_kchar_dllp_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_END_POS_ERR_FID 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_END_POS_ERR_SLC 10:10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_END_POS_ERR_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_END_POS_ERR_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_END_POS_ERR_POSITION    10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_END_POS_ERR_FMASK       64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_END_POS_ERR_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_END_POS_ERR_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_END_POS_ERR_FIELD_NAME  "msk_ill_end_pos_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_LNK_ERR_FID 3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_LNK_ERR_SLC 9:9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_LNK_ERR_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_LNK_ERR_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_LNK_ERR_POSITION    9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_LNK_ERR_FMASK       64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_LNK_ERR_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_LNK_ERR_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_LNK_ERR_FIELD_NAME  "msk_lnk_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_TRN_ERR_FID 4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_TRN_ERR_SLC 8:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_TRN_ERR_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_TRN_ERR_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_TRN_ERR_POSITION    8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_TRN_ERR_FMASK       64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_TRN_ERR_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_TRN_ERR_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_TRN_ERR_FIELD_NAME  "msk_trn_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_EDB_DET_FID 5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_EDB_DET_SLC 7:7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_EDB_DET_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_EDB_DET_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_EDB_DET_POSITION    7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_EDB_DET_FMASK       64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_EDB_DET_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_EDB_DET_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_EDB_DET_FIELD_NAME  "msk_edb_det"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_SDP_END_FID 6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_SDP_END_SLC 6:6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_SDP_END_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_SDP_END_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_SDP_END_POSITION    6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_SDP_END_FMASK       64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_SDP_END_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_SDP_END_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_SDP_END_FIELD_NAME  "msk_sdp_end"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_STP_END_EDB_FID     7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_STP_END_EDB_SLC     5:5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_STP_END_EDB_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_STP_END_EDB_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_STP_END_EDB_POSITION        5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_STP_END_EDB_FMASK   64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_STP_END_EDB_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_STP_END_EDB_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_STP_END_EDB_FIELD_NAME      "msk_stp_end_edb"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_PAD_POS_FID     8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_PAD_POS_SLC     4:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_PAD_POS_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_PAD_POS_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_PAD_POS_POSITION        4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_PAD_POS_FMASK   64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_PAD_POS_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_PAD_POS_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_PAD_POS_FIELD_NAME      "msk_ill_pad_pos"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_SDP_FID       9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_SDP_SLC       3:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_SDP_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_SDP_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_SDP_POSITION  3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_SDP_FMASK     64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_SDP_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_SDP_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_SDP_FIELD_NAME        "msk_multi_sdp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_STP_FID       10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_STP_SLC       2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_STP_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_STP_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_STP_POSITION  2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_STP_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_STP_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_STP_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_STP_FIELD_NAME        "msk_multi_stp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_SDP_POS_FID     11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_SDP_POS_SLC     1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_SDP_POS_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_SDP_POS_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_SDP_POS_POSITION        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_SDP_POS_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_SDP_POS_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_SDP_POS_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_SDP_POS_FIELD_NAME      "msk_ill_sdp_pos"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_STP_POS_FID     12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_STP_POS_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_STP_POS_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_STP_POS_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_STP_POS_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_STP_POS_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_STP_POS_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_STP_POS_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_STP_POS_FIELD_NAME      "msk_ill_stp_pos"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_HW_ADDR 20'b11011100010011010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_ADDR    30'b000000011011100010011010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_cnfg"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WIDTH   64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_DEPTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_INT_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_FIELD_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_cnfg"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_LOW_ADDR_WIDTH  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_ADDR_RANGE      19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_READ_MASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_READ_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WRITE_MASK      64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RMASK   64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RESERVED_BIT_MASK       64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_INTERNAL_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_EXTERNAL_DECODE_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_ALIASED_FROM    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_ZERO_TIME_OMNI  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_HW_ACC_JTAG_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_HW_ACC_JTAG_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_HW_ACC_SBUS_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_HW_ACC_SBUS_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_HW_ACC_RAP_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_HW_ACC_RAP_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_NUM_FIELDS      4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RX_PHY_TST_FID  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RX_PHY_TST_SLC  31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RX_PHY_TST_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RX_PHY_TST_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RX_PHY_TST_POSITION     31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RX_PHY_TST_FMASK        64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RX_PHY_TST_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RX_PHY_TST_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RX_PHY_TST_FIELD_NAME   "rx_phy_tst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_UNUSED_CONTROL_FID      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_UNUSED_CONTROL_SLC      30:18
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_UNUSED_CONTROL_WIDTH    13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_UNUSED_CONTROL_INT_SLC  12:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_UNUSED_CONTROL_POSITION 18
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_UNUSED_CONTROL_FMASK    64'b0000000000000000000000000000000001111111111111000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_UNUSED_CONTROL_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_UNUSED_CONTROL_POR_VALUE        13'b0000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_UNUSED_CONTROL_FIELD_NAME       "unused_control"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WM_SEL_FIFO_FID 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WM_SEL_FIFO_SLC 17:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WM_SEL_FIFO_WIDTH       2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WM_SEL_FIFO_INT_SLC     1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WM_SEL_FIFO_POSITION    16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WM_SEL_FIFO_FMASK       64'b0000000000000000000000000000000000000000000000110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WM_SEL_FIFO_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WM_SEL_FIFO_POR_VALUE   2'b00
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WM_SEL_FIFO_FIELD_NAME  "wm_sel_fifo"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RST_RCV_LANE_FID        3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RST_RCV_LANE_SLC        15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RST_RCV_LANE_WIDTH      16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RST_RCV_LANE_INT_SLC    15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RST_RCV_LANE_POSITION   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RST_RCV_LANE_FMASK      64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RST_RCV_LANE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RST_RCV_LANE_POR_VALUE  16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RST_RCV_LANE_FIELD_NAME "rst_rcv_lane"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_HW_ADDR        20'b11011100010011010001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ADDR   30'b000000011011100010011010001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_NAME   "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_stat1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_WIDTH  64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_DEPTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_INT_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_POSITION       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_FIELD_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_stat1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_LOW_ADDR_WIDTH 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ADDR_RANGE     19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_READ_MASK      64'b0000000000000000000000000000000000000000000000011111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000010000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_WRITE_MASK     64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_WRITE_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_SET_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_CLEAR_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_TOGGLE_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RMASK  64'b0000000000000000000000000000000000000000000000011111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RESERVED_BIT_MASK      64'b1111111111111111111111111111111111111111111111100000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000011111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_POR_VALUE      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_INTERNAL_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_EXTERNAL_DECODE_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIASED_FROM   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ZERO_TIME_OMNI 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_HW_ACC_JTAG_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_HW_ACC_JTAG_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_HW_ACC_SBUS_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_HW_ACC_SBUS_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_HW_ACC_RAP_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_HW_ACC_RAP_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_NUM_FIELDS     2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIGN_STS_FID  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIGN_STS_SLC  16:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIGN_STS_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIGN_STS_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIGN_STS_POSITION     16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIGN_STS_FMASK        64'b0000000000000000000000000000000000000000000000010000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIGN_STS_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000010000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIGN_STS_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIGN_STS_FIELD_NAME   "align_sts"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RX_PHY_STS_FID 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RX_PHY_STS_SLC 15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RX_PHY_STS_WIDTH       16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RX_PHY_STS_INT_SLC     15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RX_PHY_STS_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RX_PHY_STS_FMASK       64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RX_PHY_STS_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RX_PHY_STS_POR_VALUE   16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RX_PHY_STS_FIELD_NAME  "rx_phy_sts"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_HW_ADDR        20'b11011100010011010010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_ADDR   30'b000000011011100010011010010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_NAME   "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_stat2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_WIDTH  64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_DEPTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_INT_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_POSITION       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_FIELD_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_stat2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_LOW_ADDR_WIDTH 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_ADDR_RANGE     19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_READ_MASK      64'b0000000000000000000000000000000000001111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_READ_ONLY_MASK 64'b0000000000000000000000000000000000001111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_WRITE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_WRITE_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_SET_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_CLEAR_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_TOGGLE_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RMASK  64'b0000000000000000000000000000000000001111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RESERVED_BIT_MASK      64'b1111111111111111111111111111111111110000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_HW_LD_MASK     64'b0000000000000000000000000000000000001000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_POR_VALUE      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_INTERNAL_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_EXTERNAL_DECODE_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_ALIASED_FROM   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_ZERO_TIME_OMNI 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_HW_ACC_JTAG_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_HW_ACC_JTAG_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_HW_ACC_SBUS_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_HW_ACC_SBUS_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_HW_ACC_RAP_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_HW_ACC_RAP_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_NUM_FIELDS     7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_SCRAM_FID      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_SCRAM_SLC      27:27
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_SCRAM_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_SCRAM_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_SCRAM_POSITION 27
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_SCRAM_FMASK    64'b0000000000000000000000000000000000001000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_SCRAM_HW_LD_MASK       64'b0000000000000000000000000000000000001000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_SCRAM_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_SCRAM_FIELD_NAME       "rcv_dis_scram"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_EN_LOOPBACK_FID    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_EN_LOOPBACK_SLC    26:26
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_EN_LOOPBACK_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_EN_LOOPBACK_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_EN_LOOPBACK_POSITION       26
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_EN_LOOPBACK_FMASK  64'b0000000000000000000000000000000000000100000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_EN_LOOPBACK_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_EN_LOOPBACK_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_EN_LOOPBACK_FIELD_NAME     "rcv_en_loopback"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_LINK_FID       2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_LINK_SLC       25:25
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_LINK_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_LINK_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_LINK_POSITION  25
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_LINK_FMASK     64'b0000000000000000000000000000000000000010000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_LINK_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_LINK_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_LINK_FIELD_NAME        "rcv_dis_link"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_HOT_RST_FID        3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_HOT_RST_SLC        24:24
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_HOT_RST_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_HOT_RST_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_HOT_RST_POSITION   24
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_HOT_RST_FMASK      64'b0000000000000000000000000000000000000001000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_HOT_RST_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_HOT_RST_POR_VALUE  1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_HOT_RST_FIELD_NAME "rcv_hot_rst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DATA_RATE_FID      4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DATA_RATE_SLC      23:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DATA_RATE_WIDTH    8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DATA_RATE_INT_SLC  7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DATA_RATE_POSITION 16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DATA_RATE_FMASK    64'b0000000000000000000000000000000000000000111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DATA_RATE_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DATA_RATE_POR_VALUE        8'b00000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DATA_RATE_FIELD_NAME       "rcv_data_rate"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_FID        5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_SLC        15:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_WIDTH      8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_INT_SLC    7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_POSITION   8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_FMASK      64'b0000000000000000000000000000000000000000000000001111111100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_POR_VALUE  8'b00000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_FIELD_NAME "rcv_fts_num"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_FID       6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_SLC       7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_WIDTH     8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_INT_SLC   7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_FMASK     64'b0000000000000000000000000000000000000000000000000000000011111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_POR_VALUE 8'b00000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_FIELD_NAME        "rcv_link_num"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_HW_ADDR        20'b11011100010011010011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_ADDR   30'b000000011011100010011010011000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_NAME   "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_stat3"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_WIDTH  64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_DEPTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_INT_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_POSITION       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_FIELD_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_stat3"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_LOW_ADDR_WIDTH 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_ADDR_RANGE     19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_READ_MASK      64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_WRITE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_WRITE_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_SET_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_CLEAR_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_TOGGLE_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_RMASK  64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_RESERVED_BIT_MASK      64'b1111111111111111111111111111111111111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_POR_VALUE      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_INTERNAL_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_EXTERNAL_DECODE_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_ALIASED_FROM   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_ZERO_TIME_OMNI 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_HW_ACC_JTAG_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_HW_ACC_JTAG_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_HW_ACC_SBUS_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_HW_ACC_SBUS_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_HW_ACC_RAP_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_HW_ACC_RAP_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_NUM_FIELDS     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_FID      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_SLC      15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_WIDTH    16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_INT_SLC  15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_FMASK    64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_POR_VALUE        16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_FIELD_NAME       "byte_sync_sts"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_HW_ADDR  20'b11011100010011010100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_ADDR     30'b000000011011100010011010100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_int"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_WIDTH    64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_DEPTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_FIELD_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_int"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_LOW_ADDR_WIDTH   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_ADDR_RANGE       19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_READ_MASK        64'b0000000000000000000000000000000010000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_READ_ONLY_MASK   64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_WRITE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_WRITE_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_CLEAR_MASK       64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_TOGGLE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_RMASK    64'b0000000000000000000000000000000010000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_RESERVED_BIT_MASK        64'b1111111111111111111111111111111101111111111111111111000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_POR_VALUE        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INTERNAL_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_EXTERNAL_DECODE_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_ALIASED_FROM     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_ZERO_TIME_OMNI   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_HW_ACC_JTAG_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_HW_ACC_JTAG_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_HW_ACC_SBUS_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_HW_ACC_SBUS_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_HW_ACC_RAP_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_HW_ACC_RAP_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_NUM_FIELDS       5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_RCV_PHY_FID  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_RCV_PHY_SLC  31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_RCV_PHY_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_RCV_PHY_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_RCV_PHY_POSITION     31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_RCV_PHY_FMASK        64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_RCV_PHY_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_RCV_PHY_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_RCV_PHY_FIELD_NAME   "int_rcv_phy"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_UNUSED_FID   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_UNUSED_SLC   11:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_UNUSED_WIDTH 9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_UNUSED_INT_SLC       8:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_UNUSED_POSITION      3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_UNUSED_FMASK 64'b0000000000000000000000000000000000000000000000000000111111111000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_UNUSED_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000111111111000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_UNUSED_POR_VALUE     9'b000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_UNUSED_FIELD_NAME    "int_unused"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ALIGN_ERR_FID        2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ALIGN_ERR_SLC        2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ALIGN_ERR_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ALIGN_ERR_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ALIGN_ERR_POSITION   2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ALIGN_ERR_FMASK      64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ALIGN_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ALIGN_ERR_POR_VALUE  1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ALIGN_ERR_FIELD_NAME "int_align_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_OVRFLW_FID        3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_OVRFLW_SLC        1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_OVRFLW_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_OVRFLW_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_OVRFLW_POSITION   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_OVRFLW_FMASK      64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_OVRFLW_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_OVRFLW_POR_VALUE  1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_OVRFLW_FIELD_NAME "int_elstc_fifo_ovrflw"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_UNDRFLW_FID       4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_UNDRFLW_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_UNDRFLW_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_UNDRFLW_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_UNDRFLW_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_UNDRFLW_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_UNDRFLW_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_UNDRFLW_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_UNDRFLW_FIELD_NAME        "int_elstc_fifo_undrflw"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_HW_ADDR  20'b11011100010011010101
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_ADDR     30'b000000011011100010011010101000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_tst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_WIDTH    64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_DEPTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_INT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_FIELD_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_tst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_LOW_ADDR_WIDTH   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_ADDR_RANGE       19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_READ_MASK        64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_READ_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_WRITE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_WRITE_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_SET_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_CLEAR_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TOGGLE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_RMASK    64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_RESERVED_BIT_MASK        64'b1111111111111111111111111111111111111111111111111111000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_POR_VALUE        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_INTERNAL_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_EXTERNAL_DECODE_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_ALIASED_FROM     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_ZERO_TIME_OMNI   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_HW_ACC_JTAG_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_HW_ACC_JTAG_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_HW_ACC_SBUS_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_HW_ACC_SBUS_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_HW_ACC_RAP_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_HW_ACC_RAP_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_NUM_FIELDS       4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_UNUSED_FID   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_UNUSED_SLC   11:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_UNUSED_WIDTH 9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_UNUSED_INT_SLC       8:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_UNUSED_POSITION      3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_UNUSED_FMASK 64'b0000000000000000000000000000000000000000000000000000111111111000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_UNUSED_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000111111111000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_UNUSED_POR_VALUE     9'b000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_UNUSED_FIELD_NAME    "tst_unused"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ALIGN_ERR_FID        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ALIGN_ERR_SLC        2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ALIGN_ERR_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ALIGN_ERR_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ALIGN_ERR_POSITION   2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ALIGN_ERR_FMASK      64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ALIGN_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ALIGN_ERR_POR_VALUE  1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ALIGN_ERR_FIELD_NAME "tst_align_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_OVRFLW_FID        2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_OVRFLW_SLC        1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_OVRFLW_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_OVRFLW_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_OVRFLW_POSITION   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_OVRFLW_FMASK      64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_OVRFLW_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_OVRFLW_POR_VALUE  1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_OVRFLW_FIELD_NAME "tst_elstc_fifo_ovrflw"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_UNDRFLW_FID       3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_UNDRFLW_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_UNDRFLW_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_UNDRFLW_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_UNDRFLW_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_UNDRFLW_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_UNDRFLW_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_UNDRFLW_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_UNDRFLW_FIELD_NAME        "tst_elstc_fifo_undrflw"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_HW_ADDR  20'b11011100010011010110
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_ADDR     30'b000000011011100010011010110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_msk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_WIDTH    64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_DEPTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_INT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_FIELD_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_msk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_LOW_ADDR_WIDTH   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_ADDR_RANGE       19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_READ_MASK        64'b0000000000000000000000000000000010000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_READ_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_WRITE_MASK       64'b0000000000000000000000000000000010000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_WRITE_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_CLEAR_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_TOGGLE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_RMASK    64'b0000000000000000000000000000000010000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_RESERVED_BIT_MASK        64'b1111111111111111111111111111111101111111111111111111000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_POR_VALUE        64'b0000000000000000000000000000000010000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_INTERNAL_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_EXTERNAL_DECODE_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_ALIASED_FROM     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_ZERO_TIME_OMNI   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_HW_ACC_JTAG_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_HW_ACC_JTAG_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_HW_ACC_SBUS_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_HW_ACC_SBUS_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_HW_ACC_RAP_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_HW_ACC_RAP_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_NUM_FIELDS       5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_RCV_PHY_INT_FID      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_RCV_PHY_INT_SLC      31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_RCV_PHY_INT_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_RCV_PHY_INT_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_RCV_PHY_INT_POSITION 31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_RCV_PHY_INT_FMASK    64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_RCV_PHY_INT_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_RCV_PHY_INT_POR_VALUE        1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_RCV_PHY_INT_FIELD_NAME       "msk_rcv_phy_int"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_UNUSED_FID   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_UNUSED_SLC   11:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_UNUSED_WIDTH 9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_UNUSED_INT_SLC       8:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_UNUSED_POSITION      3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_UNUSED_FMASK 64'b0000000000000000000000000000000000000000000000000000111111111000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_UNUSED_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_UNUSED_POR_VALUE     9'b111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_UNUSED_FIELD_NAME    "msk_unused"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ALIGN_ERR_FID        2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ALIGN_ERR_SLC        2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ALIGN_ERR_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ALIGN_ERR_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ALIGN_ERR_POSITION   2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ALIGN_ERR_FMASK      64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ALIGN_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ALIGN_ERR_POR_VALUE  1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ALIGN_ERR_FIELD_NAME "msk_align_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_OVRFLW_FID        3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_OVRFLW_SLC        1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_OVRFLW_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_OVRFLW_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_OVRFLW_POSITION   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_OVRFLW_FMASK      64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_OVRFLW_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_OVRFLW_POR_VALUE  1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_OVRFLW_FIELD_NAME "msk_elstc_fifo_ovrflw"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_UNDRFLW_FID       4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_UNDRFLW_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_UNDRFLW_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_UNDRFLW_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_UNDRFLW_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_UNDRFLW_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_UNDRFLW_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_UNDRFLW_POR_VALUE 1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_UNDRFLW_FIELD_NAME        "msk_elstc_fifo_undrflw"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_HW_ADDR       20'b11011100010011100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_ADDR  30'b000000011011100010011100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_config"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_WIDTH 64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_DEPTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_INT_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FIELD_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_config"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_LOW_ADDR_WIDTH        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_ADDR_RANGE    19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_READ_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_READ_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_WRITE_MASK    64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_WRITE_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_SET_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_CLEAR_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_TOGGLE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_RESERVED_BIT_MASK     64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_POR_VALUE     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_INTERNAL_REG  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_EXTERNAL_DECODE_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_ALIASED_FROM  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_ZERO_TIME_OMNI        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_HW_ACC_JTAG_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_HW_ACC_JTAG_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_HW_ACC_SBUS_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_HW_ACC_SBUS_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_HW_ACC_RAP_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_HW_ACC_RAP_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_NUM_FIELDS    2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_RCVR_DET_FID     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_RCVR_DET_SLC     31:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_RCVR_DET_WIDTH   16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_RCVR_DET_INT_SLC 15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_RCVR_DET_POSITION        16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_RCVR_DET_FMASK   64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_RCVR_DET_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_RCVR_DET_POR_VALUE       16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_RCVR_DET_FIELD_NAME      "frce_rcvr_det"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_ELEC_IDLE_FID    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_ELEC_IDLE_SLC    15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_ELEC_IDLE_WIDTH  16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_ELEC_IDLE_INT_SLC        15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_ELEC_IDLE_POSITION       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_ELEC_IDLE_FMASK  64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_ELEC_IDLE_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_ELEC_IDLE_POR_VALUE      16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_ELEC_IDLE_FIELD_NAME     "frce_elec_idle"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_HW_ADDR 20'b11011100010011100001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_ADDR    30'b000000011011100010011100001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_stat"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_WIDTH   64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_DEPTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_INT_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_FIELD_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_stat"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_LOW_ADDR_WIDTH  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_ADDR_RANGE      19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_READ_MASK       64'b0000000000000000000000000000000011111111011111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_READ_ONLY_MASK  64'b0000000000000000000000000000000011111111011111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_WRITE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_RMASK   64'b0000000000000000000000000000000011111111011111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_RESERVED_BIT_MASK       64'b1111111111111111111111111111111100000000100000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_HW_LD_MASK      64'b0000000000000000000000000000000011111111011111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_POR_VALUE       64'b0000000000000000000000000000000001110011000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_INTERNAL_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_EXTERNAL_DECODE_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_ALIASED_FROM    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_ZERO_TIME_OMNI  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_HW_ACC_JTAG_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_HW_ACC_JTAG_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_HW_ACC_SBUS_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_HW_ACC_SBUS_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_HW_ACC_RAP_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_HW_ACC_RAP_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NUM_FIELDS      6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_FID       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_SLC       31:28
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_WIDTH     4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_INT_SLC   3:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_POSITION  28
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_FMASK     64'b0000000000000000000000000000000011110000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_HW_LD_MASK        64'b0000000000000000000000000000000011110000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_POR_VALUE 4'b0111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_FIELD_NAME        "neg_lane_wdth"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_FID      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_SLC      27:27
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_POSITION 27
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_FMASK    64'b0000000000000000000000000000000000001000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_HW_LD_MASK       64'b0000000000000000000000000000000000001000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_FIELD_NAME       "txphy_scram_en"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_REV_FID 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_REV_SLC 26:26
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_REV_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_REV_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_REV_POSITION    26
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_REV_FMASK       64'b0000000000000000000000000000000000000100000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_REV_HW_LD_MASK  64'b0000000000000000000000000000000000000100000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_REV_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_REV_FIELD_NAME  "tx_lane_rev"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_PAD_FID 3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_PAD_SLC 25:25
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_PAD_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_PAD_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_PAD_POSITION    25
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_PAD_FMASK       64'b0000000000000000000000000000000000000010000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_PAD_HW_LD_MASK  64'b0000000000000000000000000000000000000010000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_PAD_POR_VALUE   1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_PAD_FIELD_NAME  "tx_lane_pad"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LINK_PAD_FID 4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LINK_PAD_SLC 24:24
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LINK_PAD_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LINK_PAD_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LINK_PAD_POSITION    24
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LINK_PAD_FMASK       64'b0000000000000000000000000000000000000001000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LINK_PAD_HW_LD_MASK  64'b0000000000000000000000000000000000000001000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LINK_PAD_POR_VALUE   1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LINK_PAD_FIELD_NAME  "tx_link_pad"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_PHY_SMS_FID  5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_PHY_SMS_SLC  22:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_PHY_SMS_WIDTH        23
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_PHY_SMS_INT_SLC      22:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_PHY_SMS_POSITION     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_PHY_SMS_FMASK        64'b0000000000000000000000000000000000000000011111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_PHY_SMS_HW_LD_MASK   64'b0000000000000000000000000000000000000000011111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_PHY_SMS_POR_VALUE    23'b00000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_PHY_SMS_FIELD_NAME   "tx_phy_sms"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_HW_ADDR  20'b11011100010011100010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_ADDR     30'b000000011011100010011100010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_int"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_WIDTH    64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_DEPTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_FIELD_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_int"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_LOW_ADDR_WIDTH   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_ADDR_RANGE       19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_READ_MASK        64'b0000000000000000000000000000000010000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_READ_ONLY_MASK   64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_WRITE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_WRITE_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_CLEAR_MASK       64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_TOGGLE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_RMASK    64'b0000000000000000000000000000000010000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_RESERVED_BIT_MASK        64'b1111111111111111111111111111111101111111111111111111000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_POR_VALUE        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INTERNAL_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_EXTERNAL_DECODE_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_ALIASED_FROM     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_ZERO_TIME_OMNI   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_HW_ACC_JTAG_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_HW_ACC_JTAG_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_HW_ACC_SBUS_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_HW_ACC_SBUS_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_HW_ACC_RAP_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_HW_ACC_RAP_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_NUM_FIELDS       12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNMSK_FID    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNMSK_SLC    31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNMSK_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNMSK_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNMSK_POSITION       31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNMSK_FMASK  64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNMSK_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNMSK_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNMSK_FIELD_NAME     "int_unmsk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_IDLE_FID 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_IDLE_SLC 11:11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_IDLE_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_IDLE_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_IDLE_POSITION    11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_IDLE_FMASK       64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_IDLE_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_IDLE_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_IDLE_FIELD_NAME  "int_rcv_idle"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS2_FID  2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS2_SLC  10:10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS2_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS2_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS2_POSITION     10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS2_FMASK        64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS2_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS2_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS2_FIELD_NAME   "int_rcv_ts2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS1_FID  3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS1_SLC  9:9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS1_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS1_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS1_POSITION     9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS1_FMASK        64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS1_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS1_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS1_FIELD_NAME   "int_rcv_ts1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ERR_FID  4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ERR_SLC  8:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ERR_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ERR_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ERR_POSITION     8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ERR_FMASK        64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ERR_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ERR_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ERR_FIELD_NAME   "int_skp_err"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_BK2BK_FID   5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_BK2BK_SLC   7:7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_BK2BK_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_BK2BK_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_BK2BK_POSITION      7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_BK2BK_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_BK2BK_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_BK2BK_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_BK2BK_FIELD_NAME    "int_skp_done_bk2bk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ACK_DECR_FID     6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ACK_DECR_SLC     6:6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ACK_DECR_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ACK_DECR_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ACK_DECR_POSITION        6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ACK_DECR_FMASK   64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ACK_DECR_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ACK_DECR_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ACK_DECR_FIELD_NAME      "int_skp_ack_decr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_DECR_FID    7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_DECR_SLC    5:5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_DECR_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_DECR_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_DECR_POSITION       5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_DECR_FMASK  64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_DECR_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_DECR_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_DECR_FIELD_NAME     "int_skp_done_decr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_TRIG_FID 8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_TRIG_SLC 4:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_TRIG_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_TRIG_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_TRIG_POSITION    4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_TRIG_FMASK       64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_TRIG_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_TRIG_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_TRIG_FIELD_NAME  "int_skp_trig"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNUSED_2_FID 9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNUSED_2_SLC 3:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNUSED_2_WIDTH       2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNUSED_2_INT_SLC     1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNUSED_2_POSITION    2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNUSED_2_FMASK       64'b0000000000000000000000000000000000000000000000000000000000001100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNUSED_2_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000001100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNUSED_2_POR_VALUE   2'b00
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNUSED_2_FIELD_NAME  "int_unused_2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCVR_DET_VALID_FID   10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCVR_DET_VALID_SLC   1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCVR_DET_VALID_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCVR_DET_VALID_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCVR_DET_VALID_POSITION      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCVR_DET_VALID_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCVR_DET_VALID_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCVR_DET_VALID_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCVR_DET_VALID_FIELD_NAME    "int_rcvr_det_valid"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_TX_PAR_ERR_FID       11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_TX_PAR_ERR_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_TX_PAR_ERR_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_TX_PAR_ERR_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_TX_PAR_ERR_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_TX_PAR_ERR_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_TX_PAR_ERR_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_TX_PAR_ERR_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_TX_PAR_ERR_FIELD_NAME        "int_tx_par_err"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_HW_ADDR  20'b11011100010011100011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_ADDR     30'b000000011011100010011100011000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_tst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_WIDTH    64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_DEPTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_INT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_FIELD_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_tst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_LOW_ADDR_WIDTH   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_ADDR_RANGE       19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_READ_MASK        64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_READ_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_WRITE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_WRITE_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_SET_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_CLEAR_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TOGGLE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_RMASK    64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_RESERVED_BIT_MASK        64'b1111111111111111111111111111111111111111111111111111000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_POR_VALUE        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_INTERNAL_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_EXTERNAL_DECODE_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_ALIASED_FROM     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_ZERO_TIME_OMNI   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_HW_ACC_JTAG_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_HW_ACC_JTAG_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_HW_ACC_SBUS_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_HW_ACC_SBUS_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_HW_ACC_RAP_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_HW_ACC_RAP_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_NUM_FIELDS       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TST_TX_PHY_INT_FID       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TST_TX_PHY_INT_SLC       11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TST_TX_PHY_INT_WIDTH     12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TST_TX_PHY_INT_INT_SLC   11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TST_TX_PHY_INT_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TST_TX_PHY_INT_FMASK     64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TST_TX_PHY_INT_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TST_TX_PHY_INT_POR_VALUE 12'b000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TST_TX_PHY_INT_FIELD_NAME        "tst_tx_phy_int"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_HW_ADDR  20'b11011100010011100100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_ADDR     30'b000000011011100010011100100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_msk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_WIDTH    64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_DEPTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_INT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_FIELD_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_msk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_LOW_ADDR_WIDTH   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_ADDR_RANGE       19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_READ_MASK        64'b0000000000000000000000000000000010000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_READ_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_WRITE_MASK       64'b0000000000000000000000000000000010000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_WRITE_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_CLEAR_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_TOGGLE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_RMASK    64'b0000000000000000000000000000000010000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_RESERVED_BIT_MASK        64'b1111111111111111111111111111111101111111111111111111000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_POR_VALUE        64'b0000000000000000000000000000000010000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_INTERNAL_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_EXTERNAL_DECODE_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_ALIASED_FROM     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_ZERO_TIME_OMNI   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_HW_ACC_JTAG_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_HW_ACC_JTAG_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_HW_ACC_SBUS_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_HW_ACC_SBUS_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_HW_ACC_RAP_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_HW_ACC_RAP_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_NUM_FIELDS       2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_GLOBL_INT_FID        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_GLOBL_INT_SLC        31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_GLOBL_INT_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_GLOBL_INT_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_GLOBL_INT_POSITION   31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_GLOBL_INT_FMASK      64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_GLOBL_INT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_GLOBL_INT_POR_VALUE  1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_GLOBL_INT_FIELD_NAME "msk_globl_int"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_IMPLEM_INT_FID       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_IMPLEM_INT_SLC       11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_IMPLEM_INT_WIDTH     12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_IMPLEM_INT_INT_SLC   11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_IMPLEM_INT_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_IMPLEM_INT_FMASK     64'b0000000000000000000000000000000000000000000000000000111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_IMPLEM_INT_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_IMPLEM_INT_POR_VALUE 12'b111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_IMPLEM_INT_FIELD_NAME        "msk_implem_int"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_HW_ADDR        20'b11011100010011100101
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_ADDR   30'b000000011011100010011100101000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_NAME   "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_sts_2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_WIDTH  64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_DEPTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_INT_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_POSITION       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_FIELD_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_sts_2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_LOW_ADDR_WIDTH 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_ADDR_RANGE     19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_READ_MASK      64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_READ_ONLY_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_WRITE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_WRITE_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_SET_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_CLEAR_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_TOGGLE_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RMASK  64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RESERVED_BIT_MASK      64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_HW_LD_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_POR_VALUE      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_INTERNAL_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_EXTERNAL_DECODE_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_ALIASED_FROM   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_ZERO_TIME_OMNI 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_HW_ACC_JTAG_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_HW_ACC_JTAG_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_HW_ACC_SBUS_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_HW_ACC_SBUS_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_HW_ACC_RAP_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_HW_ACC_RAP_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_NUM_FIELDS     2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_STS_FID       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_STS_SLC       31:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_STS_WIDTH     16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_STS_INT_SLC   15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_STS_POSITION  16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_STS_FMASK     64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_STS_HW_LD_MASK        64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_STS_POR_VALUE 16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_STS_FIELD_NAME        "recv_det_sts"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_RAW_STS_FID   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_RAW_STS_SLC   15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_RAW_STS_WIDTH 16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_RAW_STS_INT_SLC       15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_RAW_STS_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_RAW_STS_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_RAW_STS_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_RAW_STS_POR_VALUE     16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_RAW_STS_FIELD_NAME    "recv_det_raw_sts"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HW_ADDR       20'b11011100010011110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_ADDR  30'b000000011011100010011110000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_WIDTH 64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_DEPTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_INT_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_FIELD_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LOW_ADDR_WIDTH        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_ADDR_RANGE    19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_READ_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_READ_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_WRITE_MASK    64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_WRITE_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_SET_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_CLEAR_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_TOGGLE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_RESERVED_BIT_MASK     64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_POR_VALUE     64'b0000000000000000000000000000000000000000000000000001100100000101
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_INTERNAL_REG  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_EXTERNAL_DECODE_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_ALIASED_FROM  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_ZERO_TIME_OMNI        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HW_ACC_JTAG_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HW_ACC_JTAG_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HW_ACC_SBUS_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HW_ACC_SBUS_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HW_ACC_RAP_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HW_ACC_RAP_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_NUM_FIELDS    6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_TST_FID 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_TST_SLC 31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_TST_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_TST_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_TST_POSITION    31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_TST_FMASK       64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_TST_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_TST_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_TST_FIELD_NAME  "ltssm_tst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_UNUSED_CNTL_FID       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_UNUSED_CNTL_SLC       30:18
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_UNUSED_CNTL_WIDTH     13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_UNUSED_CNTL_INT_SLC   12:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_UNUSED_CNTL_POSITION  18
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_UNUSED_CNTL_FMASK     64'b0000000000000000000000000000000001111111111111000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_UNUSED_CNTL_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_UNUSED_CNTL_POR_VALUE 13'b0000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_UNUSED_CNTL_FIELD_NAME        "unused_cntl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LPBK_MSTR_FID 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LPBK_MSTR_SLC 17:17
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LPBK_MSTR_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LPBK_MSTR_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LPBK_MSTR_POSITION    17
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LPBK_MSTR_FMASK       64'b0000000000000000000000000000000000000000000000100000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LPBK_MSTR_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LPBK_MSTR_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LPBK_MSTR_FIELD_NAME  "lpbk_mstr"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HI_DATA_SUP_FID       3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HI_DATA_SUP_SLC       16:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HI_DATA_SUP_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HI_DATA_SUP_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HI_DATA_SUP_POSITION  16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HI_DATA_SUP_FMASK     64'b0000000000000000000000000000000000000000000000010000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HI_DATA_SUP_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HI_DATA_SUP_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HI_DATA_SUP_FIELD_NAME        "hi_data_sup"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_8_TO_FID        4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_8_TO_SLC        15:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_8_TO_WIDTH      8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_8_TO_INT_SLC    7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_8_TO_POSITION   8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_8_TO_FMASK      64'b0000000000000000000000000000000000000000000000001111111100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_8_TO_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_8_TO_POR_VALUE  8'b00011001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_8_TO_FIELD_NAME "ltssm_8_to"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_20_TO_FID       5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_20_TO_SLC       7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_20_TO_WIDTH     8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_20_TO_INT_SLC   7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_20_TO_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_20_TO_FMASK     64'b0000000000000000000000000000000000000000000000000000000011111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_20_TO_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_20_TO_POR_VALUE 8'b00000101
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_20_TO_FIELD_NAME        "ltssm_20_to"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_HW_ADDR       20'b11011100010011110001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_ADDR  30'b000000011011100010011110001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_WIDTH 64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_DEPTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_INT_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_FIELD_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LOW_ADDR_WIDTH        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_ADDR_RANGE    19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_READ_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_READ_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_WRITE_MASK    64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_WRITE_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_SET_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_CLEAR_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_TOGGLE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_RESERVED_BIT_MASK     64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_POR_VALUE     64'b0000000000000000000000000000000000000000001011011100011011000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_INTERNAL_REG  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_EXTERNAL_DECODE_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_ALIASED_FROM  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_ZERO_TIME_OMNI        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_HW_ACC_JTAG_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_HW_ACC_JTAG_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_HW_ACC_SBUS_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_HW_ACC_SBUS_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_HW_ACC_RAP_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_HW_ACC_RAP_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_NUM_FIELDS    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LTSSM_12_TO_FID       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LTSSM_12_TO_SLC       31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LTSSM_12_TO_WIDTH     32
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LTSSM_12_TO_INT_SLC   31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LTSSM_12_TO_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LTSSM_12_TO_FMASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LTSSM_12_TO_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LTSSM_12_TO_POR_VALUE 32'b00000000001011011100011011000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LTSSM_12_TO_FIELD_NAME        "ltssm_12_to"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_HW_ADDR       20'b11011100010011110010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_ADDR  30'b000000011011100010011110010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config3"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_WIDTH 64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_DEPTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_INT_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_FIELD_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config3"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LOW_ADDR_WIDTH        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_ADDR_RANGE    19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_READ_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_READ_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_WRITE_MASK    64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_WRITE_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_SET_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_CLEAR_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_TOGGLE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_RESERVED_BIT_MASK     64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_POR_VALUE     64'b0000000000000000000000000000000000000000000001111010000100100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_INTERNAL_REG  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_EXTERNAL_DECODE_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_ALIASED_FROM  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_ZERO_TIME_OMNI        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_HW_ACC_JTAG_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_HW_ACC_JTAG_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_HW_ACC_SBUS_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_HW_ACC_SBUS_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_HW_ACC_RAP_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_HW_ACC_RAP_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_NUM_FIELDS    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LTSSM_2_TO_FID        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LTSSM_2_TO_SLC        31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LTSSM_2_TO_WIDTH      32
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LTSSM_2_TO_INT_SLC    31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LTSSM_2_TO_POSITION   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LTSSM_2_TO_FMASK      64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LTSSM_2_TO_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LTSSM_2_TO_POR_VALUE  32'b00000000000001111010000100100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LTSSM_2_TO_FIELD_NAME "ltssm_2_to"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_HW_ADDR       20'b11011100010011110011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_ADDR  30'b000000011011100010011110011000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config4"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_WIDTH 64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DEPTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_INT_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_FIELD_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config4"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LOW_ADDR_WIDTH        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_ADDR_RANGE    19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_READ_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_READ_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_WRITE_MASK    64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_WRITE_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_SET_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_CLEAR_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TOGGLE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_RESERVED_BIT_MASK     64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_POR_VALUE     64'b0000000000000000000000000000000000000000000000101000110000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_INTERNAL_REG  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_EXTERNAL_DECODE_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_ALIASED_FROM  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_ZERO_TIME_OMNI        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_HW_ACC_JTAG_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_HW_ACC_JTAG_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_HW_ACC_SBUS_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_HW_ACC_SBUS_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_HW_ACC_RAP_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_HW_ACC_RAP_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_NUM_FIELDS    4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TRN_CNTRL_FID 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TRN_CNTRL_SLC 31:24
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TRN_CNTRL_WIDTH       8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TRN_CNTRL_INT_SLC     7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TRN_CNTRL_POSITION    24
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TRN_CNTRL_FMASK       64'b0000000000000000000000000000000011111111000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TRN_CNTRL_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TRN_CNTRL_POR_VALUE   8'b00000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TRN_CNTRL_FIELD_NAME  "trn_cntrl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DATA_RATE_FID 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DATA_RATE_SLC 23:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DATA_RATE_WIDTH       8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DATA_RATE_INT_SLC     7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DATA_RATE_POSITION    16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DATA_RATE_FMASK       64'b0000000000000000000000000000000000000000111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DATA_RATE_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DATA_RATE_POR_VALUE   8'b00000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DATA_RATE_FIELD_NAME  "data_rate"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_N_FTS_FID     2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_N_FTS_SLC     15:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_N_FTS_WIDTH   8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_N_FTS_INT_SLC 7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_N_FTS_POSITION        8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_N_FTS_FMASK   64'b0000000000000000000000000000000000000000000000001111111100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_N_FTS_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_N_FTS_POR_VALUE       8'b10001100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_N_FTS_FIELD_NAME      "n_fts"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LNK_NUM_FID   3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LNK_NUM_SLC   7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LNK_NUM_WIDTH 8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LNK_NUM_INT_SLC       7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LNK_NUM_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LNK_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000000011111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LNK_NUM_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LNK_NUM_POR_VALUE     8'b00000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LNK_NUM_FIELD_NAME    "lnk_num"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_HW_ADDR       20'b11011100010011110100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_ADDR  30'b000000011011100010011110100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config5"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_WIDTH 64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_DEPTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_INT_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_FIELD_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config5"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LOW_ADDR_WIDTH        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_ADDR_RANGE    19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_READ_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_READ_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_WRITE_MASK    64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_WRITE_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_SET_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_CLEAR_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TOGGLE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RESERVED_BIT_MASK     64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POR_VALUE     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_INTERNAL_REG  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_EXTERNAL_DECODE_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_ALIASED_FROM  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_ZERO_TIME_OMNI        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_HW_ACC_JTAG_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_HW_ACC_JTAG_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_HW_ACC_SBUS_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_HW_ACC_SBUS_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_HW_ACC_RAP_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_HW_ACC_RAP_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_NUM_FIELDS    13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL2_FID      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL2_SLC      31:13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL2_WIDTH    19
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL2_INT_SLC  18:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL2_POSITION 13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL2_FMASK    64'b0000000000000000000000000000000011111111111111111110000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL2_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL2_POR_VALUE        19'b0000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL2_FIELD_NAME       "unused_cntl2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RCV_DET_TST_MODE_FID  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RCV_DET_TST_MODE_SLC  12:12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RCV_DET_TST_MODE_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RCV_DET_TST_MODE_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RCV_DET_TST_MODE_POSITION     12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RCV_DET_TST_MODE_FMASK        64'b0000000000000000000000000000000000000000000000000001000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RCV_DET_TST_MODE_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RCV_DET_TST_MODE_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RCV_DET_TST_MODE_FIELD_NAME   "rcv_det_tst_mode"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POLL_CMPLNC_DIS_FID   2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POLL_CMPLNC_DIS_SLC   11:11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POLL_CMPLNC_DIS_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POLL_CMPLNC_DIS_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POLL_CMPLNC_DIS_POSITION      11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POLL_CMPLNC_DIS_FMASK 64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POLL_CMPLNC_DIS_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POLL_CMPLNC_DIS_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POLL_CMPLNC_DIS_FIELD_NAME    "poll_cmplnc_dis"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TX_IDLE_TX_FTS_FID    3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TX_IDLE_TX_FTS_SLC    10:10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TX_IDLE_TX_FTS_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TX_IDLE_TX_FTS_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TX_IDLE_TX_FTS_POSITION       10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TX_IDLE_TX_FTS_FMASK  64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TX_IDLE_TX_FTS_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TX_IDLE_TX_FTS_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TX_IDLE_TX_FTS_FIELD_NAME     "tx_idle_tx_fts"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RX_FTS_RVR_LK_FID     4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RX_FTS_RVR_LK_SLC     9:9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RX_FTS_RVR_LK_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RX_FTS_RVR_LK_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RX_FTS_RVR_LK_POSITION        9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RX_FTS_RVR_LK_FMASK   64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RX_FTS_RVR_LK_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RX_FTS_RVR_LK_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RX_FTS_RVR_LK_FIELD_NAME      "rx_fts_rvr_lk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL1_FID      5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL1_SLC      8:7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL1_WIDTH    2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL1_INT_SLC  1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL1_POSITION 7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL1_FMASK    64'b0000000000000000000000000000000000000000000000000000000110000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL1_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL1_POR_VALUE        2'b00
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL1_FIELD_NAME       "unused_cntl1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_ACTIVE_FID 6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_ACTIVE_SLC 6:6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_ACTIVE_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_ACTIVE_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_ACTIVE_POSITION    6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_ACTIVE_FMASK       64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_ACTIVE_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_ACTIVE_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_ACTIVE_FIELD_NAME  "lpbk_entry_active"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_EXIT_FID   7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_EXIT_SLC   5:5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_EXIT_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_EXIT_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_EXIT_POSITION      5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_EXIT_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_EXIT_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_EXIT_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_EXIT_FIELD_NAME    "lpbk_entry_exit"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ACTIVE_EXIT_FID  8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ACTIVE_EXIT_SLC  4:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ACTIVE_EXIT_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ACTIVE_EXIT_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ACTIVE_EXIT_POSITION     4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ACTIVE_EXIT_FMASK        64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ACTIVE_EXIT_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ACTIVE_EXIT_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ACTIVE_EXIT_FIELD_NAME   "lpbk_active_exit"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L1_IDLE_RCVRY_LK_FID  9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L1_IDLE_RCVRY_LK_SLC  3:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L1_IDLE_RCVRY_LK_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L1_IDLE_RCVRY_LK_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L1_IDLE_RCVRY_LK_POSITION     3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L1_IDLE_RCVRY_LK_FMASK        64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L1_IDLE_RCVRY_LK_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L1_IDLE_RCVRY_LK_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L1_IDLE_RCVRY_LK_FIELD_NAME   "l1_idle_rcvry_lk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_TRN_CNTRL_RST_FID  10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_TRN_CNTRL_RST_SLC  2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_TRN_CNTRL_RST_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_TRN_CNTRL_RST_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_TRN_CNTRL_RST_POSITION     2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_TRN_CNTRL_RST_FMASK        64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_TRN_CNTRL_RST_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_TRN_CNTRL_RST_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_TRN_CNTRL_RST_FIELD_NAME   "l0_trn_cntrl_rst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_LPBK_FID   11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_LPBK_SLC   1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_LPBK_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_LPBK_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_LPBK_POSITION      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_LPBK_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_LPBK_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_LPBK_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_LPBK_FIELD_NAME    "l0_lpbk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL0_FID      12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL0_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL0_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL0_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL0_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL0_FMASK    64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL0_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL0_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL0_FIELD_NAME       "unused_cntl0"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_HW_ADDR 20'b11011100010011110101
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_ADDR    30'b000000011011100010011110101000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_stat1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_WIDTH   64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_DEPTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_INT_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_FIELD_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_stat1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LOW_ADDR_WIDTH  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_ADDR_RANGE      19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_READ_MASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_READ_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_WRITE_MASK      64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RMASK   64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RESERVED_BIT_MASK       64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_HW_LD_MASK      64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_INTERNAL_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_EXTERNAL_DECODE_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_ALIASED_FROM    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_ZERO_TIME_OMNI  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_HW_ACC_JTAG_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_HW_ACC_JTAG_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_HW_ACC_SBUS_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_HW_ACC_SBUS_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_HW_ACC_RAP_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_HW_ACC_RAP_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_NUM_FIELDS      9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_LN_EN_MSK_FID        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_LN_EN_MSK_SLC        31:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_LN_EN_MSK_WIDTH      16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_LN_EN_MSK_INT_SLC    15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_LN_EN_MSK_POSITION   16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_LN_EN_MSK_FMASK      64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_LN_EN_MSK_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_LN_EN_MSK_POR_VALUE  16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_LN_EN_MSK_FIELD_NAME "rx_ln_en_msk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_ALGN_CMD_FID 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_ALGN_CMD_SLC 15:15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_ALGN_CMD_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_ALGN_CMD_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_ALGN_CMD_POSITION    15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_ALGN_CMD_FMASK       64'b0000000000000000000000000000000000000000000000001000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_ALGN_CMD_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000001000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_ALGN_CMD_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_ALGN_CMD_FIELD_NAME  "rx_algn_cmd"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_MSTR_LN_SEL_FID 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_MSTR_LN_SEL_SLC 14:14
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_MSTR_LN_SEL_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_MSTR_LN_SEL_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_MSTR_LN_SEL_POSITION    14
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_MSTR_LN_SEL_FMASK       64'b0000000000000000000000000000000000000000000000000100000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_MSTR_LN_SEL_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000100000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_MSTR_LN_SEL_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_MSTR_LN_SEL_FIELD_NAME  "mstr_ln_sel"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_RX_FID   3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_RX_SLC   13:13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_RX_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_RX_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_RX_POSITION      13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_RX_FMASK 64'b0000000000000000000000000000000000000000000000000010000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_RX_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000010000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_RX_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_RX_FIELD_NAME    "lnk_ot_rx"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_TX_FID   4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_TX_SLC   12:12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_TX_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_TX_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_TX_POSITION      12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_TX_FMASK 64'b0000000000000000000000000000000000000000000000000001000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_TX_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000001000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_TX_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_TX_FIELD_NAME    "lnk_ot_tx"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_FID    5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_SLC    11:11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_POSITION       11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_FMASK  64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_FIELD_NAME     "ln_rvrsd"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_FID      6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_SLC      10:10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_POSITION 10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_FMASK    64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_FIELD_NAME       "lnk_up_dwn_sts"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_FID 7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_SLC 9:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_WIDTH       6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_INT_SLC     5:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_POSITION    4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_FMASK       64'b0000000000000000000000000000000000000000000000000000001111110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000001111110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_POR_VALUE   6'b000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_FIELD_NAME  "ltssm_state"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_FID       8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_SLC       3:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_WIDTH     4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_INT_SLC   3:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_FMASK     64'b0000000000000000000000000000000000000000000000000000000000001111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000001111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_POR_VALUE 4'b0000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_FIELD_NAME        "cnfg_lnk_wdth"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_HW_ADDR 20'b11011100010011110110
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_ADDR    30'b000000011011100010011110110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_stat2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_WIDTH   64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_DEPTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_INT_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_FIELD_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_stat2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_LOW_ADDR_WIDTH  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_ADDR_RANGE      19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_READ_MASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_READ_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_WRITE_MASK      64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RMASK   64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RESERVED_BIT_MASK       64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_HW_LD_MASK      64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_INTERNAL_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_EXTERNAL_DECODE_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_ALIASED_FROM    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_ZERO_TIME_OMNI  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_HW_ACC_JTAG_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_HW_ACC_JTAG_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_HW_ACC_SBUS_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_HW_ACC_SBUS_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_HW_ACC_RAP_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_HW_ACC_RAP_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_NUM_FIELDS      2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TX_CMD_TX_PHY_FID       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TX_CMD_TX_PHY_SLC       31:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TX_CMD_TX_PHY_WIDTH     16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TX_CMD_TX_PHY_INT_SLC   15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TX_CMD_TX_PHY_POSITION  16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TX_CMD_TX_PHY_FMASK     64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TX_CMD_TX_PHY_HW_LD_MASK        64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TX_CMD_TX_PHY_POR_VALUE 16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TX_CMD_TX_PHY_FIELD_NAME        "tx_cmd_tx_phy"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RX_CMD_RX_PHY_FID       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RX_CMD_RX_PHY_SLC       15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RX_CMD_RX_PHY_WIDTH     16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RX_CMD_RX_PHY_INT_SLC   15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RX_CMD_RX_PHY_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RX_CMD_RX_PHY_FMASK     64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RX_CMD_RX_PHY_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RX_CMD_RX_PHY_POR_VALUE 16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RX_CMD_RX_PHY_FIELD_NAME        "rx_cmd_rx_phy"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_HW_ADDR   20'b11011100010011110111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_ADDR      30'b000000011011100010011110111000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_int"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_WIDTH     64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_DEPTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_FIELD_NAME        "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_int"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_LOW_ADDR_WIDTH    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_ADDR_RANGE        19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_READ_MASK 64'b0000000000000000000000000000000010000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_READ_ONLY_MASK    64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_WRITE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_WRITE_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_SET_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_CLEAR_MASK        64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_TOGGLE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_RMASK     64'b0000000000000000000000000000000010000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_HW_LD_MASK        64'b0000000000000000000000000000000010000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INTERNAL_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_EXTERNAL_DECODE_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_ALIASED_FROM      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_ZERO_TIME_OMNI    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_HW_ACC_JTAG_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_HW_ACC_JTAG_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_HW_ACC_SBUS_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_HW_ACC_SBUS_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_HW_ACC_RAP_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_HW_ACC_RAP_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_NUM_FIELDS        17
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_ANY_FID       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_ANY_SLC       31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_ANY_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_ANY_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_ANY_POSITION  31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_ANY_FMASK     64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_ANY_HW_LD_MASK        64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_ANY_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_ANY_FIELD_NAME        "int_any"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SKIP_OS_FID   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SKIP_OS_SLC   15:15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SKIP_OS_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SKIP_OS_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SKIP_OS_POSITION      15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SKIP_OS_FMASK 64'b0000000000000000000000000000000000000000000000001000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SKIP_OS_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000001000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SKIP_OS_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SKIP_OS_FIELD_NAME    "int_skip_os"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_FTS_FID       2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_FTS_SLC       14:14
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_FTS_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_FTS_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_FTS_POSITION  14
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_FTS_FMASK     64'b0000000000000000000000000000000000000000000000000100000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_FTS_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000100000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_FTS_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_FTS_FIELD_NAME        "int_fts"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_RECOV_FID 3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_RECOV_SLC 13:13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_RECOV_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_RECOV_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_RECOV_POSITION    13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_RECOV_FMASK       64'b0000000000000000000000000000000000000000000000000010000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_RECOV_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000010000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_RECOV_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_RECOV_FIELD_NAME  "int_ts2_recov"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_8IDLE_DATA_FID        4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_8IDLE_DATA_SLC        12:12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_8IDLE_DATA_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_8IDLE_DATA_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_8IDLE_DATA_POSITION   12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_8IDLE_DATA_FMASK      64'b0000000000000000000000000000000000000000000000000001000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_8IDLE_DATA_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000001000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_8IDLE_DATA_POR_VALUE  1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_8IDLE_DATA_FIELD_NAME "int_8idle_data"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_IDLE_DATA_FID 5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_IDLE_DATA_SLC 11:11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_IDLE_DATA_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_IDLE_DATA_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_IDLE_DATA_POSITION    11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_IDLE_DATA_FMASK       64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_IDLE_DATA_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_IDLE_DATA_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_IDLE_DATA_FIELD_NAME  "int_idle_data"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_POLL_FID  6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_POLL_SLC  10:10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_POLL_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_POLL_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_POLL_POSITION     10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_POLL_FMASK        64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_POLL_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_POLL_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_POLL_FIELD_NAME   "int_tsx_poll"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_INV_FID   7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_INV_SLC   9:9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_INV_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_INV_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_INV_POSITION      9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_INV_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_INV_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_INV_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_INV_FIELD_NAME    "int_tsx_inv"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_EXIT_FID        8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_EXIT_SLC        8:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_EXIT_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_EXIT_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_EXIT_POSITION   8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_EXIT_FMASK      64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_EXIT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_EXIT_POR_VALUE  1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_EXIT_FIELD_NAME "int_eidle_exit"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_COMP_FID  9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_COMP_SLC  7:7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_COMP_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_COMP_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_COMP_POSITION     7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_COMP_FMASK        64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_COMP_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_COMP_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_COMP_FIELD_NAME   "int_tsx_comp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_LB_FID    10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_LB_SLC    6:6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_LB_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_LB_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_LB_POSITION       6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_LB_FMASK  64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_LB_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_LB_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_LB_FIELD_NAME     "int_tsx_lb"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_DIS_FID   11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_DIS_SLC   5:5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_DIS_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_DIS_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_DIS_POSITION      5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_DIS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_DIS_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_DIS_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_DIS_FIELD_NAME    "int_tsx_dis"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_RST_FID   12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_RST_SLC   4:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_RST_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_RST_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_RST_POSITION      4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_RST_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_RST_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_RST_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_RST_FIELD_NAME    "int_tsx_rst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_FID     13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_SLC     3:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_POSITION        3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_FMASK   64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_FIELD_NAME      "int_eidle"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_FID       14
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_SLC       2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_POSITION  2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_FIELD_NAME        "int_ts2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS1_FID       15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS1_SLC       1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS1_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS1_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS1_POSITION  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS1_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS1_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS1_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS1_FIELD_NAME        "int_ts1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_NONE_FID      16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_NONE_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_NONE_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_NONE_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_NONE_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_NONE_FMASK    64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_NONE_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_NONE_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_NONE_FIELD_NAME       "int_none"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_HW_ADDR   20'b11011100010011111000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_ADDR      30'b000000011011100010011111000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_tst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_WIDTH     64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_DEPTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_INT_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_FIELD_NAME        "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_tst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_LOW_ADDR_WIDTH    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_ADDR_RANGE        19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_READ_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_READ_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_WRITE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_WRITE_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_SET_MASK  64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_CLEAR_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TOGGLE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_RMASK     64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_INTERNAL_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_EXTERNAL_DECODE_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_ALIASED_FROM      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_ZERO_TIME_OMNI    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_HW_ACC_JTAG_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_HW_ACC_JTAG_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_HW_ACC_SBUS_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_HW_ACC_SBUS_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_HW_ACC_RAP_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_HW_ACC_RAP_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_NUM_FIELDS        16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_SKIP_OS_FID   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_SKIP_OS_SLC   15:15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_SKIP_OS_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_SKIP_OS_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_SKIP_OS_POSITION      15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_SKIP_OS_FMASK 64'b0000000000000000000000000000000000000000000000001000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_SKIP_OS_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000001000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_SKIP_OS_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_SKIP_OS_FIELD_NAME    "tst_skip_os"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_FTS_FID       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_FTS_SLC       14:14
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_FTS_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_FTS_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_FTS_POSITION  14
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_FTS_FMASK     64'b0000000000000000000000000000000000000000000000000100000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_FTS_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000100000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_FTS_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_FTS_FIELD_NAME        "tst_fts"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_RECOV_FID 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_RECOV_SLC 13:13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_RECOV_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_RECOV_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_RECOV_POSITION    13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_RECOV_FMASK       64'b0000000000000000000000000000000000000000000000000010000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_RECOV_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000010000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_RECOV_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_RECOV_FIELD_NAME  "tst_ts2_recov"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_8IDLE_DATA_FID        3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_8IDLE_DATA_SLC        12:12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_8IDLE_DATA_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_8IDLE_DATA_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_8IDLE_DATA_POSITION   12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_8IDLE_DATA_FMASK      64'b0000000000000000000000000000000000000000000000000001000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_8IDLE_DATA_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000001000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_8IDLE_DATA_POR_VALUE  1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_8IDLE_DATA_FIELD_NAME "tst_8idle_data"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_IDLE_DATA_FID 4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_IDLE_DATA_SLC 11:11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_IDLE_DATA_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_IDLE_DATA_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_IDLE_DATA_POSITION    11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_IDLE_DATA_FMASK       64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_IDLE_DATA_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_IDLE_DATA_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_IDLE_DATA_FIELD_NAME  "tst_idle_data"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_POLL_FID  5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_POLL_SLC  10:10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_POLL_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_POLL_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_POLL_POSITION     10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_POLL_FMASK        64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_POLL_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_POLL_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_POLL_FIELD_NAME   "tst_tsx_poll"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_INV_FID   6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_INV_SLC   9:9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_INV_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_INV_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_INV_POSITION      9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_INV_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_INV_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_INV_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_INV_FIELD_NAME    "tst_tsx_inv"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_EXIT_FID        7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_EXIT_SLC        8:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_EXIT_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_EXIT_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_EXIT_POSITION   8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_EXIT_FMASK      64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_EXIT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_EXIT_POR_VALUE  1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_EXIT_FIELD_NAME "tst_eidle_exit"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_COMP_FID  8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_COMP_SLC  7:7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_COMP_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_COMP_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_COMP_POSITION     7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_COMP_FMASK        64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_COMP_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_COMP_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_COMP_FIELD_NAME   "tst_tsx_comp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_LB_FID    9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_LB_SLC    6:6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_LB_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_LB_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_LB_POSITION       6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_LB_FMASK  64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_LB_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_LB_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_LB_FIELD_NAME     "tst_tsx_lb"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_DIS_FID   10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_DIS_SLC   5:5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_DIS_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_DIS_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_DIS_POSITION      5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_DIS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_DIS_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_DIS_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_DIS_FIELD_NAME    "tst_tsx_dis"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_RST_FID   11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_RST_SLC   4:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_RST_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_RST_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_RST_POSITION      4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_RST_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_RST_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_RST_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_RST_FIELD_NAME    "tst_tsx_rst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_FID     12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_SLC     3:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_POSITION        3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_FMASK   64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_FIELD_NAME      "tst_eidle"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_FID       13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_SLC       2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_POSITION  2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_FIELD_NAME        "tst_ts2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS1_FID       14
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS1_SLC       1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS1_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS1_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS1_POSITION  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS1_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS1_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS1_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS1_FIELD_NAME        "tst_ts1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_NONE_FID      15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_NONE_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_NONE_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_NONE_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_NONE_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_NONE_FMASK    64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_NONE_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_NONE_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_NONE_FIELD_NAME       "tst_none"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_HW_ADDR   20'b11011100010011111001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_ADDR      30'b000000011011100010011111001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_msk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_WIDTH     64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_DEPTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_INT_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_FIELD_NAME        "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_msk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_LOW_ADDR_WIDTH    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_ADDR_RANGE        19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_READ_MASK 64'b0000000000000000000000000000000010000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_READ_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_WRITE_MASK        64'b0000000000000000000000000000000010000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_WRITE_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_SET_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_CLEAR_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_TOGGLE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_RMASK     64'b0000000000000000000000000000000010000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_POR_VALUE 64'b0000000000000000000000000000000010000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_INTERNAL_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_EXTERNAL_DECODE_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_ALIASED_FROM      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_ZERO_TIME_OMNI    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_HW_ACC_JTAG_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_HW_ACC_JTAG_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_HW_ACC_SBUS_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_HW_ACC_SBUS_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_HW_ACC_RAP_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_HW_ACC_RAP_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_NUM_FIELDS        17
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_ANY_FID       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_ANY_SLC       31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_ANY_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_ANY_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_ANY_POSITION  31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_ANY_FMASK     64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_ANY_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_ANY_POR_VALUE 1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_ANY_FIELD_NAME        "msk_any"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_SKIP_OS_FID   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_SKIP_OS_SLC   15:15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_SKIP_OS_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_SKIP_OS_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_SKIP_OS_POSITION      15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_SKIP_OS_FMASK 64'b0000000000000000000000000000000000000000000000001000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_SKIP_OS_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_SKIP_OS_POR_VALUE     1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_SKIP_OS_FIELD_NAME    "msk_skip_os"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_FTS_FID       2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_FTS_SLC       14:14
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_FTS_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_FTS_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_FTS_POSITION  14
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_FTS_FMASK     64'b0000000000000000000000000000000000000000000000000100000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_FTS_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_FTS_POR_VALUE 1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_FTS_FIELD_NAME        "msk_fts"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_RECOV_FID 3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_RECOV_SLC 13:13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_RECOV_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_RECOV_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_RECOV_POSITION    13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_RECOV_FMASK       64'b0000000000000000000000000000000000000000000000000010000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_RECOV_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_RECOV_POR_VALUE   1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_RECOV_FIELD_NAME  "msk_ts2_recov"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_8IDLE_DATA_FID        4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_8IDLE_DATA_SLC        12:12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_8IDLE_DATA_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_8IDLE_DATA_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_8IDLE_DATA_POSITION   12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_8IDLE_DATA_FMASK      64'b0000000000000000000000000000000000000000000000000001000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_8IDLE_DATA_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_8IDLE_DATA_POR_VALUE  1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_8IDLE_DATA_FIELD_NAME "msk_8idle_data"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_IDLE_DATA_FID 5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_IDLE_DATA_SLC 11:11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_IDLE_DATA_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_IDLE_DATA_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_IDLE_DATA_POSITION    11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_IDLE_DATA_FMASK       64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_IDLE_DATA_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_IDLE_DATA_POR_VALUE   1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_IDLE_DATA_FIELD_NAME  "msk_idle_data"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_POLL_FID  6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_POLL_SLC  10:10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_POLL_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_POLL_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_POLL_POSITION     10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_POLL_FMASK        64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_POLL_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_POLL_POR_VALUE    1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_POLL_FIELD_NAME   "msk_tsx_poll"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_INV_FID   7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_INV_SLC   9:9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_INV_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_INV_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_INV_POSITION      9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_INV_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_INV_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_INV_POR_VALUE     1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_INV_FIELD_NAME    "msk_tsx_inv"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_EXIT_FID        8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_EXIT_SLC        8:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_EXIT_WIDTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_EXIT_INT_SLC    0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_EXIT_POSITION   8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_EXIT_FMASK      64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_EXIT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_EXIT_POR_VALUE  1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_EXIT_FIELD_NAME "msk_eidle_exit"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_COMP_FID  9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_COMP_SLC  7:7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_COMP_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_COMP_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_COMP_POSITION     7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_COMP_FMASK        64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_COMP_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_COMP_POR_VALUE    1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_COMP_FIELD_NAME   "msk_tsx_comp"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_LB_FID    10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_LB_SLC    6:6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_LB_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_LB_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_LB_POSITION       6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_LB_FMASK  64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_LB_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_LB_POR_VALUE      1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_LB_FIELD_NAME     "msk_tsx_lb"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_DIS_FID   11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_DIS_SLC   5:5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_DIS_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_DIS_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_DIS_POSITION      5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_DIS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_DIS_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_DIS_POR_VALUE     1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_DIS_FIELD_NAME    "msk_tsx_dis"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_RST_FID   12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_RST_SLC   4:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_RST_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_RST_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_RST_POSITION      4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_RST_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_RST_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_RST_POR_VALUE     1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_RST_FIELD_NAME    "msk_tsx_rst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_FID     13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_SLC     3:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_POSITION        3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_FMASK   64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_POR_VALUE       1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_FIELD_NAME      "msk_eidle"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_FID       14
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_SLC       2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_POSITION  2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_POR_VALUE 1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_FIELD_NAME        "msk_ts2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS1_FID       15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS1_SLC       1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS1_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS1_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS1_POSITION  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS1_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS1_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS1_POR_VALUE 1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS1_FIELD_NAME        "msk_ts1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_NONE_FID      16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_NONE_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_NONE_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_NONE_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_NONE_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_NONE_FMASK    64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_NONE_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_NONE_POR_VALUE        1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_NONE_FIELD_NAME       "msk_none"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_HW_ADDR    20'b11011100010011111010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_ADDR       30'b000000011011100010011111010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_stat_wr_en"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_WIDTH      64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_DEPTH      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_SLC        63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_INT_SLC    63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_POSITION   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_stat_wr_en"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LOW_ADDR_WIDTH     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_ADDR_RANGE 19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_READ_MASK  64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_READ_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RMASK      64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RESERVED_BIT_MASK  64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_POR_VALUE  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_INTERNAL_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_EXTERNAL_DECODE_REG        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_ALIASED_FROM       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_ZERO_TIME_OMNI     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_HW_ACC_JTAG_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_HW_ACC_JTAG_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_HW_ACC_SBUS_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_HW_ACC_SBUS_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_HW_ACC_RAP_RD      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_HW_ACC_RAP_WR      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_NUM_FIELDS 12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_UNUSED_CNTL_FID    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_UNUSED_CNTL_SLC    31:11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_UNUSED_CNTL_WIDTH  21
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_UNUSED_CNTL_INT_SLC        20:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_UNUSED_CNTL_POSITION       11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_UNUSED_CNTL_FMASK  64'b0000000000000000000000000000000011111111111111111111100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_UNUSED_CNTL_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_UNUSED_CNTL_POR_VALUE      21'b000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_UNUSED_CNTL_FIELD_NAME     "unused_cntl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TX_CMD_TX_PHY_FID  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TX_CMD_TX_PHY_SLC  10:10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TX_CMD_TX_PHY_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TX_CMD_TX_PHY_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TX_CMD_TX_PHY_POSITION     10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TX_CMD_TX_PHY_FMASK        64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TX_CMD_TX_PHY_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TX_CMD_TX_PHY_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TX_CMD_TX_PHY_FIELD_NAME   "tx_cmd_tx_phy"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_CMD_RX_PHY_FID  2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_CMD_RX_PHY_SLC  9:9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_CMD_RX_PHY_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_CMD_RX_PHY_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_CMD_RX_PHY_POSITION     9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_CMD_RX_PHY_FMASK        64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_CMD_RX_PHY_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_CMD_RX_PHY_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_CMD_RX_PHY_FIELD_NAME   "rx_cmd_rx_phy"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_LN_EN_MSK_FID   3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_LN_EN_MSK_SLC   8:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_LN_EN_MSK_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_LN_EN_MSK_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_LN_EN_MSK_POSITION      8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_LN_EN_MSK_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_LN_EN_MSK_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_LN_EN_MSK_POR_VALUE     1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_LN_EN_MSK_FIELD_NAME    "rx_ln_en_msk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_ALGN_CMD_FID    4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_ALGN_CMD_SLC    7:7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_ALGN_CMD_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_ALGN_CMD_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_ALGN_CMD_POSITION       7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_ALGN_CMD_FMASK  64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_ALGN_CMD_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_ALGN_CMD_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_ALGN_CMD_FIELD_NAME     "rx_algn_cmd"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_MSTR_LN_SEL_FID    5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_MSTR_LN_SEL_SLC    6:6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_MSTR_LN_SEL_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_MSTR_LN_SEL_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_MSTR_LN_SEL_POSITION       6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_MSTR_LN_SEL_FMASK  64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_MSTR_LN_SEL_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_MSTR_LN_SEL_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_MSTR_LN_SEL_FIELD_NAME     "mstr_ln_sel"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_RX_FID      6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_RX_SLC      5:5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_RX_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_RX_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_RX_POSITION 5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_RX_FMASK    64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_RX_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_RX_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_RX_FIELD_NAME       "lnk_ot_rx"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_TX_FID      7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_TX_SLC      4:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_TX_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_TX_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_TX_POSITION 4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_TX_FMASK    64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_TX_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_TX_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_TX_FIELD_NAME       "lnk_ot_tx"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LN_RVRSD_FID       8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LN_RVRSD_SLC       3:3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LN_RVRSD_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LN_RVRSD_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LN_RVRSD_POSITION  3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LN_RVRSD_FMASK     64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LN_RVRSD_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LN_RVRSD_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LN_RVRSD_FIELD_NAME        "ln_rvrsd"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_UP_DWN_STS_FID 9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_UP_DWN_STS_SLC 2:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_UP_DWN_STS_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_UP_DWN_STS_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_UP_DWN_STS_POSITION    2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_UP_DWN_STS_FMASK       64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_UP_DWN_STS_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_UP_DWN_STS_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_UP_DWN_STS_FIELD_NAME  "lnk_up_dwn_sts"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LTSSM_STATE_FID    10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LTSSM_STATE_SLC    1:1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LTSSM_STATE_WIDTH  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LTSSM_STATE_INT_SLC        0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LTSSM_STATE_POSITION       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LTSSM_STATE_FMASK  64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LTSSM_STATE_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LTSSM_STATE_POR_VALUE      1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LTSSM_STATE_FIELD_NAME     "ltssm_state"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CNFG_LNK_WDTH_FID  11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CNFG_LNK_WDTH_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CNFG_LNK_WDTH_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CNFG_LNK_WDTH_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CNFG_LNK_WDTH_POSITION     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CNFG_LNK_WDTH_FMASK        64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CNFG_LNK_WDTH_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CNFG_LNK_WDTH_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CNFG_LNK_WDTH_FIELD_NAME   "cnfg_lnk_wdth"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_HW_ADDR       20'b11011100010100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_ADDR  30'b000000011011100010100000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_WIDTH 64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_DEPTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_INT_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_FIELD_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LOW_ADDR_WIDTH        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_ADDR_RANGE    19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_READ_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_READ_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_WRITE_MASK    64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_WRITE_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_SET_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_CLEAR_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_TOGGLE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RESERVED_BIT_MASK     64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_POR_VALUE     64'b0000000000000000000000000000000000000000000010001001000000011001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_INTERNAL_REG  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_EXTERNAL_DECODE_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_ALIASED_FROM  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_ZERO_TIME_OMNI        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_HW_ACC_JTAG_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_HW_ACC_JTAG_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_HW_ACC_SBUS_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_HW_ACC_SBUS_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_HW_ACC_RAP_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_HW_ACC_RAP_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_NUM_FIELDS    11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL1_FID      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL1_SLC      31:28
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL1_WIDTH    4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL1_INT_SLC  3:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL1_POSITION 28
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL1_FMASK    64'b0000000000000000000000000000000011110000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL1_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL1_POR_VALUE        4'b0000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL1_FIELD_NAME       "unused_cntl1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_STM_SEL_FID   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_STM_SEL_SLC   27:24
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_STM_SEL_WIDTH 4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_STM_SEL_INT_SLC       3:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_STM_SEL_POSITION      24
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_STM_SEL_FMASK 64'b0000000000000000000000000000000000001111000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_STM_SEL_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_STM_SEL_POR_VALUE     4'b0000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_STM_SEL_FIELD_NAME    "stm_sel"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL2_FID      2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL2_SLC      23:22
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL2_WIDTH    2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL2_INT_SLC  1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL2_POSITION 22
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL2_FMASK    64'b0000000000000000000000000000000000000000110000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL2_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL2_POR_VALUE        2'b00
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL2_FIELD_NAME       "unused_cntl2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_SEL_FID      3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_SEL_SLC      21:20
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_SEL_WIDTH    2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_SEL_INT_SLC  1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_SEL_POSITION 20
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_SEL_FMASK    64'b0000000000000000000000000000000000000000001100000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_SEL_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_SEL_POR_VALUE        2'b00
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_SEL_FIELD_NAME       "rev_lpbk_sel"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_MODE_FID     4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_MODE_SLC     19:19
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_MODE_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_MODE_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_MODE_POSITION        19
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_MODE_FMASK   64'b0000000000000000000000000000000000000000000010000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_MODE_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_MODE_POR_VALUE       1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_MODE_FIELD_NAME      "rev_lpbk_mode"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_ENB_FID  5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_ENB_SLC  18:18
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_ENB_WIDTH        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_ENB_INT_SLC      0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_ENB_POSITION     18
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_ENB_FMASK        64'b0000000000000000000000000000000000000000000001000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_ENB_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_ENB_POR_VALUE    1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_ENB_FIELD_NAME   "lpbk_enb"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_MODE_SEL_FID     6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_MODE_SEL_SLC     17:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_MODE_SEL_WIDTH   2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_MODE_SEL_INT_SLC 1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_MODE_SEL_POSITION        16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_MODE_SEL_FMASK   64'b0000000000000000000000000000000000000000000000110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_MODE_SEL_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_MODE_SEL_POR_VALUE       2'b00
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_MODE_SEL_FIELD_NAME      "lpbk_mode_sel"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_FLTR_EN_FID     7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_FLTR_EN_SLC     15:15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_FLTR_EN_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_FLTR_EN_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_FLTR_EN_POSITION        15
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_FLTR_EN_FMASK   64'b0000000000000000000000000000000000000000000000001000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_FLTR_EN_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_FLTR_EN_POR_VALUE       1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_FLTR_EN_FIELD_NAME      "rxlos_fltr_en"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_ADJUST_FID      8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_ADJUST_SLC      14:12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_ADJUST_WIDTH    3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_ADJUST_INT_SLC  2:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_ADJUST_POSITION 12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_ADJUST_FMASK    64'b0000000000000000000000000000000000000000000000000111000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_ADJUST_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_ADJUST_POR_VALUE        3'b001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_ADJUST_FIELD_NAME       "rxlos_adjust"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_SMPL_RT_FID     9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_SMPL_RT_SLC     11:8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_SMPL_RT_WIDTH   4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_SMPL_RT_INT_SLC 3:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_SMPL_RT_POSITION        8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_SMPL_RT_FMASK   64'b0000000000000000000000000000000000000000000000000000111100000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_SMPL_RT_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_SMPL_RT_POR_VALUE       4'b0000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_SMPL_RT_FIELD_NAME      "rxlos_smpl_rt"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_THRSH_CN_FID    10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_THRSH_CN_SLC    7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_THRSH_CN_WIDTH  8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_THRSH_CN_INT_SLC        7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_THRSH_CN_POSITION       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_THRSH_CN_FMASK  64'b0000000000000000000000000000000000000000000000000000000011111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_THRSH_CN_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_THRSH_CN_POR_VALUE      8'b00011001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_THRSH_CN_FIELD_NAME     "rxlos_thrsh_cn"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_HW_ADDR       20'b11011100010100000001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_ADDR  30'b000000011011100010100000001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_WIDTH 64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_DEPTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_INT_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_FIELD_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_LOW_ADDR_WIDTH        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_ADDR_RANGE    19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_READ_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_READ_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_WRITE_MASK    64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_WRITE_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_SET_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_CLEAR_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TOGGLE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RESERVED_BIT_MASK     64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_POR_VALUE     64'b0000000000000000000000000000000010100001101000111110000101110101
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_INTERNAL_REG  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_EXTERNAL_DECODE_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_ALIASED_FROM  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_ZERO_TIME_OMNI        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_HW_ACC_JTAG_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_HW_ACC_JTAG_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_HW_ACC_SBUS_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_HW_ACC_SBUS_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_HW_ACC_RAP_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_HW_ACC_RAP_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_NUM_FIELDS    14
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VPULSE_CTL_FID     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VPULSE_CTL_SLC     31:30
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VPULSE_CTL_WIDTH   2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VPULSE_CTL_INT_SLC 1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VPULSE_CTL_POSITION        30
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VPULSE_CTL_FMASK   64'b0000000000000000000000000000000011000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VPULSE_CTL_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VPULSE_CTL_POR_VALUE       2'b10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VPULSE_CTL_FIELD_NAME      "tx_vpulse_ctl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VMUX_CTL_FID       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VMUX_CTL_SLC       29:28
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VMUX_CTL_WIDTH     2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VMUX_CTL_INT_SLC   1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VMUX_CTL_POSITION  28
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VMUX_CTL_FMASK     64'b0000000000000000000000000000000000110000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VMUX_CTL_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VMUX_CTL_POR_VALUE 2'b10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VMUX_CTL_FIELD_NAME        "tx_vmux_ctl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_RISE_FALL_FID      2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_RISE_FALL_SLC      27:25
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_RISE_FALL_WIDTH    3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_RISE_FALL_INT_SLC  2:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_RISE_FALL_POSITION 25
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_RISE_FALL_FMASK    64'b0000000000000000000000000000000000001110000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_RISE_FALL_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_RISE_FALL_POR_VALUE        3'b000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_RISE_FALL_FIELD_NAME       "tx_rise_fall"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PRE_EMPH_FID       3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PRE_EMPH_SLC       24:22
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PRE_EMPH_WIDTH     3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PRE_EMPH_INT_SLC   2:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PRE_EMPH_POSITION  22
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PRE_EMPH_FMASK     64'b0000000000000000000000000000000000000001110000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PRE_EMPH_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PRE_EMPH_POR_VALUE 3'b110
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PRE_EMPH_FIELD_NAME        "tx_pre_emph"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VSWNG_CTL_FID      4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VSWNG_CTL_SLC      21:18
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VSWNG_CTL_WIDTH    4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VSWNG_CTL_INT_SLC  3:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VSWNG_CTL_POSITION 18
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VSWNG_CTL_FMASK    64'b0000000000000000000000000000000000000000001111000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VSWNG_CTL_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VSWNG_CTL_POR_VALUE        4'b1000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VSWNG_CTL_FIELD_NAME       "tx_vswng_ctl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_ZERO_CTL_FID   5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_ZERO_CTL_SLC   17:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_ZERO_CTL_WIDTH 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_ZERO_CTL_INT_SLC       1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_ZERO_CTL_POSITION      16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_ZERO_CTL_FMASK 64'b0000000000000000000000000000000000000000000000110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_ZERO_CTL_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_ZERO_CTL_POR_VALUE     2'b11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_ZERO_CTL_FIELD_NAME    "tx_pll_zero_ctl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_POLE_CTL_FID   6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_POLE_CTL_SLC   15:14
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_POLE_CTL_WIDTH 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_POLE_CTL_INT_SLC       1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_POLE_CTL_POSITION      14
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_POLE_CTL_FMASK 64'b0000000000000000000000000000000000000000000000001100000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_POLE_CTL_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_POLE_CTL_POR_VALUE     2'b11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_POLE_CTL_FIELD_NAME    "tx_pll_pole_ctl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_ZERO_CTL_FID   7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_ZERO_CTL_SLC   13:12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_ZERO_CTL_WIDTH 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_ZERO_CTL_INT_SLC       1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_ZERO_CTL_POSITION      12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_ZERO_CTL_FMASK 64'b0000000000000000000000000000000000000000000000000011000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_ZERO_CTL_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_ZERO_CTL_POR_VALUE     2'b10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_ZERO_CTL_FIELD_NAME    "rx_pll_zero_ctl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_POLE_CTL_FID   8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_POLE_CTL_SLC   11:10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_POLE_CTL_WIDTH 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_POLE_CTL_INT_SLC       1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_POLE_CTL_POSITION      10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_POLE_CTL_FMASK 64'b0000000000000000000000000000000000000000000000000000110000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_POLE_CTL_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_POLE_CTL_POR_VALUE     2'b00
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_POLE_CTL_FIELD_NAME    "rx_pll_pole_ctl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_EQLIZR_CTL_FID     9
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_EQLIZR_CTL_SLC     9:6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_EQLIZR_CTL_WIDTH   4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_EQLIZR_CTL_INT_SLC 3:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_EQLIZR_CTL_POSITION        6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_EQLIZR_CTL_FMASK   64'b0000000000000000000000000000000000000000000000000000001111000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_EQLIZR_CTL_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_EQLIZR_CTL_POR_VALUE       4'b0101
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_EQLIZR_CTL_FIELD_NAME      "rx_eqlizr_ctl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_OHM_SEL_FID   10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_OHM_SEL_SLC   5:5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_OHM_SEL_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_OHM_SEL_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_OHM_SEL_POSITION      5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_OHM_SEL_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_OHM_SEL_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_OHM_SEL_POR_VALUE     1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_OHM_SEL_FIELD_NAME    "ohm_sel"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RTRIMEN_FID   11
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RTRIMEN_SLC   4:4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RTRIMEN_WIDTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RTRIMEN_INT_SLC       0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RTRIMEN_POSITION      4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RTRIMEN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RTRIMEN_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RTRIMEN_POR_VALUE     1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RTRIMEN_FIELD_NAME    "rtrimen"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_TERM_FID   12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_TERM_SLC   3:2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_TERM_WIDTH 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_TERM_INT_SLC       1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_TERM_POSITION      2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_TERM_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_TERM_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_TERM_POR_VALUE     2'b01
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_TERM_FIELD_NAME    "tx_term"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_TERM_FID   13
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_TERM_SLC   1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_TERM_WIDTH 2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_TERM_INT_SLC       1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_TERM_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_TERM_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_TERM_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_TERM_POR_VALUE     2'b01
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_TERM_FIELD_NAME    "rx_term"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_HW_ADDR       20'b11011100010100000010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_ADDR  30'b000000011011100010100000010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config3"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_WIDTH 64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_DEPTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_INT_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_FIELD_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config3"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_LOW_ADDR_WIDTH        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_ADDR_RANGE    19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_READ_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_READ_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_WRITE_MASK    64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_WRITE_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_SET_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_CLEAR_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TOGGLE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RESERVED_BIT_MASK     64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_POR_VALUE     64'b0000000000000000000000000000000000000000010001000000000111110100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_INTERNAL_REG  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_EXTERNAL_DECODE_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_ALIASED_FROM  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_ZERO_TIME_OMNI        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_HW_ACC_JTAG_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_HW_ACC_JTAG_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_HW_ACC_SBUS_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_HW_ACC_SBUS_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_HW_ACC_RAP_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_HW_ACC_RAP_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_NUM_FIELDS    8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_UNUSED_CNTL3_FID      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_UNUSED_CNTL3_SLC      31:27
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_UNUSED_CNTL3_WIDTH    5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_UNUSED_CNTL3_INT_SLC  4:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_UNUSED_CNTL3_POSITION 27
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_UNUSED_CNTL3_FMASK    64'b0000000000000000000000000000000011111000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_UNUSED_CNTL3_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_UNUSED_CNTL3_POR_VALUE        5'b00000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_UNUSED_CNTL3_FIELD_NAME       "unused_cntl3"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_OUT_BIAS_CTL_FID      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_OUT_BIAS_CTL_SLC      26:26
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_OUT_BIAS_CTL_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_OUT_BIAS_CTL_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_OUT_BIAS_CTL_POSITION 26
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_OUT_BIAS_CTL_FMASK    64'b0000000000000000000000000000000000000100000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_OUT_BIAS_CTL_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_OUT_BIAS_CTL_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_OUT_BIAS_CTL_FIELD_NAME       "out_bias_ctl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_RCV_DET_FID        2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_RCV_DET_SLC        25:24
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_RCV_DET_WIDTH      2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_RCV_DET_INT_SLC    1:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_RCV_DET_POSITION   24
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_RCV_DET_FMASK      64'b0000000000000000000000000000000000000011000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_RCV_DET_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_RCV_DET_POR_VALUE  2'b00
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_RCV_DET_FIELD_NAME "tx_rcv_det"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_HLF_RT_CTL_FID 3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_HLF_RT_CTL_SLC 23:23
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_HLF_RT_CTL_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_HLF_RT_CTL_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_HLF_RT_CTL_POSITION    23
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_HLF_RT_CTL_FMASK       64'b0000000000000000000000000000000000000000100000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_HLF_RT_CTL_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_HLF_RT_CTL_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_HLF_RT_CTL_FIELD_NAME  "tx_pll_hlf_rt_ctl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_FDBK_DIV_FID   4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_FDBK_DIV_SLC   22:20
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_FDBK_DIV_WIDTH 3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_FDBK_DIV_INT_SLC       2:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_FDBK_DIV_POSITION      20
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_FDBK_DIV_FMASK 64'b0000000000000000000000000000000000000000011100000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_FDBK_DIV_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_FDBK_DIV_POR_VALUE     3'b100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_FDBK_DIV_FIELD_NAME    "tx_pll_fdbk_div"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_HLF_RT_CTL_FID 5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_HLF_RT_CTL_SLC 19:19
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_HLF_RT_CTL_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_HLF_RT_CTL_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_HLF_RT_CTL_POSITION    19
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_HLF_RT_CTL_FMASK       64'b0000000000000000000000000000000000000000000010000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_HLF_RT_CTL_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_HLF_RT_CTL_POR_VALUE   1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_HLF_RT_CTL_FIELD_NAME  "rx_pll_hlf_rt_ctl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_FDBK_DIV_FID   6
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_FDBK_DIV_SLC   18:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_FDBK_DIV_WIDTH 3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_FDBK_DIV_INT_SLC       2:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_FDBK_DIV_POSITION      16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_FDBK_DIV_FMASK 64'b0000000000000000000000000000000000000000000001110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_FDBK_DIV_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_FDBK_DIV_POR_VALUE     3'b100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_FDBK_DIV_FIELD_NAME    "rx_pll_fdbk_div"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_BIT_LCK_TM_FID        7
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_BIT_LCK_TM_SLC        15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_BIT_LCK_TM_WIDTH      16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_BIT_LCK_TM_INT_SLC    15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_BIT_LCK_TM_POSITION   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_BIT_LCK_TM_FMASK      64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_BIT_LCK_TM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_BIT_LCK_TM_POR_VALUE  16'b0000000111110100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_BIT_LCK_TM_FIELD_NAME "bit_lck_tm"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_HW_ADDR       20'b11011100010100000011
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_ADDR  30'b000000011011100010100000011000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config4"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_WIDTH 64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_DEPTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INT_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_FIELD_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config4"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_LOW_ADDR_WIDTH        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_ADDR_RANGE    19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_READ_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_READ_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_WRITE_MASK    64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_WRITE_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_SET_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_CLEAR_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_TOGGLE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_RESERVED_BIT_MASK     64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_POR_VALUE     64'b0000000000000000000000000000000000000000000000011110100001001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INTERNAL_REG  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_EXTERNAL_DECODE_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_ALIASED_FROM  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_ZERO_TIME_OMNI        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_HW_ACC_JTAG_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_HW_ACC_JTAG_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_HW_ACC_SBUS_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_HW_ACC_SBUS_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_HW_ACC_RAP_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_HW_ACC_RAP_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_NUM_FIELDS    2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_UNUSED_CNTL_FID       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_UNUSED_CNTL_SLC       31:20
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_UNUSED_CNTL_WIDTH     12
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_UNUSED_CNTL_INT_SLC   11:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_UNUSED_CNTL_POSITION  20
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_UNUSED_CNTL_FMASK     64'b0000000000000000000000000000000011111111111100000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_UNUSED_CNTL_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_UNUSED_CNTL_POR_VALUE 12'b000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_UNUSED_CNTL_FIELD_NAME        "unused_cntl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INIT_TIME_FID 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INIT_TIME_SLC 19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INIT_TIME_WIDTH       20
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INIT_TIME_INT_SLC     19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INIT_TIME_POSITION    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INIT_TIME_FMASK       64'b0000000000000000000000000000000000000000000011111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INIT_TIME_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INIT_TIME_POR_VALUE   20'b00011110100001001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INIT_TIME_FIELD_NAME  "init_time"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_HW_ADDR  20'b11011100010100000100
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_ADDR     30'b000000011011100010100000100000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_NAME     "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_stat"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_WIDTH    64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_DEPTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_SLC      63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_INT_SLC  63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_POSITION 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_FIELD_NAME       "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_stat"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_LOW_ADDR_WIDTH   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_ADDR_RANGE       19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_READ_MASK        64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_READ_ONLY_MASK   64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_WRITE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_WRITE_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_CLEAR_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_TOGGLE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RMASK    64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RESERVED_BIT_MASK        64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_HW_LD_MASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_POR_VALUE        64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_INTERNAL_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_EXTERNAL_DECODE_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_ALIASED_FROM     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_ZERO_TIME_OMNI   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_HW_ACC_JTAG_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_HW_ACC_JTAG_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_HW_ACC_SBUS_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_HW_ACC_SBUS_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_HW_ACC_RAP_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_HW_ACC_RAP_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_NUM_FIELDS       2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RCV_ELECT_IDLE_FID       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RCV_ELECT_IDLE_SLC       31:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RCV_ELECT_IDLE_WIDTH     16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RCV_ELECT_IDLE_INT_SLC   15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RCV_ELECT_IDLE_POSITION  16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RCV_ELECT_IDLE_FMASK     64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RCV_ELECT_IDLE_HW_LD_MASK        64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RCV_ELECT_IDLE_POR_VALUE 16'b1111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RCV_ELECT_IDLE_FIELD_NAME        "rcv_elect_idle"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_BIT_SYNC_DN_FID  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_BIT_SYNC_DN_SLC  15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_BIT_SYNC_DN_WIDTH        16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_BIT_SYNC_DN_INT_SLC      15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_BIT_SYNC_DN_POSITION     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_BIT_SYNC_DN_FMASK        64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_BIT_SYNC_DN_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_BIT_SYNC_DN_POR_VALUE    16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_BIT_SYNC_DN_FIELD_NAME   "bit_sync_dn"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_HW_ADDR   20'b11011100010100000101
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_ADDR      30'b000000011011100010100000101000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_int"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_WIDTH     64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_DEPTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_FIELD_NAME        "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_int"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_LOW_ADDR_WIDTH    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_ADDR_RANGE        19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_READ_MASK 64'b0000000000000000000000000000000010000000111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_READ_ONLY_MASK    64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_WRITE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_WRITE_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_SET_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_CLEAR_MASK        64'b0000000000000000000000000000000000000000111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_TOGGLE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_RMASK     64'b0000000000000000000000000000000010000000111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_HW_LD_MASK        64'b0000000000000000000000000000000010000000111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INTERNAL_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_EXTERNAL_DECODE_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_ALIASED_FROM      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_ZERO_TIME_OMNI    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_HW_ACC_JTAG_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_HW_ACC_JTAG_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_HW_ACC_SBUS_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_HW_ACC_SBUS_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_HW_ACC_RAP_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_HW_ACC_RAP_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_NUM_FIELDS        3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_GLOBL_UNMSK_FID       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_GLOBL_UNMSK_SLC       31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_GLOBL_UNMSK_WIDTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_GLOBL_UNMSK_INT_SLC   0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_GLOBL_UNMSK_POSITION  31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_GLOBL_UNMSK_FMASK     64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_GLOBL_UNMSK_HW_LD_MASK        64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_GLOBL_UNMSK_POR_VALUE 1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_GLOBL_UNMSK_FIELD_NAME        "int_globl_unmsk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_UNUSED_FID    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_UNUSED_SLC    23:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_UNUSED_WIDTH  8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_UNUSED_INT_SLC        7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_UNUSED_POSITION       16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_UNUSED_FMASK  64'b0000000000000000000000000000000000000000111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_UNUSED_HW_LD_MASK     64'b0000000000000000000000000000000000000000111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_UNUSED_POR_VALUE      8'b00000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_UNUSED_FIELD_NAME     "int_unused"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_BYTE_SYNC_STS_FID     2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_BYTE_SYNC_STS_SLC     15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_BYTE_SYNC_STS_WIDTH   16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_BYTE_SYNC_STS_INT_SLC 15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_BYTE_SYNC_STS_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_BYTE_SYNC_STS_FMASK   64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_BYTE_SYNC_STS_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_BYTE_SYNC_STS_POR_VALUE       16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_BYTE_SYNC_STS_FIELD_NAME      "int_byte_sync_sts"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_HW_ADDR   20'b11011100010100000110
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_ADDR      30'b000000011011100010100000110000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_tst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_WIDTH     64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_DEPTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_INT_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_FIELD_NAME        "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_tst"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_LOW_ADDR_WIDTH    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_ADDR_RANGE        19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_READ_MASK 64'b0000000000000000000000000000000000000000111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_READ_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_WRITE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_WRITE_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_SET_MASK  64'b0000000000000000000000000000000000000000111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_CLEAR_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TOGGLE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_RMASK     64'b0000000000000000000000000000000000000000111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_HW_LD_MASK        64'b0000000000000000000000000000000000000000111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_INTERNAL_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_EXTERNAL_DECODE_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_ALIASED_FROM      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_ZERO_TIME_OMNI    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_HW_ACC_JTAG_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_HW_ACC_JTAG_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_HW_ACC_SBUS_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_HW_ACC_SBUS_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_HW_ACC_RAP_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_HW_ACC_RAP_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_NUM_FIELDS        2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_W1S_INT_FID   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_W1S_INT_SLC   23:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_W1S_INT_WIDTH 8
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_W1S_INT_INT_SLC       7:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_W1S_INT_POSITION      16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_W1S_INT_FMASK 64'b0000000000000000000000000000000000000000111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_W1S_INT_HW_LD_MASK    64'b0000000000000000000000000000000000000000111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_W1S_INT_POR_VALUE     8'b00000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_W1S_INT_FIELD_NAME    "tst_w1s_int"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_BSSS_INT_FID  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_BSSS_INT_SLC  15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_BSSS_INT_WIDTH        16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_BSSS_INT_INT_SLC      15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_BSSS_INT_POSITION     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_BSSS_INT_FMASK        64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_BSSS_INT_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_BSSS_INT_POR_VALUE    16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_BSSS_INT_FIELD_NAME   "tst_bsss_int"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_HW_ADDR   20'b11011100010100000111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_ADDR      30'b000000011011100010100000111000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_msk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_WIDTH     64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_DEPTH     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_INT_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_FIELD_NAME        "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_msk"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_LOW_ADDR_WIDTH    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_ADDR_RANGE        19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_READ_MASK 64'b0000000000000000000000000000000010000000111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_READ_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_WRITE_MASK        64'b0000000000000000000000000000000010000000111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_WRITE_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_SET_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_CLEAR_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_TOGGLE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_RMASK     64'b0000000000000000000000000000000010000000111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_POR_VALUE 64'b0000000000000000000000000000000010000000111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_INTERNAL_REG      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_EXTERNAL_DECODE_REG       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_ALIASED_FROM      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_ZERO_TIME_OMNI    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_HW_ACC_JTAG_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_HW_ACC_JTAG_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_HW_ACC_SBUS_RD    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_HW_ACC_SBUS_WR    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_HW_ACC_RAP_RD     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_HW_ACC_RAP_WR     1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_NUM_FIELDS        2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_GLOBL_INT_FID 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_GLOBL_INT_SLC 31:31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_GLOBL_INT_WIDTH       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_GLOBL_INT_INT_SLC     0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_GLOBL_INT_POSITION    31
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_GLOBL_INT_FMASK       64'b0000000000000000000000000000000010000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_GLOBL_INT_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_GLOBL_INT_POR_VALUE   1'b1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_GLOBL_INT_FIELD_NAME  "msk_globl_int"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_INT_FID       1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_INT_SLC       23:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_INT_WIDTH     24
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_INT_INT_SLC   23:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_INT_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_INT_FMASK     64'b0000000000000000000000000000000000000000111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_INT_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_INT_POR_VALUE 24'b111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_INT_FIELD_NAME        "msk_int"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_HW_ADDR 20'b11011100010100001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_ADDR    30'b000000011011100010100001000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_pdwn1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_WIDTH   64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_DEPTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_INT_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_FIELD_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_pdwn1"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_LOW_ADDR_WIDTH  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_ADDR_RANGE      19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_READ_MASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_READ_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_WRITE_MASK      64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RMASK   64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RESERVED_BIT_MASK       64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_INTERNAL_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_EXTERNAL_DECODE_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_ALIASED_FROM    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_ZERO_TIME_OMNI  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_HW_ACC_JTAG_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_HW_ACC_JTAG_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_HW_ACC_SBUS_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_HW_ACC_SBUS_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_HW_ACC_RAP_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_HW_ACC_RAP_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_NUM_FIELDS      2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TX_PWR_DN_FID   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TX_PWR_DN_SLC   31:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TX_PWR_DN_WIDTH 16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TX_PWR_DN_INT_SLC       15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TX_PWR_DN_POSITION      16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TX_PWR_DN_FMASK 64'b0000000000000000000000000000000011111111111111110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TX_PWR_DN_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TX_PWR_DN_POR_VALUE     16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TX_PWR_DN_FIELD_NAME    "tx_pwr_dn"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RX_PWR_DN_FID   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RX_PWR_DN_SLC   15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RX_PWR_DN_WIDTH 16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RX_PWR_DN_INT_SLC       15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RX_PWR_DN_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RX_PWR_DN_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RX_PWR_DN_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RX_PWR_DN_POR_VALUE     16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RX_PWR_DN_FIELD_NAME    "rx_pwr_dn"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_HW_ADDR 20'b11011100010100001001
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_ADDR    30'b000000011011100010100001001000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_pdwn2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_WIDTH   64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_DEPTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_SLC     63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_INT_SLC 63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_POSITION        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_FIELD_NAME      "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_pdwn2"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_LOW_ADDR_WIDTH  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_ADDR_RANGE      19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_READ_MASK       64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_READ_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_WRITE_MASK      64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RMASK   64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RESERVED_BIT_MASK       64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_INTERNAL_REG    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_EXTERNAL_DECODE_REG     0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_ALIASED_FROM    0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_ZERO_TIME_OMNI  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_HW_ACC_JTAG_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_HW_ACC_JTAG_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_HW_ACC_SBUS_RD  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_HW_ACC_SBUS_WR  1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_HW_ACC_RAP_RD   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_HW_ACC_RAP_WR   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_NUM_FIELDS      5
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_UNUSED_CNTL_FID 0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_UNUSED_CNTL_SLC 31:22
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_UNUSED_CNTL_WIDTH       10
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_UNUSED_CNTL_INT_SLC     9:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_UNUSED_CNTL_POSITION    22
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_UNUSED_CNTL_FMASK       64'b0000000000000000000000000000000011111111110000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_UNUSED_CNTL_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_UNUSED_CNTL_POR_VALUE   10'b0000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_UNUSED_CNTL_FIELD_NAME  "unused_cntl"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_CLK_BUF_FID      1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_CLK_BUF_SLC      21:21
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_CLK_BUF_WIDTH    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_CLK_BUF_INT_SLC  0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_CLK_BUF_POSITION 21
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_CLK_BUF_FMASK    64'b0000000000000000000000000000000000000000001000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_CLK_BUF_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_CLK_BUF_POR_VALUE        1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_CLK_BUF_FIELD_NAME       "pwr_dn_clk_buf"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_RES_TRIM_FID     2
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_RES_TRIM_SLC     20:20
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_RES_TRIM_WIDTH   1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_RES_TRIM_INT_SLC 0:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_RES_TRIM_POSITION        20
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_RES_TRIM_FMASK   64'b0000000000000000000000000000000000000000000100000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_RES_TRIM_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_RES_TRIM_POR_VALUE       1'b0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_RES_TRIM_FIELD_NAME      "pwr_dn_res_trim"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TX_PLL_PWR_D_FID        3
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TX_PLL_PWR_D_SLC        19:16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TX_PLL_PWR_D_WIDTH      4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TX_PLL_PWR_D_INT_SLC    3:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TX_PLL_PWR_D_POSITION   16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TX_PLL_PWR_D_FMASK      64'b0000000000000000000000000000000000000000000011110000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TX_PLL_PWR_D_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TX_PLL_PWR_D_POR_VALUE  4'b0000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TX_PLL_PWR_D_FIELD_NAME "tx_pll_pwr_d"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RXLOS_PWR_DN_FID        4
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RXLOS_PWR_DN_SLC        15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RXLOS_PWR_DN_WIDTH      16
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RXLOS_PWR_DN_INT_SLC    15:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RXLOS_PWR_DN_POSITION   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RXLOS_PWR_DN_FMASK      64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RXLOS_PWR_DN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RXLOS_PWR_DN_POR_VALUE  16'b0000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RXLOS_PWR_DN_FIELD_NAME "rxlos_pwr_dn"

//-------------------------------------------------------
//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5
//-------------------------------------------------------

`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_HW_ADDR       20'b11011100010100001010
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_ADDR  30'b000000011011100010100001010000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_NAME  "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config5"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_WIDTH 64
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_DEPTH 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_SLC   63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_INT_SLC       63:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_POSITION      0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_FIELD_NAME    "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config5"
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_LOW_ADDR_WIDTH        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_ADDR_RANGE    19:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_READ_MASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_READ_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_WRITE_MASK    64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_WRITE_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_SET_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_CLEAR_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_TOGGLE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_RESERVED_BIT_MASK     64'b1111111111111111111111111111111100000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_POR_VALUE     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_INTERNAL_REG  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_EXTERNAL_DECODE_REG   0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_ALIASED_FROM  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_ZERO_TIME_OMNI        0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_HW_ACC_JTAG_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_HW_ACC_JTAG_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_HW_ACC_SBUS_RD        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_HW_ACC_SBUS_WR        1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_HW_ACC_RAP_RD 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_HW_ACC_RAP_WR 1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_NUM_FIELDS    1
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_UNUSED_CNTL_FID       0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_UNUSED_CNTL_SLC       31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_UNUSED_CNTL_WIDTH     32
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_UNUSED_CNTL_INT_SLC   31:0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_UNUSED_CNTL_POSITION  0
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_UNUSED_CNTL_FMASK     64'b0000000000000000000000000000000011111111111111111111111111111111
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_UNUSED_CNTL_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_UNUSED_CNTL_POR_VALUE 32'b00000000000000000000000000000000
`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_UNUSED_CNTL_FIELD_NAME        "unused_cntl"


#endif