Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / niu / test_utils / vera / niu_txintr_utils.vr
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: niu_txintr_utils.vr
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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// ========== Copyright Header End ============================================
#include <vera_defines.vrh>
#include "niu_tx_descp.vrh"
#include "niu_int_dev.vrh"
#include "niu_int_mgr.vrh"
#include "cMesg.vrh"
extern Mesg be_msg;
// adding txdma intr dev class
class CNiuIntrDevTxDMAm extends DMAChannel {
event intr_rcvd;
bit [63:0] rd_data;
bit [63:0] wr_data;
integer count = 0;
integer exp_err;
task new(integer i, integer dev_id) {
super.new(i,"TX",dev_id);
trigger(OFF,intr_rcvd);
exp_err = 0;
}
function integer isr( ( bit[1:0] ldf_flags = 0) ) {
printf("Start In ISR id - %d LDF Flags - %x \n",super.dev_id,ldf_flags);
isr_done = 0;
SetPendingFlag();
trigger(ON,intr_rcvd);
if(ldf_flags[1] == 1'b1) {
// error interrupt detected
// read the tx_cs reg
Read_TxCs(rd_data);
be_msg.print(e_mesg_info,"TX_ISR","Tx_Cs_Rd","Value of TxCs %h for DMA %d\n",rd_data,this.id);
if(rd_data[7:0] == 8'h0) {
// err interrupt received but status bits not set
be_msg.print(e_mesg_error,"TX_ISR","err_flag_chk","Err intr rcvd, but err_stat zero for DMA %d\n",this.id);
} else {
if(!exp_err) {
if(rd_data[0])
be_msg.print(e_mesg_error,"TX_ISR","err_chk","Err intr rcvd, Pkt_Prt_Err status set for DMA %d\n",this.id);
else if(rd_data[1])
be_msg.print(e_mesg_error,"TX_ISR","err_chk","Err intr rcvd, Conf_Prt_Err status set for DMA %d\n",this.id);
else if(rd_data[2])
be_msg.print(e_mesg_error,"TX_ISR","err_chk","Err intr rcvd, Nack_PktRd_Err status set for DMA %d\n",this.id);
else if(rd_data[3])
be_msg.print(e_mesg_error,"TX_ISR","err_chk","Err intr rcvd, Nack_PrefRd_Err status set for DMA %d\n",this.id);
else if(rd_data[4])
be_msg.print(e_mesg_error,"TX_ISR","err_chk","Err intr rcvd, Pref_BufPar_Err status set for DMA %d\n",this.id);
else if(rd_data[5])
be_msg.print(e_mesg_error,"TX_ISR","err_chk","Err intr rcvd, Ring_Oflow_Err status set for DMA %d\n",this.id);
else if(rd_data[6])
be_msg.print(e_mesg_error,"TX_ISR","err_chk","Err intr rcvd, Pkt_Size_Err status set for DMA %d\n",this.id);
else if(rd_data[7])
be_msg.print(e_mesg_error,"TX_ISR","err_chk","Err intr rcvd, Mbox_Err status set for DMA %d\n",this.id);
} else {
if(rd_data[0])
be_msg.print(e_mesg_info,"TX_ISR","err_chk","Err intr rcvd, Pkt_Prt_Err status set for DMA %d\n",this.id);
else if(rd_data[1])
be_msg.print(e_mesg_info,"TX_ISR","err_chk","Err intr rcvd, Conf_Prt_Err status set for DMA %d\n",this.id);
else if(rd_data[2])
be_msg.print(e_mesg_info,"TX_ISR","err_chk","Err intr rcvd, Nack_PktRd_Err status set for DMA %d\n",this.id);
else if(rd_data[3])
be_msg.print(e_mesg_info,"TX_ISR","err_chk","Err intr rcvd, Nack_PrefRd_Err status set for DMA %d\n",this.id);
else if(rd_data[4])
be_msg.print(e_mesg_info,"TX_ISR","err_chk","Err intr rcvd, Pref_BufPar_Err status set for DMA %d\n",this.id);
else if(rd_data[5])
be_msg.print(e_mesg_info,"TX_ISR","err_chk","Err intr rcvd, Ring_Oflow_Err status set for DMA %d\n",this.id);
else if(rd_data[6])
be_msg.print(e_mesg_info,"TX_ISR","err_chk","Err intr rcvd, Pkt_Size_Err status set for DMA %d\n",this.id);
else if(rd_data[7])
be_msg.print(e_mesg_info,"TX_ISR","err_chk","Err intr rcvd, Mbox_Err status set for DMA %d\n",this.id);
}
reset_dma();
// trigger the event
isr_done = 1;
}
} else {
// read the tx_cs reg
Read_TxCs(rd_data);
be_msg.print(e_mesg_info,"TX_ISR","Tx_Cs_Rd","Value of TxCs %h for DMA %d\n",rd_data,this.id);
// printf("Value of TxCs from ISR %h\n",rd_data);
// re-enable mailbox update after this
wr_data = rd_data | 64'h2000_0000;
count++;
SetTxCs(wr_data);
// trigger the event
isr_done = 1;
}
ClrPendingFlag();
}
}